TCA6408

TCA6408 TI | Alldatasheet

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FEATURES

(TOP VIEW) 1 2 3 4 5 A B C D 8 9 PW PACKAGE (TOP VIEW) VCCI ADDR RESET GND V CCP SDA SCL INT RGT PACKAGE (TOP VIEW) 5 6 7 8 16 15 14 13 RESET SCL INT GND P4 P5 ADDRV CCI V CCP SDA DESCRIPTION/ORDERING INFORMATION TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 Operating Power-Supply Voltage Range of 5-V Tolerant I/O Ports 1.65 V to 5.5 V Active-Low Reset Input RESET Allows Bidirectional Voltage-Level Translation Open-Drain Active-Low Interrupt Output INT and GPIO Expansion Between 400-kHz Fast I C Bus 1.8-V SCL/SDA and 1.8-V, 2.5-V, Input/Output Configuration Register 3.3-V, or 5-V P Port Polarity Inversion Register 2.5-V SCL/SDA and 1.8-V, 2.5-V, Internal Power-On Reset 3.3-V, or 5-V P Port Power-Up With All Channels Configured as 3.3-V SCL/SDA and 1.8-V, 2.5-V, Inputs 3.3-V, or 5-V P Port No Glitch On Power-Up 5-V SCL/SDA and 1.8-V, 2.5-V, Noise Filter on SCL/SDA Inputs 3.3-V, or 5-V P Port Latched Outputs With High-Current Drive I C to Parallel Port Expander Maximum Capability for Directly Driving LEDs Low Standby Current Consumption of µ A Latch-Up Performance Exceeds 100 mA Per Schmitt-Trigger Action Allows Slow Input JESD 78, Class II Transition and Better Switching Noise ESD Protection Exceeds JESD Immunity at the SCL and SDA Inputs 2000-V Human-Body Model (A114-A) V hys 0.18 V Typ at 1.8 V 200-V Machine Model (A115-A) V hys 0.25 V Typ at 2.5 V 1000-V Charged-Device Model (C101) V hys 0.33 V Typ at 3.3 V V hys 0.5 V Typ at V This 8-bit I/O expander for the two-line bidirectional bus is designed to provide general-purpose remote I/O expansion for most microcontroller families via the I C interface [serial clock (SCL) and serial data (SDA)]. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. UNLESS OTHERWISE NOTED this document contains Copyright 2007, Texas Instruments Incorporated PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING QFN RGT Reel of 3000 TCA6408RGTR ZWP BGA ZXY (Pb-free) Reel of 2500 TCA6408ZXYR PH408 C to C Tube of TCA6408PW TSSOP PW PH408 Reel of 2000 TCA6408PWR (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com The major benefit of this device is its wide V CC range. It can operate from 1.65-V to 5.5-V on the P port side and on the SDA/SCL side. This allows the TCA6408 to interface with next-generation microprocessors and microcontrollers on the SDA/SCL side, where supply levels are dropping down to conserve power. In contrast to the dropping power supplies of microprocessors and microcontrollers, some PCB components such as LEDs remain at a 5-V power supply. The bidirectional voltage level translation in the TCA6408 is provided through V CC I V CC I should be connected to the V CC of the external SCL/SDA lines. This indicates the V CC level of the I C bus to the TCA6408. The voltage level on the P port of the TCA6408 is determined by V CCP The TCA6408 consists of one 8-bit configuration (input or output selection), input, output, and polarity inversion (active high) register. At power on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the input port register can be inverted with the polarity inversion register. All registers can be read by the system master. The system master can reset the TCA6408 in the event of a timeout or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I C/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part. The TCA6408 open-drain interrupt INT output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I C bus. Thus, the TCA6408 can remain a simple slave device. The device P port outputs have high-current sink capabilities for directly driving LEDs while consuming low device current. One hardware pin (ADDR) can be used to program and vary the fixed I C address and allow up to two devices to share the same I C bus or SMBus. Submit Documentation Feedback

www.ti.com TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 ZXY Terminal Assignments A RESET ADDR B GND N.C. (1) N.C. (1) V CCI C N.C. (1) INT N.C. (1) V CCP D SCL SDA (1) N.C. No internal connection TERMINAL FUNCTIONS PIN NUMBER NAME

DESCRIPTION

(PW) (RGT) (ZXY) Supply voltage of I C bus. Connect directly to the V CC of the external I C master. V CCI Provides voltage level translation. ADDR Address input. Connect directly to V CCP or ground. Active-low reset input. Connect to V CCP through a pullup resistor, if no active RESET connection is used. P port input/output (push-pull design structure). At power on, is configured as an input. P port input/output (push-pull design structure). At power on, is configured as an input. P port input/output (push-pull design structure). At power on, is configured as an input. P port input/output (push-pull design structure). At power on, is configured as an input. GND Ground P port input/output (push-pull design structure). At power on, is configured as an input. P port input/output (push-pull design structure). At power on, is configured as an input. P port input/output (push-pull design structure). At power on, is configured as an input. P port input/output (push-pull design structure). At power on, is configured as an input. INT Interrupt output. Connect to V CCI through a pullup resistor. SCL Serial clock bus. Connect to V CCI through a pullup resistor. SDA Serial data bus. Connect to V CCI through a pullup resistor. V CCP Supply voltage of TCA6408 for P port. Submit Documentation Feedback

www.ti.com Voltage Translation TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 Table shows how to set up V CC levels for the necessary voltage translation between the I C bus and the TCA6408. Table Voltage Translation V CCI V CCP (SCL and SDA of I C master) Port) (V) (V) 1.8 1.8 1.8 2.5 1.8 3.3 1.8 2.5 1.8 2.5 2.5 2.5 3.3 2.5 3.3 1.8 3.3 2.5 3.3 3.3 3.3 1.8 2.5 3.3 Submit Documentation Feedback

www.ti.com I/O PortShift Register

8 BitsInput

P7–P0 TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 LOGIC DIAGRAM (POSITIVE LOGIC) All pin numbers shown are for the PW package. All I/Os are set to inputs at reset. Submit Documentation Feedback

www.ti.com Data From Shift Register Write Configuration Pulse Write Pulse Read Pulse Write Polarity Pulse Polarity Inversion Register Input Port Register Output Port Register Configuration Register VCCP GND Input Port Register Data Polarity Register Data ESD Protection Diode P0 to P7 Output Port Register Data To INT D FF CK Q Q D FF CK Q Q D FF CK Q Q D FF CK Q Q Data From Shift Register Data From Shift Register I/O Port I C Interface TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 Simplified Schematic of to On power up or reset, all registers return to default values. When an I/O is configured as an input, FETs and are off, which creates a high-impedance input. The input voltage may be raised above V CC to a maximum of 5.5 If the I/O is configured as an output, or is enabled depending on the state of the output port register. In this case, there are low impedance paths between the I/O pin and either V CC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation. The bidirectional I C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I C communication with this device is initiated by a master sending a start condition, a high-to-low transition on the SDA input/output, while the SCL input is high (see Figure After the start condition, the device address byte is sent, MSB first, including the data direction bit (R/ W After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address input (ADDR) of the slave device must not be changed between the start and the stop conditions. On the I C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (start or stop) (see Figure Submit Documentation Feedback

www.ti.com SDA SCL S P Start□Condition Stop□Condition SDA SCL Data□Line Change S 1 2 8 9 NACK ACK Data□Output by□Transmitter Data□Output by□Receiver SCL From Master Start Condition Clock□Pulse□for Acknowledgment TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 A stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure Any number of data bytes can be transferred from the transmitter to receiver between the start and the stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation. A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a stop condition. Figure Definition of Start and Stop Conditions Figure Bit Transfer Figure Acknowledgment on the I C Bus Submit Documentation Feedback

www.ti.com Device Address Slave Address 01 0 0 AD DR R/W Fixed Programmable Control Register and Command Byte B2 B1 B0B5 B4 B3B7 B6 TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 Interface Definition BIT BYTE (MSB) (LSB) I C slave address L H L L L L ADDR W I/O data bus The address of the TCA6408 is shown in Figure Figure TCA6408 Address Address Reference ADDR I C BUS SLAVE ADDRESS L (decimal), (hexadecimal) H (decimal), (hexadecimal) The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation. Following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the control register in the TCA6408. Two bits of this data byte state the operation (read or write) and the internal registers (input, output, polarity inversion or configuration) that will be affected. This register can be written or read through the I C bus. The command byte is sent only during a write transmission. Figure Control Register Bits Command Byte CONTROL REGISTER BITS COMMAND POWER-UP BYTE REGISTER PROTOCOL DEFAULT (HEX) Input Port Read byte xxxx xxxx (1) Output Port Read/write byte 1111 1111 Polarity Inversion Read/write byte 0000 0000 Configuration Read/write byte 1111 1111 (1) Undefined Submit Documentation Feedback

www.ti.com Register Descriptions Power-On Reset Reset Input RESET TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 The input port register (register reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the configuration register. They act only on read operation. Writes to this register have no effect. The default value (X) is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to indicate to the I C device that the input port register will be accessed next. Register (Input Port Register) BIT I-7 I-6 I-5 I-4 I-3 I-2 I-1 I-0 DEFAULT X X X X X X X X The output port register (register shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Register (Output Port Register) BIT O-7 O-6 O-5 O-4 O-3 O-2 O-1 O-0 DEFAULT The polarity inversion register (register allows polarity inversion of pins defined as inputs by the configuration register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original polarity is retained. Register (Polarity Inversion Register) BIT N-7 N-6 N-5 N-4 N-3 N-2 N-1 N-0 DEFAULT The configuration register (register configures the direction of the I/O pins. If a bit in this register is set to the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to the corresponding port pin is enabled as an output. Register (Configuration Register) BIT C-7 C-6 C-5 C-4 C-3 C-2 C-1 C-0 DEFAULT When power (from is applied to V CCP an internal power-on reset holds the TCA6408 in a reset condition until V CCP has reached V POR At that time, the reset condition is released, and the TCA6408 registers and I C/SMBus state machine initialize to their default states. After that, V CCP must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle. The RESET input can be asserted to intialize the system while keeping V CCP at its operating level. A reset can be accomplished by holding the RESET pin low for a minimum of t W The TCA6408 registers and I C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1), the I/O levels at the P port can be changed externally or through the master. This input requires a pullup resistor to V CCP if no active connection is used. Submit Documentation Feedback

www.ti.com Interrupt Output INT Bus Transactions Writes SCL Start Condition Data 1 V alid SDA Write to Port Data Out From Port R/W ACK From Slave ACK From Slave ACK From Slave 1 9 8765432 Data 1100 1S 00 0 AD DR 0 A 0000000 A A P Data to PortCommand ByteSlave Address tpv 1/000 1S 00 0 AD DR 0 A 1000000 A A P SCL SDA Start□Condition R/W ACK□From□Slave ACK□From□Slave ACK□From□Slave 1 9 8765432 Data□to□RegisterCommand□ByteSlave Address Data TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time t iv the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting, data is read from the port that generated the interrupt or in a stop event. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. In a stop event, INT is cleared after the rising edge of SDA. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the

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register. The INT output has an open-drain structure and requires a pullup resistor to V CCP or V CCI depending on the application. If the INT signal is connected back to the processor that provides the SCL signal to the TCA6408, then the INT pin has to be connected to V CCI If not, the INT pin can be connected to V CCP Data is exchanged between the master and TCA6408 through write and read commands. Data is transmitted to the TCA6408 by sending the device address and setting the least-significant bit to a logic (see Figure for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one write transmission. Figure Write to Output Port Register <br/ Figure Write to Configuration or Polarity Inversion Registers Submit Documentation Feedback

www.ti.com Reads 00 1S 00 0 AD DR 0 A A Data from RegisterSlave AddressSlave Address R/W ACK From Slave Command Byte S 00 1 00 0 R/W

1 A Data A

At this moment, master-transmitter becomes master-receiver , and slave-receiver becomes slave-transmitter ACK From Slave ACK From Slave ACK From Master NACK From Master First byte AD DR SCL SDA INT Start Condition R/W Read From Port Data Into Port Stop Condition ACK From Master NACK From Master ACK From Slave Data From PortSlave Address Data From Port 1 9 8765432 00 1S 00 0 AD DR 0 A Data 1 Data 4A NA P Data 2 Data 3 Data 4 Data 5 tph tps tirtiv TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 The bus master first must send the TCA6408 address with the least-significant bit set to a logic (see Figure for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again but, this time, the least-significant bit is set to a logic Data from the register defined by the command byte then is sent by the TCA6408 (see Figure and Figure Data is clocked into the register on the rising edge of the ACK clock pulse. Figure Read From Register <br/ Transfer of data can be stopped at any time by a stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to (read input port register). This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from P port (see Figure Figure Read Input Port Register Submit Documentation Feedback

www.ti.com Absolute Maximum Ratings (1) Recommended Operating Conditions TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CCI Supply voltage range 0.5 6.5 V V CCP Supply voltage range 0.5 6.5 V V I Input voltage range (2) 0.5 6.5 V V O Output voltage range (2) 0.5 6.5 V I IK Input clamp current ADDR, RESET SCL V I mA I OK Output clamp current INT V O mA P Port V O or V O V CCP mA I IOK Input/output clamp current SDA V O or V O V CCI mA Continuous output low current P Port V O to V CCP mA I OL Continuous output low current SDA, INT V O to V CCI mA I OH Continuous output high current P Port V O to V CCP mA Continuous current through GND 200 mA I CC Continuous current through V CCP 160 mA Continuous current through V CCI mA PW package 108 θ JA Package thermal impedance (3) RGT package C/W ZXY package 193 T stg Storage temperature range 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The package thermal impedance is calculated in accordance with JESD 51-7. MIN MAX UNIT V CCI Supply voltage 1.65 5.5 V V CCP Supply voltage 1.65 5.5 SCL, SDA 0.7 V CCI 5.5 V IH High-level input voltage V ADDR, P0, RESET 0.7 V CCP 5.5 SCL, SDA 0.5 0.3 V CCI V IL Low-level input voltage V ADDR, P0, RESET 0.5 0.3 V CCP I OH High-level output current mA I OL Low-level output current mA T A Operating free-air temperature C Submit Documentation Feedback

www.ti.com Electrical Characteristics TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 over recommended operating free-air temperature range, V CCI 1.65 V to 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS V CCP MIN TYP (1) MAX UNIT V IK Input diode clamp voltage I I mA 1.65 V to 5.5 V 1.2 V V POR Power-on reset voltage (2) V I V CCP or GND, I O 1.65 V to 5.5 V 1.4 V 1.65 V 1.2 2.3 V 1.8 I OH mA V 2.6 4.5 V 4.1 P port high-level output V OH V voltage 1.65 V 1.1 2.3 V 1.7 I OH mA V 2.5 4.5 V 4.0 1.65 V 0.45 2.3 V 0.25 I OL mA V 0.25 4.5 V 0.2 P port low-level output V OL V voltage 1.65 V 0.6 2.3 V 0.3 I OL mA V 0.25 4.5 V 0.2 SDA V OL 0.4 V 1.65 V to 5.5 V I OL mA INT V OL 0.4 V 1.65 V to 5.5 V SCL, SDA V I V CCI or GND 0.1 I I 1.65 V to 5.5 V µ A ADDR, RESET V I V CCP or GND 0.1 I IH P port V I V CCP µ A 1.65 V to 5.5 V I IL P port V I GND µ A V I on SDA V CCI or GND, 3.6 V to 5.5 V SDA, V I on P port, ADDR and 2.3 V to 3.6 V 6.5 Operating P Port, RESET V CCP or GND, mode ADDR, I O I/O inputs, 1.65 V to 2.3 V RESET f SCL 400 kHz V I on SDA V CCI or GND, 3.6 V to 5.5 V 2.5 SDA, V I on P port, ADDR and 2.3 V to 3.6 V 1.6 3.8 Operating P Port, I CC RESET V CCP or GND, mode ADDR, µ A CCI I CCP I O I/O inputs, 1.65 V to 2.3 V 2.3 RESET f SCL 100 kHz V I on SCL and SDA V CCI or 3.6 V to 5.5 V 0.2 SCL, SDA, GND, 2.3 V to 3.6 V 0.1 0.6 Standby P Port, V I on P Port, ADDR and mode ADDR, RESET V CCP or GND, 1.65 V to 2.3 V 0.1 0.4 RESET I O I/O inputs, f SCL One input at V CCI 0.6 Δ I CCI SCL, SDA 1.65 V to 5.5 V µ A Additional Other inputs at V CCI or GND current in P Port, Standby One input at V CCP 0.6 Δ I CCP ADDR, 1.65 V to 5.5 V µ A mode Other inputs at V CCP or GND RESET C i SCL V I V CCI or GND 1.65 V to 5.5 V pF SDA V IO V CCI or GND C io 1.65 V to 5.5 V pF P Port V IO V CCP or GND 7.5 8.5 (1) All typical values are at nominal supply voltage (1.8-V, 2.5-V, 3.3-V, or 5-V V CC and T A (2) When power (from is applied to V CCP an internal power-on reset holds the TCA6408 in a reset condition until V CCP has reached V POR At that time, the reset condition is released, and the TCA6408 registers and I C/SMBus state machine initialize to their default states. After that, V CCP must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle. Submit Documentation Feedback

www.ti.com I C Interface Timing Requirements Reset Timing Requirements Switching Characteristics TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 over recommended operating free-air temperature range (unless otherwise noted) (see Figure STANDARD MODE FAST MODE I C BUS I C BUS UNIT MIN MAX MIN MAX f scl I C clock frequency 100 400 kHz t sch I C clock high time 0.6 µ s t scl I C clock low time 4.7 1.3 µ s t sp I C spike time ns t sds I C serial data setup time 250 100 ns t sdh I C serial data hold time ns t icr I C input rise time 1000 0.1C b (1) 300 ns t icf I C input fall time 300 0.1C b (1) 300 ns t ocf I C output fall time; pF to 400 pF bus 300 0.1C b (1) 300 µ s t buf I C bus free time between Stop and Start 4.7 1.3 µ s t sts I C Start or repeater Start condition setup time 4.7 0.6 µ s t sth I C Start or repeater Start condition hold time 0.6 µ s t sps I C Stop condition setup time 0.6 µ s t vd(data) Valid data time; SCL low to SDA output valid µ s Valid data time of ACK condition; ACK signal from SCL low to t vd(ack) µ s SDA (out) low (1) C b total capacitance of one bus line in pF over recommended operating free-air temperature range (unless otherwise noted) (see Figure STANDARD MODE FAST MODE I C BUS I C BUS UNIT MIN MAX MIN MAX t W Reset pulse duration ns t REC Reset recovery time ns t RESET Time to reset (1) 600 600 ns (1) Minimum time for SDA to become high or minimum time to wait before doing a START over recommended operating free-air temperature range, C L 100 pF (unless otherwise noted) (see Figure STANDARD FAST MODE MODE I C BUS PARAMETER FROM TO UNIT I C BUS MIN MAX MIN MAX t iv Interrupt valid time P Port INT µ s t ir Interrupt reset delay time SCL INT µ s t pv Output data valid SCL 400 400 ns t ps Input data setup time P Port SCL ns t ph Input data hold time P Port SCL 300 300 ns Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS Supply Voltage, V (V)CC Supply Current, (µA) ICC f = All I/Os unloaded SCL 400 kHz – 40 – 15 10 35 60 85 V = 1.8 VCC VCC = 2.5 V VCC = 3.3 V VCC = 5.0 V Temperature, °C)T (A Supply Current, (µA) ICC f = All I/Os unloaded SCL 400 kHz 100 120 – 40 – 15 10 35 60 85 Temperature, °C)T (A Suppl y Current, (nA) ICC SCL = All I/Os unloaded VCC VCC = 5.0 V VCC = 3.3 V VCC = 2.5 V V = 1.8 VCC Output Low Voltage, V)V (OL Sink Current, (mA) ISINK TA = –40°C TA = 25°C TA = 85°C VCC = 1.8 V Output Low Voltage, V)V (OL Sink Current, (mA) ISINK VCC = 3.3 V TA = 85°C TA = –40°C TA = 25°C Output Low Voltage, V)V (OL Sink Current, (mA) ISINK VCC = 2.5 V TA = 85°C TA = –40°C TA = 25°C V (V)CCP – V OH Source Current, (mA) ISOURCE TA = –40°C TA = 25°C TA = 85°C VCC = 1.8 V Output Low Voltage, V)V (OL Sink Current, (mA) ISINK VCC = 5.0 V TA = –40°C TA = 25°C TA = 85°C Temperature, °C)T (A Output Low V olta ge (mV) V OL 100 150 200 250 300 – 40 – 15 10 35 60 85 V =□1.8□V,□I =□1□mACC SOURCE V ICC SOURCE=□5□V, =□1□mA V ICC SOURCE=□1.8□V, =□10□mA V ICC SOURCE=□5.0□V, =□10□mA TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 T A C (unless otherwise noted) SUPPLY CURRENT STANDBY SUPPLY CURRENT SUPPLY CURRENT vs vs vs TEMPERATURE TEMPERATURE SUPPLY VOLTAGE I/O SINK CURRENT I/O SINK CURRENT I/O SINK CURRENT vs vs vs OUTPUT LOW VOLTAGE OUTPUT LOW VOLTAGE OUTPUT LOW VOLTAGE I/O SINK CURRENT I/O LOW VOLTAGE I/O SOURCE CURRENT vs vs vs OUTPUT LOW VOLTAGE TEMPERATURE OUTPUT HIGH VOLTAGE Submit Documentation Feedback

www.ti.com TA = –40°C TA = 25°C TA = 85°C VCC = 5.0 V V (V)CCP – V OH Source Current, I SOURCE (mA) TA = –40°C TA = 25°C VCC = 3.3 V TA = 85°C V (V)CCP – V OH Source Current, I SOURCE (mA) TA = –40°C TA = 25°C VCC = 2.5 V TA = 85°C V (V)CCP – V OH Source Current, I SOURCE (mA) Temperature, °C)T (A V CC OH 100 150 200 250 300 – 40 – 15 10 35 60 85 V = 1.8 V,CC I = 10 mASOURCE V = 5.0 V,CC I = 10 mASOURCE TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 TYPICAL CHARACTERISTICS (continued) T A C (unless otherwise noted) I/O SOURCE CURRENT I/O SOURCE CURRENT I/O SOURCE CURRENT vs vs vs OUTPUT HIGH VOLTAGE OUTPUT HIGH VOLTAGE OUTPUT HIGH VOLTAGE I/O HIGH VOLTAGE vs TEMPERATURE Submit Documentation Feedback

www.ti.com PARAMETER MEASUREMENT INFORMATION SDA LOAD□CONFIGURATION VCCI R =□1□kL /c87 C =□50□pF (see□Note A) L DUT SDA Two□Bytes□for□READ□□Input□□Port□Register (see□Figure□9) VOLTAGE□WAVEFORMS BYTE DESCRIPTION I C□address Input□register□port□data SCL SDA Stop Condition (P) Start Condition (S) Address Bit□7 (MSB) Address Bit□1 Bit□0 (LSB) W ACK (A) Data Bit□7 (MSB) Data Bit□0 (LSB) Stop Condition (P) 0.7 /c180VCCI 0.3 /c180VCCI Repeat□Start Condition Stop Condition 0.7 /c180VCCI 0.3 /c180VCCI tscl tsch tsp ticf ticf ticr tsth ticr tsds tsdh tocf tvd(ack) tvd tvd tsts tsps tbuf TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 C L includes probe and jig capacitance. tocf is measured with C L of pF or 400 pF. All inputs are supplied by generators having the following characteristics: PRR MHz, Z O Ω t r f ns. All parameters and waveforms are not applicable to all devices. Figure 10. I C Interface Load Circuit and Voltage Waveforms Submit Documentation Feedback

www.ti.com A A A A S 0 1 0 0 0 0 AD DR

1 Data□1 1 PData□2

Condition 8□Bits (One□Data□Byte) From□Port Data□From□PortSlave Address R/W 87654321 Address Data□1 Data□2 INT B B A A Pn INT R/W AINT SCL View□B−BView A−A ACK From□Slave ACK From□Slave INTERRUPT□LOAD□CONFIGURATION VCCI R =□4.7□kL /c87 C =□100□pF (see□Note A) L DUT INT

0.7 V/c180 CCI

0.3 V/c180 CCI

0.5 V/c180 CCI

0.5 V/c180 CCP

I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 PARAMETER MEASUREMENT INFORMATION (continued) C L includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR MHz, Z O Ω t r f ns. All parameters and waveforms are not applicable to all devices. Figure 11. Interrupt Load Circuit and Voltage Waveforms Submit Documentation Feedback

www.ti.com P0 ASCL P3 Unstable Data Last□Stable□Bit SDA WRITE□MODE□(R/ =□0)W P0 ASCL P3 READ□MODE□(R/ =□1)W DUT P PORT□LOAD□CONFIGURATION Pn 500 /c87 500 /c87

2 V/c180 CCP

0.7 V/c180 CCP

0.3 /c180VCCI 0.5 /c180VCCP C =□50□pF (see□Note A) L Slave ACK t (see□Note□B) pv Pn Pn tps tph TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 PARAMETER MEASUREMENT INFORMATION (continued) C L includes probe and jig capacitance. t pv is measured from 0.7 V CC on SCL to 50% I/O (Pn) output. All inputs are supplied by generators having the following characteristics: PRR MHz, Z O Ω t r f ns. The outputs are measured one at a time, with one transition per measurement. All parameters and waveforms are not applicable to all devices. Figure 12. P Port Load Circuit and Timing Waveforms Submit Documentation Feedback

www.ti.com SDA SCL Start ACK□or□Read□Cycle RESET Pn SDA LOAD□CONFIGURATION VCCI R =□1□k /c87L C =□50□pF (see□Note A) L DUT SDA DUT P PORT□LOAD□CONFIGURATION Pn 500 /c87 500 /c87 C =□50□pF (see□Note A) L I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 PARAMETER MEASUREMENT INFORMATION (continued) C L includes probe and jig capacitance. All inputs are supplied by generators having the following characteristics: PRR MHz, Z O Ω t r f ns. The outputs are measured one at a time, with one transition per measurement. I/Os are configured as inputs. All parameters and waveforms are not applicable to all devices. Figure 13. Reset Load Circuits and Voltage Waveforms Submit Documentation Feedback

www.ti.com APPLICATION INFORMATION ADDR GND INT SDA SCL TCA6408 SDA SCL INT GND Keypad A B ENABLE Master Controller 161 RESET 3RESET V (1.8□V) CCI VCC VCCP 10□k (x□4) /c87 P0 ALARM Subsystem□1 (e.g., Alarm) (see□note□D) 100□k (x□3)/c87 VCCPVCCI VCCI TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 Figure shows an application in which the TCA6408 can be used. Device address configured as 0100000 for this example. and are configured as inputs. and P5-P7 are configured as outputs. Resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float, a resistor is not needed. Outputs (in the P port) do not need pullup resistors. Figure 14. Typical Application Submit Documentation Feedback

www.ti.com Minimizing I CC When the I/O is Used to Control LEDs Px LED 100 kΩVCC VCC 3.3 V Px LED 5 V VCC TCA6408 LOW-VOLTAGE 8-BIT I C AND SMBus I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS151C FEBRUARY 2007 REVISED JUNE 2007 APPLICATION INFORMATION (continued) When the I/Os are used to control LEDs, normally they are connected to V CC through a resistor as shown in Figure The LED acts as a diode so when the LED is off the I/O V IN is about 1.2 V less than V CC The Δ I CC parameter in "Electrical Characteristics" shows how I CC increases as V IN becomes lower than V CC Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to V CC when the LED is off. Figure shows a high-value resistor in parallel with the LED. Figure shows V CC less than the LED supply voltage by at least 1.2 Both of these methods maintain the I/O V IN at or above V CC and prevent additional supply current consumption when the LED is off. Figure 15. High-Value Resistor in Parallel With the LED Figure 16. Device Supplied by a Low Voltage Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TCA6408PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA6408PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA6408PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA6408PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA6408RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TCA6408RGTRG4 ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2007 Addendum-Page 1

TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant TCA6408PWR PW 16 SITE 41 330 12 7.0 5.6 1.6 8 12 Q1 TCA6408RGTR RGT 16 SITE 41 330 12 3.3 3.3 1.1 8 12 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Sep-2007 Pack Materials-Page 1

Device Package Pins Site Length (mm) Width (mm) Height (mm) TCA6408PWR PW 16 SITE 41 346.0 346.0 0.0 TCA6408RGTR RGT 16 SITE 41 346.0 346.0 0.0 PACKAGE MATERIALS INFORMATION www.ti.com 24-Sep-2007 Pack Materials-Page 2

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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