TCA62746AFNG

TCA62746AFG MARKTECH | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 25

Technical content

Features

• 16-output built-in
• Output open detection (OOD) function : When in detection mode, outputs the detection results via SOUT.
• Output short detection (OSD) function : When in detection mode, outputs the detection results via SOUT.
• Output current setting range : 2 to 50 mA × 16-constant current output
• Current accuracy (@ REXT = 1.56 kΩ, VO = 1.0 V, VDD = 5.0 V) : Between outputs: ± 1% (typ.) Between devices: ± 3% (typ.)
• Control data format: serial-in, parallel-out
• I/O logic: TTL level (Schmitt trigger input)
• Data transfer frequency: fMAX = 25 MHz (max)
• Power supply voltage: VDD = 4.5 to 5.5 V
• Operation temperature range: Topr = −40 to 85°C
• Constant current output voltage: VO = 17V (max)
• Output delay circuit built-in: Internal data reset circuit for power-on resetting (POR)
• Backward compatible to TB62706B and TB62726A series drivers
• Package: FG type: SSOP24-P-300-1.00B FNG type: SSOP24-P-300-0.65A Caution This device is sensitive to electr ostatic discharge. Please handle with care. T h e t e r m i n a l s w h i c h a r e m a r ginal to electro static discharge are shown in the following table. (Please refer to page 22 for details.) ESD test MM Model Marginal terminals (MM Model Internal Standard ±200V) * ESD test HBM Model Internal Standard (±2000V) is OK TCA62746AFG TCA62746AFNG Weight SSOP24-P-300-1.00B : 0.32 g (typ.) SSOP24-P-300-0.65A : 0.14 g (typ.)

Pin Assignment (top view) As shown below, this series has the same pin assignments as the TB62706B and TB62726A series: Note1: Short circuiting an output pin to a power supply pin (VDD or VLED*), or short-circuiting the REXT pin to the GND pin will likely exceed the rating, which in turn may result in smoldering and/or permanent damage. Please keep this in mind when determining the wiring layout for the power supply and GND pins. LED: LED power supply GND SIN SCK SLAT OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 VDD REXT SOUT OE OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT8 OUT9

3.0 V 0.3 V OSD OOD Constant current outputs OUT0 OUT1 OUT15 OOD OUT15 OSD Delay1 Delay15 16-bit D-latch G Q0 Q1 Q15 D0 D1 D15 R 16-bit shift register Q15Q0 Q1 Q15 ST D0~D15 R OOD/OSD controller OE ST-OUT SLAT OE SIN SCK 16-bit MUX SOSD OOD DO B.G POR VDD GND REXT SOUT OSD OOD

SCK SLAT OE SIN OUT0 ʜ OUT7 ʜ OUT15 *1 SOUT H L Dn Dn ʜ Dn − 7 ʜ Dn − 15 Dn − 15 L L Dn + 1 No Change Dn − 14 H L Dn + 2 Dn + 2 ʜ Dn − 5 ʜ Dn − 13 Dn − 13 - *2 L Dn + 3 Dn + 2 ʜ Dn − 5 ʜ Dn − 13 Dn − 13 - *2 H Dn + 3 OFF Dn − 13 Note1: When OUT0 to OUT15 output pins are set to "H" the respective output will be ON and when set to "L" the respective output will be OFF. Note2: “-“ is irrelevant to the truth table. Timing Chart Note 1: The latch circuit is a leveled-latch circuit. Please exercise precaution as it is not triggered-latch circuit. Note 2: Keep the SLAT pin is set to “L” to enable the latch circuit to hold data. In addition, when the SLAT pin is set to “H” the latch circuit does not hold data. The data will instead pass onto output. When the OE pin is set to “L” the OUT0 to OUT15 output pins will go ON and OFF in response to the data. In addition, when the OE pin is set to “H” all the output pins will be forced OFF regardless of the data. SIN SLAT SCK OUT0 OUT1 SOUT OE OUT15 H L n = 0 1 2 3 4 5 6 8 H L H L H L ON OFF ON OFF ON OFF ON OFF H L 79 1 1 10 12 13 1514 2OUT

Pin No Pin Name I/O Function 1 GND ⎯ The ground pin. 2 SIN I The serial data input pin. 3 SCK I The serial data transfer clock input pin. Also used for OOD/OSD mode settings.

4 SLAT I

The latch signal input pin. Data is saved at L level. Also used for OOD/OSD mode settings. 5 0OUT O A sink type constant current output pin. 6 1OUT O A sink type constant current output pin. 7 2OUT O A sink type constant current output pin. 8 3OUT O A sink type constant current output pin. 9 4OUT O A sink type constant current output pin. 10 5OUT O A sink type constant current output pin. 11 6OUT O A sink type constant current output pin. 12 7OUT O A sink type constant current output pin. 13 8OUT O A sink type constant current output pin. 14 9OUT O A sink type constant current output pin. 15 10OUT O A sink type constant current output pin. 16 11OUT O A sink type constant current output pin. 17 12OUT O A sink type constant current output pin. 18 13OUT O A sink type constant current output pin. 19 14OUT O A sink type constant current output pin. 20 15OUT O A sink type constant current output pin.

21 OE I

The constant current output enable signal input pin. During the “H” level, the output will be forced off. Also used for OOD/OSD mode settings. 22 SOUT O The serial data output pin. This pin outputs the OD/OSD detection result data. 23 R EXT ⎯ The constant current value se tting resistor connection pin. 24 V DD ⎯ The power supply input pin.

Absolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating *1 Unit Power supply voltage V DD −0.4 to 6.0 V Output current I O 55 mA Logic input voltage V IN −0.3 to VDD + 0.3 *2 V Output voltage V O −0.3 to 17 V Operating temperature T opr −40 to 85 °C Storage temperature T stg −55 to 150 °C Thermal resistance R th(j-a) 94(AFG type When mounted PCB)/120(AFNG type When mounted PCB) *3 °C/W Power dissipation P D 1.32(AFG type When mounted PCB)/1.04(AFNG type When mounted PCB) *3,4 W Note1: Voltage is ground referenced. Note2: However, do not exceed 6V. Note3: PCB condition 76.2 x 114.3 x 1.6 mm, Cu 30% (SEMI conforming) Note4: The power dissipation decreases the reciprocal of the saturated thermal resistance (1/ Rth(j-a)) for each degree (1°C) that the ambient temperature is exceeded (Ta = 25°C). Recommended Operating Conditions DC Items (Unless otherwise specified, Ta = −40°C to 85°C) Characteristics Symbol Test Conditions Min Typ. Max Unit Power supply voltage V DD ⎯ 4.5 ⎯ 5.5 V Output voltage when OFF V O (OFF) OUTn ⎯ ⎯ 16 V Output voltage when ON V O (ON) OUTn 0.7 ⎯ 4 V High level logic input voltage V IH ⎯ 2.0 ⎯ V DD V Low level logic input voltage V IL ⎯ GND ⎯ 0.8 V High level SOUT output current I OH V DD = 5 V ⎯ ⎯ −1 mA Low level SOUT output current I OL V DD = 5 V ⎯ ⎯ 1 mA Constant current output I O OUTn 2 ⎯ 50 mA AC Items (Unless otherwise specified, VDD = 4.5 to 5.5 V, Ta = −40°C to 85°C) Characteristics Symbol Test Circui ts Test Conditions Min Typ. Max Unit Serial data transfer frequency f SCK 7 ⎯ ⎯ ⎯ 25 MHz Clock pulse width t wSCK 7 SCK = “H” or “L” 20 ⎯ ⎯ ns Latch pulse width t wSLAT 7 SLAT = “H” 20 ⎯ ⎯ ns twOE1 7 OE = “H” or “L” ,REXT = 500 Ω 100 ⎯ ⎯ ns Enable pulse width twOE2 ⎯ When error is detected *1 2 ⎯ ⎯ µs tHOLD1 7 ⎯ 5 ⎯ ⎯ ns tHOLD2 7 ⎯ 5 ⎯ ⎯ ns tHOLD3 7 ⎯ 10 ⎯ ⎯ ns Hold time tHOLD4 7 ⎯ 10 ⎯ ⎯ ns tSETUP1 7 ⎯ 5 ⎯ ⎯ ns tSETUP2 7 ⎯ 5 ⎯ ⎯ ns tSETUP3 7 ⎯ 10 ⎯ ⎯ ns Setup time tSETUP4 7 ⎯ 10 ⎯ ⎯ ns Maximum clock rise time t r 7 *2 ⎯ ⎯ 500 ns Maximum clock fall time t f 7 *2 ⎯ ⎯ 500 ns Note1: Please refer to page 16 for details of the error detection. Note2: If the device is connected in a cascade and the tr/tf of the clock waveform increases due to deceleration of the clock waveform, it may not be possible to achiev e the timing required for data transfer. Please keep these timing conditions in mind when designing your application.

Electrical Characteristics (Unless otherwise specified, VDD = 4.5 to 5.5 V and Ta = 25°C) Characteristics Symbol Test Circui ts Test Conditions Min Typ. Max Unit High level logic output voltage V OH 1 I OH = −1 mA, SOUT VDD − 0.4 ⎯ ⎯ V Low level logic output voltage V OL 1 I OH = +1 mA, SOUT ⎯ ⎯ 0.4 V High level logic input current I IH 2 V IN = VDD, OE , SIN, SCK ⎯ ⎯ 1 µA Low level logic input current I IL 3 V IN = GND, SLAT , SIN, SCK ⎯ ⎯ − 1 µA IDD1 4 VO = 16 V, No REXT SCK = “L”, OE = “H” ⎯ 0.1 0.5 mA IDD2 4 REXT = 1.56 kΩ, All output OFF ⎯ ⎯ 7.0 mA IDD3 4 REXT = 500 Ω, All output OFF ⎯ ⎯ 14.0 mA IDD4 4 REXT = 1.2 kΩ, All output ON ⎯ ⎯ 7.0 mA Power supply current IDD5 4 REXT = 500 Ω, All output ON ⎯ ⎯ 14.0 mA IO1 5 VDD = 5.0V, VO = 1.0 V, REXT = 1.56 kΩ 14.1 15 15.9 mA Constant current output IO2 5 VDD = 5.0V, VO = 1.0 V, REXT = 500 Ω 44.2 47 49.8 mA Output OFF leak current I OK 5 VO = 16 V, REXT = 1.56 kΩ, All output OFF ⎯ ⎯ 0.5 µA Constant current error ∆IO 5 VDD = 5.0V, VO = 1.0 V, REXT = 1.56 kΩ, 0OUT to 15OUT ⎯ ± 1 ±3 % Constant current power supply voltage regulation %VDD 5 VDD = 4.5 to 5.5V, VO = 1.0 V, REXT = 1.56 kΩ, 0OUT to 15OUT ⎯ ± 1 ±4 %/V Constant current output voltage regulation %VO 5 VDD = 5.0V, VO = 1.0 to 3.0 V, REXT =1.56 kΩ, 0OUT to 15OUT ⎯ ± 1 ±4 %/V Pull-up resistor R UP 3 OE 250 500 800 k Ω Pull-down resistor R DOWN 2 SLAT 250 500 800 k Ω Electrical Characteristics during OOD/OSD Mode (Unless otherwise specified, VDD = 4.5 to 5.5 V and Ta = 25°C) Characteristics Symbol Test Circui ts Test Conditions Min Typ. Max Unit OOD voltage V OOD 6 R EXT = 464 Ω~11.5 kΩ ⎯ 0.30 0.40 V OSD voltage V OSD 6 R EXT = 464 Ω~11.5 kΩ 2.85 3.0 ⎯ V

Switching Characteristics (Unless otherwise specified, Ta = 25°C and VDD = 5.0 V) Characteristics Symbol Test Circui ts Test Conditions Min Typ. Max Unit SCK- 0OUT t pLH1 7 SLAT = “H”, OE = “L” ⎯ 20 100 SLAT - 0OUT t pLH2 7 OE = “L” ⎯ 20 100 OE - 0OUT t pLH3 7 SLAT = “H” ⎯ 20 100 SCK-SOUT t pLH 7 ⎯ 5 10 ⎯ SCK- 0OUT t pHL1 7 SLAT = “H”, OE = “L” ⎯ 50 100 SLAT - 0OUT t pHL2 7 OE = “L” ⎯ 50 100 OE - 0OUT t pHL3 7 SLAT = “H” ⎯ 50 100 Propagation delay time SCK-SOUT t pHL 7 ⎯ 15 20 ⎯ ns Output rise time t or 7 10 to 90% of voltage waveform ⎯ 30 150 ns Output fall time t of 7 90 to 10% of voltage waveform ⎯ 70 150 ns Output delay time t DLY (ON) 7 OUTn - )1n(OUT + between adjacent outputs ⎯ 20 ⎯ ns Output delay time t DLY (OFF) 7 OUTn - )1n(OUT + between adjacent outputs ⎯ 20 ⎯ ns

1. SCK, SIN 2. OE 3. SLAT 4. SOUT 5. OUT0 to OUT15 VDD GND SLAT VDD (SCK) (SIN) GND VDD SOUT GND VDD OE GND 0OUT to 15OUT GND

IO = -1mA~1mA CL = 10.5 pF VDD = 4.5~5.5 V F.G VIH = VDD VIL = 0 V tr = tf = 10 ns (10~90%) SLAT Test Circuit1: High level logic input voltage / Low level logic input voltage REXT SCK SIN OE VDD OUT0 OUT7 OUT15 SOUTGNDREXT CL = 10.5 pF VDD = 4.5~5.5 V SLAT Test Circuit2: High level logic input current / Pull-down resistor REXT VIN = VDD A A A A SCK SIN OE VDD OUT0 OUT7 OUT15 SOUTGNDREXT CL = 10.5 pF VDD = 4.5~5.5 V SLAT Test Circuit3: Low level logic input current / Pull-up resistor REXT A A A A V

Test Circuit4: Power supply current Test Circuit6: OOD voltage / OSD voltage All output terminals is set to turning on, only one output terminal is connected with the VO2 power supply, and VO2 is changed. VOOD/VOSD is confirmed by the error detection result from SOUT. Test Circuit5: Constant current output / Output OFF leak current / Constant current error Test Circuit5: Constant current power supply voltage regulation / Constant current output voltage regulation VO = 1V, 3V, 16V REXT = 1.56kΩ, 500Ω SCK SIN OE VDD OUT0 OUT7 OUT15 SOUTGNDREXT CL = 10.5 pF VDD = 4.5~5.5V SLAT F.G VIH = VDD VIL = 0 V tr = tf = 10 ns (10~90%) A A A SCK SIN OE VDD OUT0 OUT7 OUT15 SOUTGNDREXT CL = 10.5 pF VDD = 4.5~5.5V SLAT REXT = 1.56kΩ, 500Ω F.G VIH = VDD VIL = 0 V tr = tf = 10 ns (10~90%) A SCK SIN OE VDD OUT0 OUT7 OUT15 SOUTGNDREXT CL = 10.5 pF VDD = 4.5 V~5.5 V SLAT REXT = 464Ω , 11.5kΩ F.G VIH = VDD VIL = 0 V tr = tf = 10 ns (10~90%) VO1 = 1 V V V V VO2

This is designed for high speed switching between outputs and is intended to have the effect of reducing switching noise by reducing the di/dt when all outputs are ON or OFF at the same time.There is a switching time lag (20 ns typ.) between adjacent outputs. The equivalent circuit chart of the delay circuit is shown in the following. SCK SIN OE VDD OUT0 RL = 85 Ω CL OUT7 CL RL OUT15 CL = 10.5 pF RL SOUTGNDREXT CL = 10.5 pF VDD = 4.5~5.5 V SLAT Test Circuit7: Switching Characteristics REXT = 500Ω F.G VIH = VDD VIL = 0 V tr = tf = 10 ns (10~90%) VLED =5V Delay Delay OUT2 Delay Delay OUT15 ×15 D15 Delay OUT1 OUT0 OE

1. SCK, SIN, SOUT 2. SCK, SIN, SLAT , OE , OUT0 3. OUT0 tHOLD1 tpLH/tpHL twSCK 50%50% 50% 50% tSETUP1 SIN SCK SOUT 50% 90% 10% tr tf 90% 10% twSCK 50% twOE1 50% tHOLD2 SIN SCK 50% 50% 50% 50% tpHL1/tpLH1 tpHL2/tpLH2 twSLAT OE OUT0 50%SLAT 50% tSETUP2 10% 90% 10% 90% tor OUT0 OFF ON 50% 50% 50% 50% twOE1 tpLH3tpHL3 OE tof

1. OOD Mode/OSD Mode 5. OOD/OSD Read Mode tHOLD3 twsck 50%50% tSETUP3 SCK 50% 50% 50% tSETUP4 tHOLD4 50%50% SLAT OE SCK 50% 50% 50% twOE2 50% OE

This IC is possible to PWM grayscale control by the input of the PWM signal to the EN terminal. When PWM grayscale control is done, we recommend the LED power-supply voltage to be set to become the satiety region of the constant current characteristic. When using this IC outside the saturation area, PWM grayscale control cannot be normally done. Switching to Open Circuit Detection (OOD) and Short Circuit Detection (OSD) Modes Switching to OSD mode The signal sequence set to be in the OSD mode. Here, the SLAT active pulse would not latch any data. Switching to OOD mode The signal sequence set to be in the OOD mode. Here, the SLAT active pulse would not latch any data. H SCK SLAT OE 1 2 3 4 5 6 LH HH H L LL HL L H SCK SLAT OE 1 2 3 4 5 6 LH HH H L LL LL H

When the above signal sequence is set in the OOD and OSD modes, the error state code can be read through the terminal SOUT. Error state code of OOD detection mode Error state code State of output terminal VOOD ≥ VO 0 Open circuit VOOD < VO 1 Normal Error state code of OSD detection mode Error state code State of output terminal VOSD ≤ VO 0 Short circuit VOSD > VO 1 Normal

Description

In the OOD and OSD modes, the state of OE must be switched from “H” to “L”. And, then, This IC would execute Open-/Short-circuit Detection as well as enabling output ports to drive current. At least three clock must be inputs at the “L” state of OE and the third clock should be at least 2 µs after the falling edge of OE . the detected error status into the built-in shift register is done by rising edge of this third clock. When OE is “L", the serial data cannot be input from the terminal SIN. When OE is changed from “L" to “H", the error stat e code is output from the terminal SOUT synchronizing with the clock. Switching to Normal Mode The signal sequence set to be in the Normal mode. H SCK SLAT OE 1 2 3 4 5 6 LH HH H L LL LL L “L” level H SCK OE L H HH H Error status code SOUT Bit H Bit Bit Bit Bit Bit L MIN 2 µs n > = 3 L

Timing chart of error detection mode (OSD mode) SCK SLAT OE SIN, 0 TCA62746, 0 SOUT, 0 TCA62746, 1 SOUT, 1SIN, 1 TCA62746, 2 SOUT, 2SIN, 2 TCA62746, N-2 TCA62746, N-1 SOUT, N-1

3 CLK or more N × 15 CLK

A. Switching to Error detection mode SCK SIN SLAT OE 1 2 3 4 5 6 1 2 3 4 5 6 SIN, 0 0 12 2CLK 2 µs Don’t care 1415SOUT, 0 3031SOUT, 1 N × 16-1SOUT, N-1 B. Setting of output terminal that does the erro r E. Switching to Normal C. Detection the error D. Reading back the error status code Error: 0, Normal: 1 N × 16 CLK N × 16-1

*This data is provided for reference only. Thorough evaluation and testing should be implemented when designing your application's mass production design. Set output current – Duty cycle graph IO - Duty 0 20 40 60 80 100 Duty - Turn on rate (%) IO (mA) TCA62746FG TCA62746FNG IO - Duty 0 20 40 60 80 100 Duty - Turn on rate (%) IO (mA) TCA62746FG TCA62746FNG IO - Duty 0 2 04 06 08 0 1 0 0 Duty - Turn on rate (%) IO (mA) TCA62746FG TCA62746FNG PD - Ta 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 1 02 03 04 05 06 07 08 09 0 Ta (ˆ) PD (W) TCA62746FG TCA62746FNG ON PCB VDD=5.5V VO=1.0V Ta=25°C ON PCB All output ON TCA62746AFG TCA62746AFNG TCA62746AFG TCA62746AFNG TCA62746AFG TCA62746AFNG TCA62746AFG TCA62746AFNG VDD=5.5V VO=1.0V Ta=55°C ON PCB All output ON VDD=5.5V VO=1.0V Ta=80°C ON PCB All output ON

*This data is provided for reference only. Thorough evaluation and testing should be implemented when designing your application's mass production design. Output Current – REXT Resistor Constant current characteristic IO - REXT 0123456789 1 0 1 1 1 2 R EXT (k⒋) IO (mA) Theoretical value I O (A) = (1.23(V) ÷ REXT (Ω)) × 19 VDD=5.0V VO=1.0V Ta=25°C IO - VO V O (V) IO (mA) VDD=5.0V VO=1.0V Ta=25°C

Weight: 0.32 g (typ.)

Weight: 0.14 g (typ.)

The terminals which are weak to electro static discharge are shown in the following table. MM Model ESD test Result (Internal Standard ±200V) - Serge + Serge pin Standard TEST Result Standard TEST Result

1 V DD 200V V DD 200V

2 V DD,GND 200V VDD,GND 200V

3 V DD,GND 200V VDD,GND 200V

4 V DD,GND 200V VDD,GND 200V

5 V DD,GND 200V VDD,GND 160V

6 V DD,GND 200V VDD,GND 160V

7 V DD,GND 200V VDD,GND 160V

8 V DD,GND 200V VDD,GND 160V

9 V DD,GND 200V VDD,GND 160V

10 V DD,GND 200V VDD,GND 160V

11 V DD,GND 200V VDD,GND 160V

12 V DD,GND 200V VDD,GND 160V

13 V DD,GND 200V VDD,GND 160V

14 V DD,GND 200V VDD,GND 160V

15 V DD,GND 200V VDD,GND 160V

16 V DD,GND 200V VDD,GND 160V

17 V DD,GND 200V VDD,GND 160V

18 V DD,GND 200V VDD,GND 160V

19 V DD,GND 200V VDD,GND 160V

20 V DD,GND 200V VDD,GND 160V

21 V DD,GND 200V VDD,GND 200V

22 V DD,GND 200V VDD,GND 200V

23 V DD,GND 200V VDD,GND 200V

24 GND 200V GND 200V

1. Block Diagrams Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. Timing Charts Timing charts may be simplified for explanatory purposes. 4. Application Circuits The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. Test Circuits Components in the test circuits are used only to ob tain and confirm the device characteristics. These components and circuits are not gua ranteed to prevent malfunction or failure from occurring in the application equipment.

[1] The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. [2] Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or IC failure. The IC will fully brea k down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow and the breakdown can lead smoke or ignition. To minimize the effects of the flow of a large current in case of breakdown, appropriate settings, such as fuse capacity, fusing time and insertion circuit location, are required. [3] If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resu lting from the inrush current at power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or ignition. Use a stable power supply with ICs with built-in protec tion functions. If the power supply is unstable, the protection function may not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition. [4] Do not insert devices in the wrong orientation or incorrectly. Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, dam age or deterioration, and may result injury by explosion or combustion. In addition, do not use any device that is applied the current with inserting in the wrong orientation or incorrectly even just one time. [5] Carefully select external components (such as inputs and negative feedback capacitors) and load components (such as speakers), for example, power amp and regulator. If there is a large amount of leakage current such as input or negative feedback condenser, the IC output DC voltage will increase. If this output voltage is connected to a speaker with low input withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied Load (BTL) connection type IC that inputs output DC voltage to a speaker directly.