TCA4311DRG4

TCA4311 TI | Alldatasheet

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Technical content

FEATURES

www.ti.com SCPS173 DECEMBER 2008 HOT SWAPPABLE 2-WIRE BUS BUFFERS Operating Power-Supply Voltage Range of

Applications

2.7-V to 5.5-V Bus Extension Supports Bidirectional Data Transfer of I C Low I CC Chip Disable of µ A Bus Signals READY Open-Drain Output SDA and SCL Lines Are Buffered Which Supports Clock Stretching, Arbitration, and Increases Fanout Synchronization 1-V Precharge on All SDA and SCL Lines Powered-Off High-Impedance I C Pins Prevents Corruption During Live Board Open-Drain I C Pins Insertion and Removal From Backplane Latch-Up Performance Exceeds 100 mA Per SDA and SCL Input Lines Are Isolated From JESD 78, Class II Outputs ESD Protection Exceeds JESD Accommodates Standard Mode and Fast Mode 8000-V Human-Body Model (A114-A) I C Devices 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) D OR DGK PACKAGES (TOP VIEW) The TCA4311 is a hot swappable I C bus buffer that supports I/O card insertion into a live backplane without corruption of the data and clock busses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, this device provides bidirectional buffering, keeping the backplane and card capacitances isolated. During insertion, the SDA and SCL lines are precharged to V to minimize the current required to charge the parasitic capacitance of the chip. When the I C bus is idle, the TCA4311 can be put into shutdown mode by setting the EN pin low. When EN is high, the TCA4311 resumes normal operation. It also includes an open drain READY output pin, which indicates that the backplane and card sides are connected together. When READY is high, the SDAIN and SCLIN are connected to SDAOUT and SCLOUT. When the two sides are disconnected, READY is low. Both the backplane and card may be powered with supply voltages ranging from 2.7 V to 5.5 with no restrictions on which supply voltage is higher. The TCA4311 has standard open-drain I/Os. The size of the pullup resistors to the I/Os depends on the system, but each side of this buffer must have a pullup resistor. The device is designed to work with Standard Mode and Fast Mode I C devices in addition to SMBus devices. Standard Mode I C devices only specify mA in a generic I C system where Standard Mode devices and multiple masters are possible. Under certain conditions, high termination currents can be used. Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. CompactPCI is a trademark of PCI Industrial Computer Manufacturers Group. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ORDERING INFORMATION T A PACKAGE (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC D Tape and reel TCA4311DR PR311 C to C MSOP DGK Tape and reel TCA4311DGKR 3JS (1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging (2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com TERMINAL FUNCTIONS SOIC (D) OR MSOP (DGK) PACKAGE

DESCRIPTION

pin. If EN is low, the TCA4311 is in a low current µ mode. It also disables the rise-time accelerators, disables the bus precharge circuitry, drives READY low, isolates SDAIN EN from SDAOUT and isolates SCLIN from SCLOUT. EN should be high (at V CC for normal operation. Connect EN to V CC if this feature is not being used. SCLOUT Serial clock output. Connect this pin to the SCL bus on the card. SCLIN Serial clock input. Connect this pin to the SCL bus on the backplane. GND Supply ground Connection flag/rise-time accelerator control. READY is low when either EN is low or the start-up READY sequence described in the operation section has not been completed. READY goes high when EN is high and start-up is complete. Connect a 10-k Ω resistor from this pin to V CC to provide the pull up. SDAIN Serial data input. Connect this pin to the SDA bus on the backplane. SDAOUT Serial data output. Connect this pin to the SDA bus on the card. Supply power. Main input power supply from backplane. This is the supply voltage for the devices on V CC the backplane I C busses. Connect pullup resistors from SDAIN and SCLIN (and also from SDAOUT and SCLOUT) to this pin. Place a bypass capacitor of at least 0.01 µ F close to this pin for best results. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TCA4311

100□k RCH1 100□k RCH3 0.5□pF READY UVLO 3SCLIN CONNECT Stop□Bit□and□Bus□Idle GND CONNECT 20□pF RD S QB 0.5□µA 0.55□V / 0.45□V CC CC V – 1□VCC 2□mA 95 µs Delay , Rising Only Backplane-To-Card Connection CONNECTCONNECT

2 SCLOUT

7 SDAOUT

8 VCC

1□V Precharge 100□k RCH2 100□k RCH4 2□mA 2□mA Slew□Rate Detector CONNECT ENABLE 2-Wire□Bus□Buffer□and□Hot□Swap□Controller 2□mA Slew□Rate Dectector Backplane-To-Card Connection Slew□Rate Dectector Slew□Rate Dectector ENABLE TCA4311 www.ti.com SCPS173 DECEMBER 2008 BLOCK DIAGRAM Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TCA4311

(1) RECOMMENDED OPERATING CONDITIONS TCA4311 SCPS173 DECEMBER 2008 www.ti.com over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range 0.5 V V I/O I C bus voltage range (2) SDAIN, SCLIN, SDAOUT, SCLOUT 0.3 V V I Input voltage range (2) EN 0.3 V I IK Input clamp current V I mA I OK Output clamp current V O mA I O Continuous output current mA I CC Continuous current through V CC or GND 100 mA D package θ JA Package thermal impedance (3) C/W DGK package 172 T stg Storage temperature range 150 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The package thermal impedance is calculated in accordance with JESD 51-7. MIN MAX UNIT V CC Supply voltage 2.7 5.5 V SDA and SCL inputs 0.7 V CC 5.5 V IH High-level input voltage V EN input 5.5 SDA and SCL inputs 0.5 0.3 V CC V IL Low-level input voltage V EN input 0.5 0.8 V CC V I OL Low-level output current mA V CC 4.5 V T A Operating free-air temperature C Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TCA4311

www.ti.com SCPS173 DECEMBER 2008 over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Supply V CC Positive supply voltage 2.7 5.5 V I CC Supply current V CC 5.5 V SDAIN V SCLIN V 5.1 mA Supply current in shutdown I SD V EN V 0.1 µ A mode Start-Up Circuitry V PRE Precharge voltage SDA, SCL floating 0.8 1.2 V t IDLE Bus idle time 150 µ s V EN EN threshold voltage 0.5 V CC 0.9 V CC V V DIS Disable threshold voltage EN Pin 0.1 V CC 0.5 V CC V I EN EN input current EN from V to V CC 0.1 µ A t EN Enable time µ s Disable time (EN to t DIS ns READY) SDAIN to READY delay t STOP 1.2 µ s after STOP SCLOUT/SDAOUT to t READY 0.8 µ s READY READY OFF state leakage I OFF 0.1 µ A current V OL READY output low voltage I PULLUP mA 0.4 V Rise-Time Accelerators Transient boosted pull-up I PULLUPAC Positive transition on SDA, SCL, V CC 2.7 mA current Input-Output Connection V OS Input-output offset voltage k Ω to V CC on SDA, SCL, V CC 3.3 (1) 100 175 mV C IN Digital input capacitance pF Output low voltage, input V OL SDA, SCL pins, I SINK mA, 0.4 V V I I Input leakage current SDA, SCL pins V CC 5.5 V µ A (1) The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function of the pullup resistor and V CC voltage is shown in the Typical Performance Characteristics section. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TCA4311

www.ti.com When the TCA4311 first receives power on its V CC pin, either during power-up or during live insertion, it starts in an undervoltage lockout (UVLO) state, ignoring any activity on the SDA and SCL pins until V CC rises above 2.5 During this time, the V precharge circuitry is also active and forces V through 100-k Ω nominal resistors to the SDA and SCL pins. Because the I/O card is being plugged into a live backplane, the voltage on the backplane SDA and SCL busses may be anywhere between V and V CC Precharging the SCL and SDA pins to V minimizes the worst-case voltage differential these pins will see at the moment of connection, therefore minimizing the amount of disturbance caused by the I/O card. Once the TCA4311 comes out of UVLO, it assumes that SDAIN and SCLIN have been inserted into a live system and that SDAOUT and SCLOUT are being powered up at the same time as itself. Therefore, it looks for either a stop bit or bus idle condition on the backplane side to indicate the completion of a data transaction. When either one occurs, the part also verifies that both the SDAOUT and SCLOUT voltages are high. When all of these conditions are met, the input-to-output connection circuitry is activated, joining the SDA and SCL busses on the I/O card with those on the backplane, and the rise time accelerators are enabled. Once the connection circuitry is activated, the functionality of the SDAIN and SDAOUT pins is identical. A low forced on either pin at any time results in both pin voltages being low. For proper operation, logic low input voltages should be no higher than 0.4 V with respect to the ground pin voltage of the TCA4311. SDAIN and SDAOUT enter a logic high state only when all devices on both SDAIN and SDAOUT release high. The same is true for SCLIN and SCLOUT. This important feature ensures that clock stretching, clock synchronization, arbitration and the acknowledge protocol always work, regardless of how the devices in the system are tied to the TCA4311. Another key feature of the connection circuitry is that it provides bidirectional buffering, keeping the backplane and card capacitances isolated. Because of this isolation, the waveforms on the backplane busses look slightly different than the corresponding card bus waveforms, as described here. When a logic low voltage, V LOW1 is driven on any of the TCA4311's data or clock pins, the TCA4311 regulates the voltage on the other side of the chip (call it V LOW2 to a slightly higher voltage, as directed by the following equation: V LOW2 V LOW1 mV CC /R) 100 where R is the bus pullup resistance in ohms Ω For example, if a device is forcing SDAOUT to mV where V CC 3.3 V and the pullup resistor R on SDAIN is k Ω then the voltage on SDAIN (3.3/10000) 100 118 mV. See the Typical Performance Characteristics section for curves showing the offset voltage as a function of V CC and During a rising edge, the rise-time on each side is determined by the combined pullup current of the TCA4311 boost current and the bus resistor and the equivalent capacitance on the line. If the pullup currents are the same, a difference in rise-time occurs which is directly proportional to the difference in capacitance between the two sides. This effect is displayed in Figure for V CC 3.3 V and a 10-k Ω pullup resistor on each side (50 pF on one side and 150 pF on the other). Since the output side has less capacitance than the input, it rises faster and the effective t PLH is negative. There is a finite propagation delay, t PHL through the connection circuitry for falling waveforms. Figure shows the falling edge waveforms for the same V CC pullup resistors and equivalent capacitance conditions as used in Figure An external NMOS device pulls down the voltage on the side with 150 pF capacitance; the TCA4311 pulls down the voltage on the opposite side, with a delay of ns. This delay is always positive and is a function of supply voltage, temperature and the pullup resistors and equivalent bus capacitances on both sides of the bus. The Typical Performance Characteristics section shows t PHL as a function of temperature and voltage for Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TCA4311

52.0 52.025 0.0 1.0 2.5 –0.5 0.5 1.5 3.0 2.0 3.5 52.075 52.1 52.125 t (s) (V) 52.15 52.175 VXSDAIN Delay: 72.258 VXSDAOUT 54.0 54.2 0.0 1.0 2.5 –0.5 0.5 1.5 3.0 2.0 3.5 54.4 54.6 54.8 t (s) (V) VXSDAOUT VXSDAIN Rise-Time Accelerators READY Digital Output EN Low Current Disable TCA4311 www.ti.com SCPS173 DECEMBER 2008 10-k Ω pullup resistors and 100 pF equivalent capacitance on both sides of the part. By comparison with Figure the V CC 3.3 V curve shows that increasing the capacitance from pF to 100 pF results in a t PHL increase from ns to ns. Larger output capacitances translate to longer delays (up to 150 ns). Users must quantify the difference in propagation times for a rising edge versus a falling edge in their systems and adjust setup and hold times accordingly. Figure Input-Output Connection t PLH Figure Input-Output Connection t PHL Once connection has been established, rise-time accelerator circuits on all four SDA and SCL pins are activated. These allow the user to choose weaker DC pullup currents on the bus, reducing power consumption while still meeting system rise-time requirements. During positive bus transitions, the TCA4311 switches in mA (typical) of current to quickly slew the SDA and SCL lines once their DC voltages exceed 0.6 Using a general rule of pF of capacitance for every device on the bus (10 pF for the device and pF for interconnect), choose a pullup current so that the bus will rise on its own at a rate of at least 1.25 µ s to guarantee activation of the accelerators. For example, assume an SMBus system with V CC a 10-k Ω pullup resistor and equivalent bus capacitance of 200 pF. The rise-time of an SMBus system is calculated from IL(MAX) 0.15 to IH(MIN) 0.15 V), or 0.65 V to 2.25 It takes an RC circuit 0.92 time constants to traverse this voltage for a V supply; in this case, 0.92 (10 k Ω 200 pF) 1.84 µ Thus, the system exceeds the maximum allowed rise-time of µ s by 84%. However, using the rise-time accelerators, which are activated at a DC threshold of below 0.65 the worst-case rise-time is: (2.25 V 0.65 200 pF/1 mA 320 ns, which meets the µ s rise-time requirement. This pin provides a digital flag which is low when either EN is low or the start-up sequence described earlier in this section has not been completed. READY goes high when EN is high and start-up is complete. The pin is driven by an open drain pull-down capable of sinking mA while holding 0.4 V on the pin. Connect a resistor of k Ω to V CC to provide the pullup. Grounding the EN pin disconnects the backplane side from the card side, disables the rise-time accelerators, drives READY low, disables the bus precharge circuitry and puts the part in a near-zero current state. When the pin voltage is driven all the way to V CC the part waits for data transactions on both the backplane and card sides to be complete (as described in the Start-Up section) before reconnecting the two sides. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TCA4311

www.ti.com The system pullup resistors must be strong enough to provide a positive slew rate of 1.25 µ s on the SDA and SCL pins, in order to activate the boost pullup currents during rising edges. Choose maximum resistor value R using the formula: R CC(MIN) 0.6) (800,000) C where R is the pullup resistor value in ohms, V CC(MIN) is the minimum V CC voltage and C is the equivalent bus capacitance in picofarads (pF). In addition, regardless of the bus capacitance, always choose R k Ω for V CC 5.5 V maximum, R k Ω for V CC 3.6 V maximum. The start-up circuitry requires logic high voltages on SDAOUT and SCLOUT to connect the backplane to the card, and these pullup values are needed to overcome the precharge voltage. In large 2-wire systems, the V CC voltages seen by devices at various points in the system can differ by a few hundred millivolts or more. This situation is well modeled by a series resistor in the V CC line, as shown in Figure For proper operation of the TCA4311, make sure that V CC(BUS) V CC(TCA4311) 0.5 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TCA4311

–50 –25 0 25 50 Temperature (°C) I (mA)PULLUPAC 75 100 2.7 V2.5 V 3 V 5 V 100 –40 25 85 T emperature, T (°C)A tPHL 2.7 V 3.3 V 5.5 V 52.0 52.025 0.0 1.0 2.5 –0.5 0.5 1.5 3.0 2.0 3.5 52.075 52.1 52.125 t (s) (V) 52.15 52.175 VXSDAIN Delay: 72.258 VXSDAOUT 54.0 54.2 0.0 1.0 2.5 –0.5 0.5 1.5 3.0 2.0 3.5 54.4 54.6 54.8 t (s) (V) VXSDAOUT VXSDAIN TCA4311 www.ti.com SCPS173 DECEMBER 2008 Figure Input/Output t PLH vs Temperature Figure I PULLUPAC vs Temperature Figure Figure Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TCA4311

10,000 20,000 30,000 Voffset33V Voffset5V 40,000 TCA4311 SCPS173 DECEMBER 2008 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Figure Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TCA4311

D.U.T. VCC VCC VI VO RT R 10 k L Ω C 100 pF L SDAn/SCLn ENABLE READ Y ten tdistidle(READ Y) SCLIN SCLOUT SDAOUT SDAIN ENABLE READ Y ten tstp(READ Y) TCA4311 www.ti.com SCPS173 DECEMBER 2008 R L Load resistor C L Load capacitance includes jig and probe capacitance R T Termination resistance should be equal to the output impedance Z of the pulse generators. Figure Test Circuitry for Switching Times Figure Timing for t en t idle(READY) and t dis Figure 10. t stp(READY) That Can Occur After t en Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TCA4311

SCLOUT , SDAOUT SCLIN, SDAIN ENABLE READ Y tstp(READ Y) tidle(READ Y) ten TCA4311 SCPS173 DECEMBER 2008 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Figure 11. t stp(READY) That Can Occur After t en and t idle(READY) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TCA4311

Staggered□Connector R13 10□k R12 10□k R14 10□k I/O□Peripheral□Card□NEN SDAIN SCLIN TCA4311 V CC GND CARDN_SCL CARDN_SDASDAOUT SCLOUT READY EN SDAIN SCLIN V CC GND SDAOUT SCLOUT READY EN Card Enable/Disable SDAIN SCLIN V CC GND SDAOUT SCLOUT READY 10□k 10□k R10 10□k I/O□Peripheral□Card□2 TCA4311 CARD2_SCL CARD2_SDA 10□k 10□k 10□k I/O□Peripheral□Card□1 TCA4311 CARD_SCL CARD_SDA 10□k V CC 10□k Backplane Backplane Connector SDA BD_SEL SCL C1R3 10□k 10□k R11 10□k 0.01□µF 0.01□µF Power□Supply Hot□Swap Power□Supply Hot□Swap Card Enable/Disable Card Enable/Disable Staggered□Connector Staggered□Connector Power□Supply Hot□Swap 0.01□µF TCA4311 www.ti.com SCPS173 DECEMBER 2008 Figure through Figure illustrate the usage of the TCA4311 in features. In all of these applications, note that if the I/O cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise- and fall-time requirements difficult to meet. Placing a TCA4311 on the edge of each card, however, isolates the card capacitance from the backplane. For a given I/O card, the TCA4311 drives the capacitance of everything on the card and the backplane must drive only the capacitance of the TCA4311, which is less than pF. Figure shows the TCA4311 in a CompactPCI configuration. Connect V CC and EN to the output of one of the CompactPCI power supply Hot Swap circuits. Use a pullup resistor to EN for a card side enable/disable. V CC is monitored by a filtered UVLO circuit. With the V CC voltage powering up after all other pins have established connection, the UVLO circuit ensures that the backplane and card data and clock busses are not connected until the transients associated with live insertion have settled. Owing to their small capacitance, the SDAIN and SCLIN pins cause minimal disturbance on the backplane busses when they make contact with the connector. Figure 12. Inserting Multiple I/O Cards into a Live Backplane Using the TCA4311 in a CompactPCI System Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TCA4311

100□k EN SDAIN SCLIN V GND CC SDAOUT SCLOUT READY EN SDAIN SCLIN V GND CC SDAOUT SCLOUT READY 10□k 10□k R10 10□k I/O□Peripheral□Card□2 TCA4311 CARD2_SCL CARD2_SDA 10□k 10□k I/O□Periperal□Card□1 TCA4311 C2□0.1 Fµ 100□kC4□0.1 Fµ CARD_SCL CARD_SDA 10□k VCC 10□k Backplane Backplane Connector SDA SCL 0.01 Fµ 0.01 Fµ 10k Repeater/Bus Extender Application TCA4311 SCPS173 DECEMBER 2008 www.ti.com Figure shows the TCA4311 in a PCI application, where all of the pins have the same length. In this case, connect an RC series circuit on the I/O card between V CC and EN. An RC product of ms provides a filter to prevent the TCA4311 from becoming activated until the transients associated with live insertion have settled. Figure 13. Inserting Multiple I/O Cards into a Live Backplane Using the TCA4311 in a PCI System Users who wish to connect two 2-wire systems separated by a distance can do so by connecting two TCA4311 back-to-back, as shown in Figure The I C specification allows for 400 pF maximum bus capacitance, severely limiting the length of the bus. The SMBus specification places no restriction on bus capacitance, but the limited impedances of devices connected to the bus require systems to remain small if rise- and fall-time specifications are to be met. The strong pullup and pulldown impedances of the TCA4311 are capable of meeting rise- and fall-time specifications for one nanofarad of capacitance, thus allowing much more interconnect distance. In this situation, the differential ground voltage between the two systems may limit the allowed distance, because a valid logic low voltage with respect to the ground at one end of the system may violate the allowed V OL specification with respect to the ground at the other end. In addition, the connection circuitry offset voltages of the back-to-back TCA4311 add together, directly contributing to the same problem. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): TCA4311

10□k 5.1□k 10□k 5.1□k V CC =□5□V 10□k 10□k 10□k 2-Wire□System□1 EN SDAIN SCLIN TCA4311 GND V CC 0.01 Fµ SDAOUT SCLOUT READY SCL1 To□Other System□1 Devices SDA1 0.01 Fµ 10□k 2-Wire□System□2 TCA431 1 EN SDAIN SCLIN SDAOUT SCLOUT READY Long Distance Bus VCC SCL1 SDA1 To□Other System□2 Devices GND VCC 10□k VCC (BUS) 10□k RDROP VCC (TCA4311) SDA SCL 10□k 10□k 10□k SDAIN EN SCLIN TCA4311 VCC GND SCL2 SDA2SDAOUT SCLOUT READY 0.01 Fµ 10□k V CC 3.3□V 10□k EN SCLIN SCLOUT SDAIN SDAOUT 1 5 6 7 3 2 GND TCA431 1 READY 0.01 Fµ 10□k 10□k Input – Output Connection t PLH 52.0 52.025 0.0 1.0 2.5 –0.5 0.5 1.5 3.0 2.0 3.5 52.075 52.1 52.125 t (s) (V) 52.15 52.175 VXSDAIN Delay: 72.258 VXSDAOUT t (s) 0.0 1.0 2.5 –0.5 0.5 1.5 3.0 2.0 3.5 (V) VXSDAOUT VXSDAIN TCA4311 www.ti.com SCPS173 DECEMBER 2008 Figure 14. Repeater/Bus Extender Application Figure 15. System With Disparate V CC Voltages Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TCA4311

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) TCA4311D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA4311DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA4311DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA4311DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA4311DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TCA4311DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 22-Dec-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCA4311DGKR MSOP DGK 8 2500 358.0 335.0 35.0 TCA4311DR SOIC D 8 2500 346.0 346.0 29.0 PACKAGE MATERIALS INFORMATION www.ti.com 12-Dec-2008 Pack Materials-Page 2

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