TC9142P TOSHIBA | Alldatasheet
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Technical content
The TC9142P is a c2-mMos LST developed for con- 16 9 ; trolling the motor of a quartz-lock D.D. record reeeme | ales ° player. Since an 8-bit D/A converter system > has been employed for each of the speed control aiaiaiaiaial + system (AFC) and the phase control system (APC), a Ea a wide reduction of external parts can be made 7 —____—_+ $j $ ‘ei in comparison with conventional capacitor-type rent 4 . S/H systems, thus having realized adjustment | {| A pz) fe free operation. [es] ah B ° . Has built-in AFC and APC, for. each of which —— oo efs0255] 8-bit D/A converter system has been employed. Package wie eeeeasiens do not . Speed-changeover positions are available at ‘Allowable mold protrusion is 0.5mm. 33 1/3 and 45-rpm. [yepee . Crystal can be used up to 12 MHz, and crystal reference dividing frequency is selectable from three positions of 1/4, 1/32 and 1/128 to increase the degree of freedom in the number of FG pulses of motor or crystal frequency, which allows a wide range of design to be made. . External oscillator makes possible fine adjustment of speed. . Provided with strobe reference output and reverse signal output. MAXIMUM RATINGS (Ta=25°C) PIN CONNECTIONS aPoll7 r0flss 745 arcllf® ofxy tosis conporatinn —527—
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_—_— Ome = 709142P ELECTRICAL CHARACTERISTICS (Unless otherwise specified VDD=7.5V, Ta=25°C) ; EST CHARACTERISTIC syMBoL |CIR- TEST CONDITIONS UNIT V; X'tal=6MHz,CPyy=1.5MHz, * v Operating Supply opt) IN Voltage Vpp(2) X' tal=12MHz ,CPyy=3.0MHz,* ~ Operating Suppl ‘tal= =3.0MHz,* . mA Chrrent Ply Ipp X'tal=12MHz ,CP[y=3.0MHz, 5.5 12 XT Operating fMax(2) pp=7.5.¥9.5) Range can max() |, | Yoo Frequency Range fre Vpp=5+0%9-5V,VIN=0-5Vpp, 10 | kHz Vpp=5.0 9.5V,fFGv 10kH2 FG. . DD > DD vi Input Operation | Vin(1) Sine Wave {5 | % Plog | VPP Amplitude = 4 FGjy Threshold v Vop=5.0 09.50, b.2 08 | y Voltage Range TH(FG) At time of DC connection |* VDD x Vpp Deviation Vppe5.0°9.5V, Toyr=0 + x D/A ——- 256 Ladd Re Temperature = * Ladder Resistor 5 Amplifier Feedback | p 5 too | 200 | 500 | ka Resistor £ N1, N2, 33/45, P/S, CPIN vullup Resistor | in Tacepe GPyy Fevainal 0.7 Ni Input "H" Level | VIH Vpp=5-009.5V too] -_| 3 Voltage xcey dN: i : Pee By ands ee L = Bi RV, LD, STROBE, CPouT Pwo [or | Poe ry =] Output oN OH or * ; Ta=Range of -300+75°C —529—
FUNCTIONAL EXPLANATION OF EACH TERMINAL [RON | sympow | TERMINAL NAME FUNCTIONAL & OPERATION EXPLANATION | _ Remarks | “poreony 8 soni a fs | cm fom Ferninal Grown ae 2 | x — |crystar j with a built-in 3 | xp Oscillation Crystal Oscillator is connected. feedback Terminal resistor FG Pulse Input terminal for pulse showing motor |With a built-in FG. pul i . un |7mPue speed. amplifier With a built-in 33, _ |Speed Switching | Terminal for switching motor speed. pull-up 10 45 |verminal L=33 1/3rpm, H or NC=45rpm. resistor. With a built-i hn ps _ |PLAY/sTOP Motor PLAY/STOP signal input terminal [pull-up " Input Terminal L=PLAY, H or NC=STOP resistor. Reference Normally connected to CPQUT- For ex- 14 | cPyy [Frequency ternal fine adjustment input from an Input Terminal | external oscillator. Reference Terminal for divided output from the 15 | cPour [Frequency crystal reference frequency divider. Output Terminal | Normally connected to CPIN- Strobe Output Reference freguency output termianl 13 | srroge |Terminal for strobe. Duty is 1/8. This termianl becomes H when the motor
12 LD Lock Detecting speed is within the lock range and
Terminal otherwise L. AFC output Output terminal for motor speed control AFC uepu system. Output of 8bit D/A converter. Terminal 7 | apc JAPC Output Output terminal for motor phase control Terminal system. Output of 8bit D/A converter. pv [Reverse Signal | Terminal for motor reverse signal Output Treminal | Output.
4 Ny BPEGE GS oi cncy] Switching of divided frequency from the [With @ built-in
5 NQ Switching crystal reference frequency divider pull-up
Terminal into 1/4, 1/32 and 1/128 is possible. | resistor. TOSHIBA CORPORATION —530—
(1) Crystal oscillation terminals (XT, XT ) . The crystal oscillator is used by connecting as shown below. xp kp a cy Oo F t TRIMMER a rt * Cy OF 10~S0pF is appropriate, + Crystal oscillation frequency is calculated by the following equation according to number of FG pulses of a motor to be used. fx = 3/4 FG'x 128% 20*N = 5/9 FG" 128 27xN = 1920 FG'-N (Hz) (Note) 3/4 FG’ : FGry frequency at 45rpm. 5/9 FG' : FGIN frequency at 33 1/3rpm. Further, fx: Crystal oscillation frequency, FG': No. of FG pulses gen- erated per revolution of motor. N : Ratio of frequency division of the crystal reference frequency divider, (Refer to Item (10).) + Maximum operating frequency is above 12MHz and crystals up to 12MHz can be used. (2) Reference frequency input/output terminals (CPouT, CPIN) f . Divided output = from the crystal reference frequency divider is available at CPoyr, which is normally connected to CPqy+ + When an external oscillator (CR oscillator, etc.) is connected to CPyy, motor speed can be finally adjusted. PS = TOSHIBA CORPORATION —531—
(3) Strobe reference frequency output terminal (STROBE) . This is the reference output terminal for strobe and sr ee of crystal oscillation frequency is available at this terminal. . Duty is 1/8 and suited to a single stripe strobe. (4) FG pulse input terminal (FGqN) . This is the input terminal of FG pulse that shows the motor speed. This FG pulse becomes comparison frequency. . This terminal has built-in Amplifier and Schmitt circuit. FC pulses are applied through capacitor coupling and small amplitude is enough for proper operation. (5) Speed switching terminal (33/45) . This terminal is for switching the motor speed 33 1/3 and 45rpm, with a pull-up resistor and chattering preventive circuit. (TRUTH TABLE) 3S DivipED [As [REgtaHox] orneo | z 2 oor No Ay 2 (6) APC, AFC output terminal (APC, AFC) . AFC (speed control output) is a F-V converter for FG frequency, and is consisting of a 8bit D/A converter. . APC (phase control output) is a phase comparator (4-V converter) that compares phase difference é between 1/2 FG and reference frequency FS' , and is also consisting of a 8bit D/A converter. . Both APC and AFC perform the following 3 operations according to FGqy frequency. —532—
a. When FGqy frequency is within the lock range: Both APC and AFC perform the normal operation for FGIN- Further, the Lock range is, Lf +4.6 43.4 (Note) fx case Reference frequency FS* -N-(79-cr 27) TIE (Hz), FS'=4 FS b. When FGzy frequency is below the lock range (under speed): APC and AFC outputs are both fixed at "K" level. c. When FGqy frequency is above the lock range (over speed): APC and AFC outputs are both fixed at “L" level. . When a motor is in STOP state (P/S=H or NC), both AFC and APC are fixed "L" level. —533—
131420 eee eee re—se AFC Output change status for FCqy frequency APC Output change status for phase difference $. Fixed at Mt1eve1 H ' aoa ' é D/A # ' D/a ourPuT ea ' S 1 ss & &5 3 £8 2 x4 > 23 & 28 < Fixed at ‘Lt ¢a rever L L om ° Ed 2 UNDER SPESD. OVER PRED PHAGE DIPEREMOE LOCK RANGE PGzy FREQUENCY . AFC and APC timing chart within lock range. a. AFO (SP8ED CONTROL sy¥sTm) EG PULSE LoaD PULSE OUTPUT ee ee bd. APC (PHASE CONTROL SYSTEM) REFERENCE FREQUENCY FS! PULSE 1 2 $ 2 zo PULSE apo | Oureur TOSHIBA CORPORATION —— —534—
As _ = = 109142P (7) Lock detecting terminal (LD) . This terminal is the lock detecting output and is placed at "H" level when FGIN frequency is within the lock range and otherwise, placed at "L" level. (8) PLAY/STOP input terminal (P/S) : PLAY/STOP signals of the motor are input to this terminal. PLAY=L, STOP=H or NC. . This terminal has a pull-up resistor and a chattering proventive circuit. . During PLAY (P/S=L), AFC, APC and LD perform the above-mentioned oper ations for FGry frequency, and during STOP (P/S=H or NC), AFC, APC and LD are all fixed at "L" level. (9) Reverse signal output terminal (RV) . Reverse signal for braking the motor at time of switching of motor speed from 45rpm to 33 1/3rpm or the operation from PLAY to STOP is output through this terminal. . Change of RV output status wvloUs erat RV OUTPUT CHANGE RV OUTPUT CHANGE During aormai ro-| When the motor speed | Whon the motor spood ie tation (during io switched from gsrpm| locked at $3 1/3rpm, or lock) at asrpm, to 33 1/3rpm, When FGyy 51/8 FS, or When the motor epeed is switched from 33 1/3rpm to 45rpm During normal ro-| When the operation ic | When FG;y21/8FS or When tation (during awitched from PLAY to | the operation ie ewitcned tock) at 33 1/3 | s7oP, from STOP to PLAY, rpm.or 45rpm, . In other cases than above, RV output is not changed and fixed at "L" level. . Further, if FG frequency rises up to 1.5 times of normal rotation at 45rpm. (2 times of normal rotation at 33rpm), RV output is reset. —535—
(10) Reference divided frequency switching terminal (N1, N2) . Divided frequency 1/N of the crystal reference frequency divider can be switched to 1/4, 1/32 or 1/128 by number of FG pulses or a crystal used. . This terminal has a built-in pull-up resistor. ( TRUTH TABLE ) [a [oe [F_[osrone oonror maaimne | 1 fx (We) 32 32x (20 or 27) x 128 L a a ee ae ize | “sexeoer anyxise | W ' CRISTAL REFERENCE L a tx (#2) 4 32x (20 or 27) x 128 (11) Chattering preventing time of P/S, 33/45 terminal: Tc PY/S , 38/45 —T71n_, ic INTERNAL INPUT SIGNAL —_ lr Te [avers [ eorre| 1728 1280 torn foPin 432 320 foPrN foPry FREQUENCY (Ha) eo12 5120 toPIn toPiy TOSHIBA CORPORATION — —536—
2 eee §=—-09142P CHARACTERISTIC TEST CIRCUIT (1) Operating supply current (2) Xp Operating frequency range Ipp Synchroscope £MAX(1),(2) vpp=78¥ Vpp= 5~9sv b> im i x Wis isisie uw o j6 1516 Use 11 10 8 4 © 12345678 t2545678 FS | Vin=05%pp) S fhe t=iaia 8 x'earsiawigl 5, ViN=20Vpp (3) CPyy Operating frequency range (4) FGyy Input sensitivity fmMax(3), (4) VIN(1) , (2) PG Vyp=07 x Vpp (QU) Monitor yr.=03 x Vpp MONITOR Vpp=5~95V a Vvpp=5~95V 1B us wilw 1615 is wu 10D ® 1) t2345678 tes*#5678 - Synchroacope laa | tats X'tal=6Mia QO sa VIN (5) Amplifier feedback resistor (6) Pullup resistor Re RIN 3 ° eye vpp=v | | vpp=v | | if 7 Ww eubeuoD s Wis iiui os]! i 12345678 tassseve| } 28 78 Res Rin=—— f= zy 1) Iw= zy, \\@) toi cornporation —537—
(7) D/A Converter ladder resistor (8) Output current ("H" level) RL Ton Vpp=7.5¥ vpp=7.5¥ ° ° Set input 60 that output [| may attain ‘a? levei, W615 i4 13 2 108 16 —I0H% 12545678 ® Xtal 1 Vou=65V Rigmeserate + © Ops, m= = lw) (9) Output current ("L" level) Vpp=7.8¥ ToL O Set input so that output may attain *L" level, — Ton Vor=10¥ + OF ™ TOSHIBA CORRORATION —538—
70914: TMAX( XT) Tr =7.5V FT v= ; z po a ot Ei FEES “oT iT] berry 7@) 20» PRS coc HEE EH esas - is ssccostit i ceoesereeess ue Hert ! 3 “Tr CL LT | ‘: A i FH T | p= [I ay oH ce a CTT TT] KH ace i : 23 os [TI PT] TT | a3 H : i a8 2 || | aap coo . EE it cE 3 Ra an an) [| mani =: FH | Zam secittedt : PEE isasae ge 4 ann Cr i [saa = a a3 is Raa = : Se Pee 4 oe a - : aeeeeen 16 it) . ” = = tL TACK + 2 me oe 3 eT aan CC r He ; ae aan CC Er = 25 3 ; ; He a r 28 EEE aa H % Cul : : e Poo Sth oO za seerascerees CO LL TT CI] = He as Ba proses taceat eg sreriaeiait a SESaEa PEER af FRESE : FEESperee 84 aipen [TTtt) j pada 7 “ARE 40 re te) 28 ‘TO Zan cee HH HEE
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Pa ‘EECA oo izes ee : T =75V SSH Vp TT Tyop= 3a aa LPitT | i: = a os PTT | sueaa2 Yop () man a : + SUPPL’ a i : °% ING - : z = ana me or: Vop [ ] seneoe 7 feve ‘AAAS loca) 7 “HHS i: ra : = on an 7 aa. a: FS at i HAH Hp 4 © sol 4 HEA ~ a2 ane co 3 aeaee a PEE suite
710 CL CL an as aan eae HH
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2 EEE Et a
g 2 oo FHA ‘ “FEE | ny VOLTAGE a . . + iG SUPPL’ 4 Gopratan a
EXAMPLE APPLICATION CIRCUIT HIGH VOLTAGS y vvpp
3 PLL LOCK
in. 66 6@ DISPLAY LED TUBE h } 38/45 rpm PLAY VDD D Co] \\sT0. 1 2 5 4 58 6 7 Yop x! tat y ae ze aS ea = Ped FG Pulse \\/ DIF FERENTIAL) AMPLIFIER AMPLIFIER It FRECUENCY MOTOR SHEMET oron | coutxoL cIROUIT Example of crystal oscillation frequency calculation When FG' (number of FG pulse)=90 pulses, if the dividing frequency of reference divider is set at N=32 dividing frequency, the crystal oscil- lation frequency fx is as follows + fx = 1920.FG'N = 1920x 90* 32 = 5,5296MHz TosHima CORPORATION — —540—
er __09142P CAUTION IN APPLICATION . APC and AFC terminals are for the 8-bit D/A converter outputs, which are directly output from the R-2R ladder type resistor network as shown in the following diagram. Impedance of these outputs becomes equal to the ladder resistor value RL. Terefore, input impedance at the receiving side of these terminals shall be designed accordingly. aR @1 L-be QC) aPc/aro ourpur Bea %EDe
43 Lam
£3 as [pe RL=S5~80kQ (TYP 58kQ) a5 \\ 5 ! L 3 ' ael-pe aku ‘ aR, . A filter for an externally mounted differential amplifier on an application circuit shall be selected to meet the response characteristic of a motor to be used. a i TASHIBA CORPORATION + —541—