TC90A67F

TC90A67F TOSHIBA | Alldatasheet

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Features

Video Decoder for the Sub-Picture /Gb7/G20NTSC, PAL (Europe), M-PAL and N-PAL systems /Gb7/G20Automatic color system identification /Gb7/G208-bit ADC for a composite video input /Gb7/G20Y/C separation by built-in digital filters /Gb7/G20ACC, Color killer circuits /Gb7/G20Contrast, Brightness, Tint and Color level controls /Gb7/G20Accessible V-chip signal data via. IIC bus Main-Picture System Clock /Gb7/G20External PLL circuit for main-picture system clock (A recommended IC TI: TLC2933) PIP Controller /Gb7/G20525-60 Hz, 626-50 Hz and mixed are available /Gb7/G20Vertical filter /Gb7/G20Field memory (181 kbit) /Gb7/G20PIP mode: Single PIP with 1/9 or 1/16 size, 6 PIPs with 1/36 size /Gb7/G20Flexible PIP position /Gb7/G203ch 8-bit DACs for YUV or RGB outputs /Gb7/G20YUV to RGB converter Others /Gb7/G2042 MHz crystal oscillator /Gb7/G20I2C bus control /Gb7/G20Package: QFP80 /Gb7/G20Power supply: 3.3 V Weight: 1.6 g (typ.) Preliminary

42 MHz

V.Sync Sepa Sync Sepa fH PLL fsc PLL DAC DAC IIC BUS main- timing Gen PDVCO Field Memory Line Memory PVDPHDPHREFCKP XOXI CLMP CVI Yout Rout Bout Ys Compsite signal VD main HD main

Terminal Connection Diagram QFP80-P-1420-0.80B

65 TEST2

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VDD BOUT AVDD NC BIAS1 NC BIAS2 VREFD NC NC VSS CHREF AVSS ROUT AVDD YOUT CVREF CFIELD VDD PVD VSS NC YS PIPEN NC SCL NC CKILL VCHIP RESET V DD SDA AVSS NC AVSS VREFH AVSS NC BIASA NC CKIN AVDD FILTER AVSS NC AVDD CVI AVDD VREFL CKOUT BIASD VREF CLMP CKCSEL CKC VSS TESTM1 TESTM0 NC PHD V SS CKP CKPSEL PHREF NC PFIELD V DD VSS CSTD NC NC V DD NC XO XI V SS TEST VDD TC90A67F (QFP80)

QFP80-P-1420-0.80B PIN Name I/O Function Condition

1 AV SS /Gbe Ground for DAC

2 BIASA /Gbe ADC bias voltage

3 V REFH /Gbe Upper limit reference voltage of ADC normal: 2.3 V

4 AV SS /Gbe Ground for ADC

5 CVI I /G20Composite video signal input

6 AV DD /Gbe Power supply for ADC

7 V REFL /Gbe Lower limit reference voltage of ADC normal: 1.0 V

8 AV SS /Gbe Ground for ADC

9 NC /Gbe

10 CKOUT O 384fH-clock output

11 AV DD O Power supply for VCO

12 BIASD /Gbe DAC bias voltage

13 V REF /Gbe Lower limit reference voltage of DAC normal: 1.8 V

14 NC /Gbe

15 NC /Gbe

16 AV SS /Gbe Ground for VCO

17 FILTER O VCO filter terminal

18 AV DD /Gbe Power supply for DAC

19 CKIN I /G20384fH-clock input

20 NC /Gbe

21 V SS /Gbe Ground for digital circuit

22 CKC I /G20Clock input (sub-picture)

23 CKCSEL I /G20Internal/external 384fH VCO select L: internal, H: external

24 CLMP O Clamp level output

25 V DD /Gbe Power supply for digital circuit

26 TEST I /G20Test pin normal: H

27 V SS /Gbe Ground for crystal oscillator

28 XI I /G2042 MHz crystal oscillator input

29 XO O 42 MHz crystal oscillator output

30 NC /Gbe

31 V DD /Gbe Power supply for crystal oscillator

32 NC /Gbe

33 NC /Gbe

34 CSTD O Internal signal output

35 V SS /Gbe Ground for DRAM

36 V DD /Gbe Power supply for DRAM

37 PFIELD O Field odd/even output (main picture) H: even, L: odd

38 CFIELD O Field odd/even output (sub picture) H: even, L: odd

39 CV REF O Vertical sync. output (sub picture) 40 CH REF O Horizontal sync. output (sub picture)

41 NC /Gbe

PIN Name I/O Function Condition

42 CKILL O Color killer detection output (sub picture) H: color killer ON,

L: OFF

43 VCHIP I /G2023rd-line detect signal output 23rd-line: H

44 RESET I /G20Reset input L: reset

45 V DD /Gbe Power supply for digital circuit

46 SDA I /G2fO I2C BUS data input, data and acknowledge output

47 SCL I /G20I2C BUS clock input

48 NC /Gbe

49 PIPEN I /G20PIP enable normal: H

50 YS O Main, sub-picture switching pulse sub-picture: high

51 NC /Gbe

52 V SS O Ground for digital circuit

53 PVD I /G20Vertical sync. input (main picture) normal: negative

54 V DD O Power supply for digital component

55 NC /Gbe

56 PH REF O Horizontal sync. output (main picture)

57 CKPSEL I /G20CKP frequency selection L: 24 MHz, H: 48 MHz

58 CKP I /G20Clock input (main-picture)

59 V SS /Gbe Ground for digital circuit

60 PHD I /G20Horizontal sync. input (main picture) normal: positive

61 NC /Gbe

62 TESTM0 I /G20Test pin normal: H

63 TESTM1 I /G20Test pin normal: H

64 TESTM2 I /G20Test pin normal: H

65 TEST2 I /G20Test pin normal: H

66 V DD /Gbe Power supply for digital circuit

67 V SS /Gbe Ground for digital circuit

68 NC /Gbe

69 NC /Gbe

70 V REFD I /G20Lower limit reference voltage of DAC normal: 1.8 V

71 BIAS2 /Gbe DAC bias reference voltage

72 NC /Gbe

73 BIAS1 /Gbe DAC bias reference voltage

74 NC /Gbe

75 AV DD /Gbe Power supply for DAC

76 BOUT O Analog signal output (B-Y or B)

77 AV SS /Gbe Ground for DAC

78 ROUT O Analog signal output (R-Y or R)

79 AV DD /Gbe Power supply for DAC

80 YOUT O Analog signal output (Y or G)

6 PIP MODE 2

Size: 1/6 /Gb4 6

6 PIP MODE 1

Size: 1/6 /Gb4 6

1 PIP MODE

TC90A67F has horizontal and vertical sync separation circuit for sub picture, color demodulation circuit for sub picture, horizontal and vertical timing generation circuit for main picture, PIP control circuit. Color demodulation circuit consists of digital circuit, and corresponds to M-NTSC, PAL, M-PAL, N-PAL system. It is possible to process the sub picture easily, according to adopting system clock of 24 MHz by digital PLL circuit locked fH. Horizontal and vertical timing generation circuit uses system clock (24 MHz) generated by analog PLL circuit locked main picture’s fH. PIP control circuit consists of filter for horizontal and vertical reduction, line memory, field memory and according to changing horizontal and vertical reduction factors, it is possible to carry out various pip sizes. 1. ADC, Clamping Circuit Dynamic range of ADC is 1.32 Vp-p whose voltage is fixed in IC. (top voltage is 2.31 V , bottom voltage is 0.99 V) ADC has pedestal clamp function, base voltage is output from CLMP terminal. The pedestal level becomes about 1.32 V . (64LSB) 2. Horizontal and Vertical Sync for Main Picture It is necessary to input main picture’s H-sync and V-sync at PHD and PVD terminal in order to make system clock for readout stored data into the internal field memory. PHD and PVD are fitted to 5 V . It can be inverted the polarity using IICBUS registers WHINV and WNINV at sub address 29hex. At terminals of IC, polarity of H-sync is positive and V-sync is negative. The clocks from external VCO are selectable in 24 MHz and 48 MHz, it can be switched by given voltage to CKPSEL (SDIP: 52 pin, QFP: 57 pin) terminal. (CKPSEL /G3d L: 24 MHz, CKPSEL /G3d H: 48 MHz) 3. The System Clock Locked to the Sub Picture’s Horizontal Sync. The signal converted into the digital environment passes through horizontal sync separation circuit, horizontal locked circuit, which construct PLL circuit, it makes the system clock locked to the sub picture’s horizontal sync. This clock is put in internal VCO and generated the system clock of 24 MHz. 4. Horizontal Reduction It is necessary to limit to frequency bandwidth for Y signal and color difference signal concerning PIP mode. Horizontal reduction is selectable using HWS. (HWS: sub address 10hex) HWS [1:0] Horizontal Reduction Sampling Rate for Y Sampling Rate for Color Difference 00 1/3 4 MHz 1 MHz 01 1/4 3 MHz 0.75 MHz 10 1/6 2 MHz 0.5 MHz 11 1/8 1.5 MHz 0.375 MHz In order to horizontal reduction, LPFs are used for Y signal and color difference signal. It is selectable in two kinds of LPF for Y signal and six kinds of LPF for color difference signal.

1. Vertical Reduction It is necessary to reduce vertical direction concerning PIP mode, and vertical reduction is carried out from multiplication of coefficient as below. Vertical reduction is selectable using VWS. (VWS: sub address 10hex) Vertical Reduction Coefficient Coefficient Coefficient Coefficient Coefficient Coefficient 1/3 (VWS [1:0] /G3d 00) 1/4 1/2 1/4 /Gbe/G20 /Gbe /Gbe 6. The Sub Picture’s Area of Writing in the Field Memory and Reading from the Field Memory Writing start position is defined horizontal start point to write (sub address 16hex: CHS) and vertical start point to write. (sub address 16hex: CVSN or sub address 17hex: CVSP) CVSN: Vertical frequency of sub picture is 60 Hz CVSP: Vertical frequency of sub picture is 50 Hz Horizontal width of the sub picture is defined by sampling number of horizontal direction. (sub address 1Ahex: HSPL) The number of writing vertical lines is determined internally according to vertical frequency of the main picture and VWS. Reading start position is defined horizontal start point to read (sub address 14hex: PHS) and vertical start point to read. (sub address 14hex: PVSN or 15hex: PVSP) PVSN: Vertical frequency of sub picture is 60 Hz PVSP: Vertical frequency of sub picture is 50 Hz Horizontal display size of the sub picture is defined by PHW (sub address 12hex) and the readout number of vertical lines is defined by PVWN (sub address 12hex) or PVWP (sub address 13hex). PVWN: Vertical frequency of sub picture is 60 Hz PVWP: Vertical frequency of sub picture is 50 Hz 7. DACs for Y Signal and Color Difference Signal TC90A67F is built-in three 8 bit-DAC in motion on 24 MHz. Output dynamic range is determined by the difference between VDD and VREFD terminal voltage. Standard level is 1.5 Vp-p. 8. ACC Control ACC control is carried out comparing demodulation result of color burst signal with set reference level by ACCPAL or ACCNTSC register. (ACCPAL, ACCNTSC: sub address 21hex) When compared value is less than the reference level, controller puts on gain, and more than reference level, controller cuts down one. 9. Peaking Circuit for Y Signal It is possible to carry out a clear picture according to putting up some frequency bandwidth when sub picture becomes indistinct picture for reducing high frequency bandwidth using LPF for Y signal. There are two kinds of characteristics for LPF, and it is selectable about gain of four stages respectively using YPKGS and YPKGG. YPKGS: select for LPF characteristics (sub address 10hex) YPKGG: select for gain (sub address 10hex) 10. PGB Matrix Circuit For a built-in RGB matrix circuit, and when RGBON = 1, it can be changed R-Y, Y, B-Y into RGB signal. How to find the value of coefficient (a, b, c) is as below. 1Chex: MTXCR: a, MTXCG2: b, MTXCG1: c (on condition 0 /G3c/G3da /G3c 1, 0 /G3c/G3db /G3c 1, 0 /G3c/G20/G3dc /G3c 1) R /G3d a (R /G2d Y) /G2b Y G /G3d b {/G2d(R /G2d Y)} /G2b c {/G2d(B /G2d Y)} /G2b Y B /G3d (B /G2d Y) /G2b Y

1. Blue Back Function It is possible to control blue back function using BBACK resister. (BBACK: sub address 13hex, BBACK /G3d 1: blue back mode) It is available for only sub picture set to live mode. BBACK is useful when detected V chip or no signal. it can be selected in four kinds of colors using BLEVEL. (BLEVEL: sub address 13hex) 12. Addition of Frame It is possible to add the frame to the sub picture. It is selectable frame width by FRAMEW and adjustable frame color for RGB or R-Y, Y, B-Y respectively by FRAMEYG, FRAMER, FRAMEB. (FRAMEW, FRAMEYG, FRAMER, FRAMEB: sub address 1Ehex) 13. CCD Slice Circuit This IC has a CCD slice circuit, picks up CCD data, the CCD data and CCD slice conditions can be checked on using IIC BUS read mode.

Bus Map (the value in parentheses indicate preseted data. the parts of mesh is fixed, input the indicated value.) Sub Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 (READ) CR13DET CRIN [3:0] CFIELD SBDET AEDGE BEDGE SLV [6:0] 01 (READ) CCDATA [15:0] 02 (READ) NOSIG CVMD525 CNOVPN CVDET60 BCF [1:0] PVMD525 PNOVPN PVDET60 CKIL PD UNLOCK PALDET 10 0 TRAPFIX (0) TRAP358 (0) YDLY1 [1:0] (1) YPKGS (0) YLPFS (0) YPKGG 11 0 0 MF (0) STRO [3:0] (0) TATEON (0) PIPNUM [2:0] (0) RON (0) MSNUM [2:0] (0) MSON (0)

13 BBACK

(0) BLEVEL [1:0] (0) SELGAIN

17 BRTRGB

18 DRAMCLRN

(0) 1 0 WADOS [12:0] (0000) 19 0 0 0 RADOS [12:0] (0000) 1A HSPL [5:0] (32) CLVL [4:0] CTRT [4:0] (00) 1B 0 0 HUEBIAS 1C MTXCB [5:0] (31) MTXCG [24:20] (0C) MTXCG [14:10] (0A) 1E YSDLYS [1:0] (0) FRAMEW [1:0] (0) FRAMEYG [3:0] (0) FRAMER [3:0] (0) FRAMEB [3:0] (0) 1F TYDLY [1:0] (0) 0 PMDFIX (0) PMDS [1:0] (0) OFF2527 (0) SELREV (0) 0 0 0 0 0 PFLDREV (0) CFLDREV (0) RGBON (0) CHLOADN [7:0] (FE) CHLOADP [7:0] (F9) 21 0 0 ACCPAL [6:0] (3A) ACCNTSC [6:0] (51) 22 0 0 KILON [6:0] (0C) KILOFF [6:0] (14) 23 0 0 NTSOFF [6:0] (14) NTSON [6:0] (0C) 24 0 0 0 0 0 0 0 0 0 PIDREF [6:0] (76) 25 0 0 0 0 1 1 1 1 0 0 FSSTM [1:0] (1) FSSEL

Sub Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

26 SSLV [5:0] (20) CCDSBH

[4:0] (0C) CCDSBL [4:0] (4) 27 1 1 0 0 0 0 0 0 0 0 0 0 0 FLDSEL (1) SELFLOOP (0) SLVFIX (1) 28 1 0 1 0 CCDL [3:0] (8) F60 (0) F50 (0) 0 0 0 0 0 WS262 (0) 29 1 0 0 WS262 (0) WVINV (0) WHINV (0) F60 (0) F50 (0) 0 0 0 0 0 0 0 0

Description of I2C Bus Registers Write Command Sub Address Bit Name Preset Comment D15 /Gbe 0 Fix to ‘0’ D14 TRAPFIX 0 Change fsc-trap mode. 0: auto, 1: fix D13 TRAP358 0 Select fsc-trap characteristic. (active at TRAPFIX /G3d 1 only) 0: 4.43 MHz, 1: 3.58 MHz D12, D11 YDLY1 [1:0] 01 Y-output signal delay against U and V output signal (rough). D10 YPKGS 0 Select Y-peaking filter characteristic. 0: hi-band, 1: low-band D9 YLPFS 0 Select Y-horizontal decimation filter characteristic. 0: hi-band, 1: low-band D8, D7 YPKGG [1:0] 00 Select Y-peaking gain level. 00: 0, 01: 1/4, 10: 1/2, 11: 1 D6 to D4 CLPF [2:0] 000 Select R-Y/B-Y horizontal decimation filter characteristic. D3, D2 VWS [1:0] 00 Select vertical decimation. 00: 1/3, 01: 1/4, 10: 1/5, 11: 1/6 10H D1, D0 HWS [1:0] 00 Select horizontal decimation. 00: 1/3, 01: 1/4, 10: 1/6, 11: 1/8 /G20 D15, D14 /Gbe 00 Fix to ‘0’ D13 MF 0 Set single-field display mode. 0: normal, 1: Fixed to single-field display D12 to D9 STRO [3:0] 0000 Select off-and-on cycle of field memory writing. (4 field step) 0000: normal 0001: strobe (once 6 fields) 1110: strobe (once 58 fields) 0010: strobe (once 10 fields) 1111: still D8 TATEON 0 Sub-pictures’ set at multi-pictures 0: horizontal, 1: vertical D7 to D5 PIPNUM [2:0] 000 Set multi-picture numbers of the animation picture. D4 RON 0 Sub-picture display ON/OFF. 0: OFF, 1: ON D3 to D1 MSNUM [2:0] 000 Select multi-strobe pictures number. 000: 1-picture, 001: 2-pictures, 010: 3-pictures, 011: 4-pictures, 100: 5-pictures, 101: 6-pictures 11H D0 MSON 0 Select multi-strobe mode. (0: normal strobe mode, 1: multi-strobe mode) /G20 D15 to D9 PHW [6:0] 011000 1 Sub-pictures range in the main-picture. (horizontal width, rough) 12H D8 to D0 PVWN [8:0] 001001 010 Sub-pictures range in the main-picture (vertical height) , when main-picture is 60 Hz system. /G20 D15 BBACK 0 Replace sub-picture by blue-back at write-memory. 0: normal, 1: blue-back D14, D13 BLEVEL [1:0] 00 Select blue-back level. (DRAMCLRN /G3d 1 or BBACK /G3d 1 only) 00: black, 01: blue1, 10: blue2, 11: blue3 D12 SELGAIN 00 Control internal Y-level. 0: 1.5 times, 1: Twice D11 to D9 PHE0 [2:0] 000 Sub-pictures range in the main-picture. (horizontal width, fine) 13H D8 to D0 PVWP [8:0] 001011 100 Sub-pictures range in the main-picture (vertical height) , when main-picture is 50 Hz system.

Address Bit Name Preset Comment D15 to D8 PHS [7:0] 001010 11 Horizontal starting point of the sub-pictures in the main-picture. 14H D7 to D0 PVSN [7:0] 1001100 Vertical starting point of the sub-pictures in the main-picture , when main-picture is 60 Hz system. /G20 D15 to D9 PHC [6:0] 000000 Set clock frequency of main-picture processing. (set the dividing number of fH PLL.) 15H D8 to D0 PVSP [8:0] 010000 011 Vertical starting point of the sub-pictures in the main-picture , when main-picture is 50 Hz system. /G20 D15 to D8 CHS [7:0] 000110 01 Horizontal starting point to write into the memory in the sub-picture. 16H D7 to D0 CVSN [7:0] 000010 Vertical starting point to write into the memory in the sub-picture at 60 Hz system. /G20 D15 to D10 BRTRGB [5:0] 000000 Control bright at RGB mode. 100000: /G2d32 LSB, 000000: 0 LSB, 011111: /G2b31 LSB D9 /Gbe 1 Fix to ‘1’ 17H D8 to D0 CVSP [8:0] 100010 010 Vertical starting point to write into the memory in the sub-picture at 50 Hz system. D15 DRAMCLRN 0 Field-memory reset 0: normal, 1: reset D14 /Gbe 1 Fix to ‘1’ D13 /Gbe 0 Fix to ‘0’ 18H D12 to D0 WADOS [12:0] 000000 000000 Set start-address to write the memory. (for the memory partition to memorize several sub-pictures at the same time.) /G20 D15 to D13 /Gbe 000 Fix to ‘0’ 19H D12 to D0 RADOS [12:0] 000000 000000 Set start-address to read from the memory. (for the select of sub-pictures in the memory) /G20 D15 to D10 HSPL [5:0] 110010 Set number of horizontal sampling on the input sub-picture. D9 to D5 CLVL [4:0] 00000 Set color-level. 10000: /G2d6 dB, 00000: 0 dB, 01111: /G2b6 dB 1AH D4 to D0 CTRT [4:0] 00000 Set contrast level. 00000: /G2b1 dB, 11111: /G2b3.5 dB /G20 D15, D14 /Gbe 00 Fix to ‘0’ D13 to D8 HUEBIAS [5:0] 000000 Adjustment the demodulation phases for R-Y signal. (NTSC only) 000000: 0°, 111111: /G2b45° 1BH D7 to D0 HUE [7:0] 000000 Adjustment the demodulation phase for R-Y and B-Y signals. (NTSC only) 10000000: /G2d45°, 00000000: 0°, 01111111: /G2b45° /G20

Address Bit Name Preset Comment D15 to D10 MTXCB [5:0] 110001 Set RGB matrix coefficient 1. D9 to D5 MTXCG [24:20] 01100 Set RGB matrix coefficient 2. 1CH D4 to D0 MTXCG [14:10] 01010 Set RGB matrix coefficient 3. /G20 D15, D10 YGOS [5:0] 000000 Set DC offset of sub-picture. (Y or G signal) 100000: /G2d32 LSB, 000000: 0 LSB, 011111: /G2b31 LSB D9 to D5 ROS [4:0] 00000 Set DC offset of sub-picture. (R-Y or R signal) 10000: /G2d16 LSB, 00000: 0 LSB, 01111: /G2b15 LSB 1DH D4 to D0 BOS [4:0] 00000 Set DC offset of sub-picture. (B-Y or B signal) 10000: /G2d16 LSB, 00000: 0 LSB, 01111: /G2b15 LSB /G20 D15, D14 YSDLY [1:0] 01 Timing offset of Ys pulse. 00: /G2d1 ck, 01: center, 10: /G2b1 ck, 11: /G2b2 ck (24 MHz) D13, D12 FRAMEW [1:0] 00 Select the side frame width of sub-picture. 00: OFF (no-frame), 01: narrow, 10: center, 11: wide D11 to D8 FRAMEYG [3:0] 0000 Select frame signal level of PIP. (Y or G signal) D7 to D4 FRAMER [3:0] 0000 Select frame signal level of PIP. (R-Y or R signal) 1EH D3 to D0 FRAMEB [3:0] 0000 Select frame signal level of PIP. (B-Y or B signal) /G20 D15, D14 TYDLY [1:0] 00 Y-output signal delay for U and V output signal. (fine). D13 /Gbe 0 Fix to ‘0’ D12 PMDFIX 0 Clock frequency to read from the memory. 0: auto, 1: fix D11, D10 PMDS [1:0] 00 Select Clock frequency to read from the memory. (active at PMDFIX /G3d 1 only) 00: 12 MHz, 01: 9 MHz, 10: 18 MHz, 11: 16 MHz D9 OFF2527 0 Set 50 Hz/ 60 Hz-conversion mode. (VWS /G3d 1/3 mode only) 0: ON, 1: OFF D8 SELREV 0 Set reverse mode. 0: normal, 1: reverse D7 to D3 /Gbe 00000 Fix to ‘0’ D2 PFLDREV 1 Reverse PFIELD at internal circuit. 0: reverse, 1: normal D1 CFLDREV 0 Reverse CFIELD at internal circuit. 0: normal, 1: reverse 1FH D0 RGBON 1 Select output signal format. 0: YUV, 1: RGB /G20 D15 to D8 CHLOADN [7:0] 111111 Set clock frequency of sub-picture processing at 60 Hz system. (set the dividing number of H-PLL) 20H D7 to D0 CHLOADP [7:0] 111110 Set clock frequency of main-picture processing at 50 Hz system. (set the dividing number of H-PLL) /G20

Address Bit Name Preset Comment D15, D14 /Gbe 00 Fix to ‘0’ D13 to D7 ACCPAL [6:0] 011101 Set ACC reference level (for PAL). 0: Minimum level 127: Maximum level 21H D6 to D0 ACCNTSC [6:0] 101000 Set ACC reference level (for NTSC). 0: Minimum level 127: Maximum level /G20 D15, D14 /Gbe 00 Fix to ‘0’ D13 to D7 KILON [6:0] 000110 Set color killer ON level. 0: Minimum level 63: maximum level It must be set “KILON” /G3c “KILOFF” 22H D6 to D0 KILOFF [6:0] 001010 Set color killer OFF level. 0: Minimum level 63: maximum level It must be set “KILON” /G3c “KILOFF” /G20 D15, D14 /Gbe 00 Fix to ‘0’ D13 to D7 NTSOFF [6:0] 001010 Set level to turn over from NTSC to PAL in NTSC/PAL detector. 0: Minimum level 63: maximum level It must be set “NTSON” /G3c “NTSOFF” 23H D6 to D0 NTSON [6:0] 000110 Set level to turn over from PAL to NTSC in NTSC/PAL detector. 0: Minimum level 63: maximum level It must be set “NTSON” /G3c “NTSOFF” /G20 D15 to D7 /Gbe 000000

000 Fix to ‘0’ 24H

[6:0] 111011 Sensitivity of PAL-IDENT detection. 0: Minimum Sensitivity 63: Maximum Sensitivity /G20 D15 to D12 /Gbe 0000 Fix to ‘0’ D11 to D8 /Gbe 1111 Fix to ‘1’ D7, D6 /Gbe 00 Fix to ‘0’ D5, D4 FSSTM [1:0] 10 Set cycle of color system detection in color sub-carrier frequency detector. (1field step) 0: 1 field 3: 4 fields D3, D2 FSSEL [1:0] 00 Set color system of sub-picture processing. (at FSMO /G3d 11 only) 00: N-PAL, 01: M-PAL, 10: M-NTSC, 11: BG-PAL/4.43NTSC 25H D1, D0 FSMO [1:0] 01 Mode for color sub-carrier frequency search 00: M-NTSC only, 01: BG-PAL/4.43NTSC/GaeM-NTSC, 10: N-PAL/GaeM-PAL/GaeM-NTSC, 11: FSSEL [1:0] /G20 D15 to D10 SSLV [5:0] 100000 Set slice level for CCD. (this data is initial value of peak detector circuit at auto-slice mode.) D9 to D5 CCDSBH [4:0] 01100 Set minimum-width of high-period in start-bit for CCD. 26H D4 to D0 CCDSBL [4:0] 00100 Set minimum-width of low-period in start-bit for CCD. /G20

Address Bit Name Preset Comment D15, D14 /Gbe 11 Fix to ‘1’ D13 to D3 /Gbe 000000

00000 Fix to ‘0’

D2 FLDSEL 1 Control CCD slice 1. D1 SELPLOOP 0 Control CCD slice 2. 27H D0 SLVFIX 0 Fix CCD slice level. 0: fix, 1: auto-slice /G20 D15 /Gbe 1 Fix to ‘1’ D14 /Gbe 0 Fix to ‘0’ D13 /Gbe 1 Fix to ‘1’ D12 /Gbe 0 Fix to ‘0’ D11 to D8 CCDL [3:0] 1000 Set line No. of data slicing for CCD. 1000: 21 H (NTSC) D7 F60 0 Force 60 Hz mode (sub-picture). 0: normal, 1: force D6 F50 0 Force 50 Hz mode (sub-picture). 0: normal, 1: force D5 to D1 /Gbe 00000 Fix to ‘0’ 28H D0 WS262 0 Reverse CFIELD polarity. 0: even high, 1: odd high /G20 D15 /Gbe 0 Fix to ‘0’ D14, D13 /Gbe 11 Fix to ‘1’ D12 WS262 0 Reverse PFIELD polarity. 0: even high, 1: odd high D11 WVINV 0 Set polarity of vertical sync pulse input at pin “PVD” . (main-picture) 0: Negative, 1: Positive D10 WHINV 0 Set polarity of horizontal sync pulse input at pin “PHD”. (main-picture) 0: Positive, 1: Negative D9 F60 0 Force 60 Hz mode (main-picture) 0: OFF, 1: ON D8 F50 0 Force 50 Hz mode (main-picture) 0: OFF, 1: ON 29H D7 to D0 /Gbe 000000

00 Fix to ‘0’

D15 CRI3DET CRI detection. D14 to D11 CRIN [3:0] CRI number detection. D10 CFIELD Field-detection. (sub-picture) 1: 1st field, 0: 2nd field D9 SBDET Start-bit (001) detection. 0: not start-bit detected, 1: start-bit detected D8 AEDGE Caution of too near sampling point for back-edge of data. 0: OK, 1: too near D7 BEDGE Caution of too near sampling point for front-edge of data. 0: OK, 1: too near 00H D6 to D0 SLV [6:0] Slice level data. 01H D15 to D0 CCDDATA [15:0] CCD data including parity bits. D15 NOSIG Result of no-signal detection (sub-picture) 0: exist, 1: not-signal D14 CVMD525 Vertical sync frequency standard/non-standard detection. (sub-picture) 0: Non-standard, 1: Standard D13 CNOVPN Vertical sync detection. (sub-picture) 0: exist, 1: No vertical sync D12 CVDET60 Vertical frequency detection. (sub-picture) 0: 50 Hz, 1: 60 Hz D11, D10 BCF [1:0] System mode detection. (sub-picture) 00: N-PAL, 01: M-PAL, 10: M-NTSC, 11: BG-PAL/4.43NTSC D9 PVMD525 Vertical sync frequency standard/non-standard detection. (main-picture) 0: Non-standard, 1: Standard D8 PNOVPN Vertical sync detection. (main-picture) 0: exist, 1: No vertical sync D7 PVDET60 Vertical frequency detection. (main-picture) 0: 50 Hz, 1: 60 Hz D6 CKIL Color Killer detection. (sub-picture) 0: Killer-off, 1: Killer-on D5 PDUNLOCK H-PLL condition. (sub-picture) 0: Lock, 1: Un-lock 02H D4 PALDET PAL signal detection. 0: NTSC or No-color, 1: PAL CCD Data Slicer Supplementary Explanation SLVFIX SELFLOOP FLDSEL Slice Level Control Circuit Detected Slice Level Feedback Motion Field at Auto Slice ON ON 1st and 2nd field 1 0 /Gbe/G20 Auto slice function works both field. (CCD details sliced at suitable level) ON OFF 1st and 2nd field 1 1 /Gbe Slice level is detecting from value of SSLV resistor, and sliced the most suitable value. (Detected slice level is not feedback at the next field) ON OFF /Gbe 0 1 /Gbe Slice level is fixed value of SSLV resistor. ON ON 2nd field (CFIELD /G3d 0) Renewed slice level reading value of SLV resistor only 2nd field. ON ON 1st field (CFIELD /G3d 1) 0 0 Renewed slice level reading value of SLV resistor only 1st field.

Outline of I2C BUS Control Format Sub-pictures range in the main-picture. (horizontal width) Slave Address A6 A5 A4 A3 A2 A1 A0 R/W 0 0 1 0 1 1 1 1/0 Write Format Read Format Purchase of TOSHIBA I2C components conveys a license under the Philips I 2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips. DATA (MSB) ACK SUB ADDRESS DATA (LSB) SCL START SLAVE ADDRESS (0010111) R/W START ACK END SLAVE ADDRESS (0010111) ACKR/W ACK ACK END SDA DATA (MSB) ACK SUB ADDRESS DATA (LSB) SCL START SLAVE ADDRESS (0010111) R/W ACK ACK ACK END SDA

Maximum Ratings (VSS /G3d/G3d/G3d/G3d 0 V, Ta /G3d/G3d/G3d/G3d 25°C) Characteristics Symbol Rating Unit Supply voltage V DD V SS to VSS /G2b 4.5 V Applied voltage V IN /G2d0.3 to VDD /G2b 0.3 V Applied current I IN /Gb110 mA Power dissipation PD 1538 mW Storage temperature T STG /G2d55 to 125 °C TD-PD (on board mounting) Recommended Operating Conditions Characteristics Symbol Rating Unit Supply voltage V DD 3.0 to 3.6 V Input voltage V IN 0 to V DD V Output voltage V OUT 0 to V DD V Ambient temperature T OPR /G2d10 to 70 °C Ambient temperature ( /Gb0C) Power dissipation PD (mW) 1500 12550 0 1538 25 70 100 500 846 1000

Electrical Characteristics

Digital Part Operating Condition: VDD /G3d/G3d/G3d/G3d 3.3 V, Ta /G3d/G3d/G3d/G3d 25°C Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit Applicable Terminals Consumption current I DD /Gbe /Gbe /Gbe 160 230 mA /Gbe CMOS input V IH1 /Gbe/G20 /Gbe VDD /Gb4 0.8 /Gbe V DD V (Note1)High input voltage Schmitt trigger input V IH2 /Gbe/G20 /Gbe VDD /Gb4 0.8 /Gbe V DD V (Note2) CMOS input V IL1 /Gbe/G20 /Gbe /Gbe /Gbe 0.8 V (Note1)Low level input voltage Schmitt trigger input V IL2 /Gbe/G20 /Gbe /Gbe /Gbe 0.8 V (Note2) High level I IH /Gbe/G20 /Gbe /G2d10 /Gbe /G2b10 /G6dA/G20 (Note1) (Note2)Input current Low level I IL /Gbe/G20 /Gbe /G2d10 /Gbe /G2b10 /G6dA/G20 (Note1) (Note2) High level V OH /Gbe/G20 /Gbe 2.4 /Gbe /Gbe V (Note3)Output voltage Low level V OL /Gbe/G20 /Gbe /Gbe /Gbe 0.4 V (Note3) Note1: CKC, CKCSEL, TEST, SDA, PIPEN, CKPSEL, CKP, TESTM0, TESTM1, TESTM2, TEST2 Note2: RESET, SCL, PVD, PHD Note3: CLMP, CSTD, PFIELD, CFIELD, CV REF, CHREF, CKILL, VCHIP, Ys, PHREF ADC Characteristics Operating Condition: VDD /G3d/G3d/G3d/G3d 3.3 V, Ta /G3d/G3d/G3d/G3d 25°C Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit Applicable Terminals Resolution R S1 /Gbe /Gbe /Gbe /Gbe 8 bit /Gbe Input level ADIN /Gbe/G20AVDD /G3d 3.3 V /Gbe 1.32 /Gbe V p-p CVI BIASA /Gbe/G20 /Gbe 0.9 V BIASA VREFH /Gbe/G20 /Gbe 2.3 V V REFH Pin voltage VREFL /Gbe/G20 /Gbe 1.0 V V REFL Non-linear error ILE1 /Gbe/G20(8 bit precision) /Gbe /Gbe /Gb13 LSB /Gbe Differential non-linear error DLE1 /Gbe/G20(8 bit precision) /Gbe /Gbe /Gb12 LSB /Gbe DG DG /Gbe/G20 /Gbe 0 /Gbe 6.5 % /Gbe/G20 A/D converter DP DP /Gbe/G20 /Gbe/G20 0 /Gbe/G204.0 deg /Gbe/G20

DAC, VCO Characteristics Operating Condition: VDD /G3d/G3d/G3d/G3d 3.3 V, Ta /G3d/G3d/G3d/G3d 25°C Characteristics Symbol Test Circuit Test Condition Min Typ. Max Unit Applicable Terminals Resolution R S2 /Gbe /Gbe /Gbe /Gbe 8 bit /Gbe YOUT /Gbe/G20(VDD /G2d VREFD) /Gbe /Gbe 1.5 V p-p YOUT ROUT /Gbe/G20(VDD /G2d VREFD) /Gbe/G20 /Gbe/G201.5 V p-p ROUT Output level BOUT /Gbe/G20(VDD /G2d VREFD) /Gbe/G20 /Gbe/G201.5 V p-p BOUT Non-linear error ILE2 /Gbe/G20(8 bit precision) /Gbe /Gbe /Gb11/G20 LSB /Gbe Differential non-linear error DLE2 /Gbe/G20(8 bit precision) /Gbe /Gbe /Gb11 LSB /Gbe BIAS1 /Gbe/G20 /Gbe 0.8 1.0 1.4 V BIAS1 Pin voltage BIAS2 /Gbe/G20 /Gbe 1.8 2 /G2e0/G20 2.2 V BIAS2 Reference voltage level VREFD /Gbe/G20 /Gbe 1.8 /Gbe /Gbe V V REFD D/A converter (VIDEO) Output impedance ZOUT1 /Gbe/G20 /Gbe /Gbe 200 /Gbe /G57/G20 YOUT, ROUT, BOUT Resolution R SD2 /Gbe/G20 /Gbe /Gbe /Gbe 6 bit /Gbe Output level CKOUT /Gbe/G20(VDD /G2d VREF) /Gbe /Gbe 2.0 V p-p CKOUT Non-linear error ILE3 /Gbe/G20(6 bit precision) /Gbe /Gbe /Gb13 LSB /Gbe Differential non-linear error DLE3 /Gbe/G20(6 bit precision) /Gbe /Gbe /Gb12 LSB /Gbe Pin voltage BIASD /Gbe/G20 /Gbe 0.8 1.0 1.4 V BIASD Reference voltage level VREF /Gbe/G20 /Gbe 1.3 /Gbe /Gbe V V REF D/A converter (CLOCK) Output impedance ZOUT2 /Gbe/G20 /Gbe /Gbe 200 /Gbe /G57 CKOUT Pull-in frequency FCK1 /Gbe/G20 /Gbe 5.4 6.0 6.6 MHz /Gbe Input amplitude VCK /Gbe/G20 /Gbe 1.0 2.0 /Gbe V CKIN Pull-in oscillation frequency FCK2 /Gbe/G20 /Gbe 21.6 24.0 26.4 MHz /Gbe VCO FILTER terminal voltage FILTER /Gbe/G20 /Gbe 0.8 /Gbe 2.7 V FILTER

0.1 /G6dF 10 k/G57 510 /G57 14 13 12 11 10 9 8 1 2 3 4 5 6 7 CVREF NC TC90A67F (QFP80) 270 k/G57 R15 C13 0.1 /G6dF 6 pF 8.2 k/G57 30 k/G57 TEST2 TESTM2 171 8765432 161514131211109 18 19 20 21 22 23 24 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VDD BOUT AVDD NC BIAS1 NC BIAS2 V REFD NC NC V SS CHREF AVSS ROUT AVDD YOUT CFIELD VDD PVD VSS NC Ys PIPEN NC SCL CKILL VCHIP RESET VDD SDA AVSS NC AVSS VREFH AVSS NC BIASA NC CKIN AVDD FILTER AVSS NC AVDD CVI AVDD VREFL CKOUT BIASD VREF CLMP CKCSEL CKC V SS TESTM1 TESTM0 NC PHD VSS CKP CKPSEL PHREF NC PFIELD VDD VSS CSTD NC NC V DD NC XO XI VSS TEST VDD 10 k/G57 0.1 /G6dF 0.1 /G6dF 47 k/G57 1 k/G57 C18 CSTD C16 C20 PFIELD CFIELD CV REF CHREF LQ13 C26 0.1 /G6dF 10 k/G57 C27 0.1 /G6dF C29 C28 0.1 /G6dF R17 C25 0.1 /G6dF TLC2933 C33 0.1 /G6dF R19 560 /G57 10 /G6dF TLC2933 LQ17 0.1 /G6dF C30 74HC14AP PHD SCL Ys PVD HD 2SC1815 2SC1815 2SC1815 R21 R22 R23 4.7 k/G57 4.7 k/G57 4.7 k/G57 B-Y (B) OUT Y (G) OUT R-Y (R) OUT /G2b3.3 V VSS LQ18 LQ19 SDA 1.5 k/G57 R9 2SC1B15 LQ10 1 /G6dF 2SC1815 VIDEO C2 10 /G6dF CKC SW1 LQ12 LQ11 CKIN BOUT ROUT YOUT SW2SW3PHREF 0.1 /G6dF C24 LQ7 VIDEO INPUT R13 0.1 /G6dF VCHIP CKILL 0.1 /G6dF C22 C23 8.2 k/G57 R16 R24 470 /G57 R25 470 /G57 R26 470 /G57 C34 6 pF C35 6 pF C36 C41 Q 1 /G6dF LQ14 LQ15 LQ16 C31 0.1 /G6dF C32 R18 3 k/G57 R20 2 k/G57 R7 R8 0.01 /G6dF C12 0.1 /G6dF C14 0.1 /G6dF C10 820 /G57 R11 C15 180 pF 360 /G57 R10 LQ9 4 pF C11 1 k/G57 68 pF 33 k /G57 LQ5 LQ6 LQ8 C37 100 /G6dF C38 0.1 /G6dF C39 100 /G6dF C40 0.1 /G6dF LQ1 LQ2 LQ3 LQ4 0.1 /G6dF C17 12 pF R12 1.5 /G6dH CY1 0.1 /G6dF R14 30 k/G57 100 /G57 1000 pF TC90A67F 0.1 /G6dF 0.1 /G6dF C4 0.1 /G6dF C5 0.1 /G6dF 0.1 /G6dF C6

Weight: 1.6 g (typ.)

/Gb7/G20TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. /Gb7/G20The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. /Gb7/G20The products described in this document are subject to the foreign exchange and foreign trade laws. /Gb7/G20The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. /Gb7/G20The information contained herein is subject to change without notice. 000707EBARESTRICTIONS ON PRODUCT USE