TC90A13N

TC90A13N TOSHIBA | Alldatasheet

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TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC90A13N, TC9I0A13F The TC90A13N and TC90A13F separate luminance (Y) and TC90A13N chrominance (C) signals from an NTSC composite video signal. It employs the Toshiba original logical comb filter to realize high performance Y/C separation at low cost.

FEATURES

@ NTSC system @ PLL 4X multiplication circuit SDIP28-P-400-1.78, @ Sync. tip clampping circuit TC9OA13F @ 8bit A/D converter _ @ 8bit D/Aconverters (2ch) _ @ 2H line memory NI ee a \\ © Dynamic comb filter S e@ 1 line dot correction circuit SOP28-P-450-1.27 © Vertical enhancer Weight SDIP28-P-400-1.78 : 1.7g (Typ.) @ Color killer mode (Y/C separation OFF) SOP28-P-450-1.27 : 0.8g (Typ.) @ Chrominance wide band output mode @ SDIP28/SOP28 package @ 5V single power supply 961001EBA2 @ TOSHIBA is continually working to improve the quality and the reliability of its products, Nevertheless, semiconductor devices in general can malfunction or fall due to their inherent electrical sensitivity and vulnerability to physical stress. itis the responsibilty of the buyer, when utliing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified ‘operating rangot as tot forth in the most recent products pecificatione. Alzo, pleaze keep in mind the precautions and conditions tet forth in the TOSHIBA Semiconductor Reliability Handbook. & The products described in this document ae subject to foreign exchange and foreign trade control laws The [Information contained herein is presented only as a guide for ‘the applications, of our products. No responsiblity is assumed by, TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. © The information contained herein is subject to change without notice 1997-11-18 1/14

CHO) ©) cuamec G Enhancement Circuit Circuit aol ? © evo Color Killer Kid) KILLER 53) veers Dynamic 1 Line Dot Correction CBF Comb Filter reat ° —? ¢ DAC (23) couT vei CO (3) (©) 1LINE cBPF TERMINAL CONNECTION DIAGRAM vert (1) 28) vssa vssi QJ R)) vooa voo1 G) [35 vrers vrerH (4) 25) Your avin G) (24) Biasa Bias; ©) (23) couT ciamec GJ [22) Bias3 test: @} 2} vss3 1/2Vp @} RD Vos veil GQ} (19) CORING cxin GY Onn Voo2 @ [i venus vss2 [7 vennio KILLER (4) (15) capr (TOP VIEW) 1997-11-18 2/14

PIN | NAME FUNCTION PIN | NAME FUNCTION | 1 [VREFL [Bias for ADC CBPF L:.C-BPF = WIDE, H : NARROW Vertical edge enhanced level GND for ADC VENHO | (VENHO, VENH1) =(L, L) = OFF : L_: 1 line color ON | 4 |vrern Bias for ADC TUNE |. 4 line color OFF : . L_: Coring ON [6 BIAS; [Bias for ADC ————~*d:«20 [V3 _| Vp for digital Clamp filter | 21 |Vss3__| GND for digital Le _ [Test BIAS3 | Bias for DAC [9 _[1/2Vpp [Bias for line memory [23 [cour | 10 [VFL [VCO filter | 24 |BIAS2 _ | Bias for DAC CKIN [Clock input YOUT KILLER [L: Color, H: B/W mode GND for DAC (Note) Pin9 and Pin 26 require external bias 1997-11-18 3/14

FUNCTION BLOCK DESCRIPTIONS 1. Input clamp (CLAMP) This block performs sync tip clamping of the composite video signal. It provides a feedback signal for clamping A/D-converted minimum data at Y/C separation to the internal DC bias level. 2. A/D converter (ADC) This block comprises a high-speed series-parallel 8bit A/D converter that accepts an input video signal of 1.5Vp-p (from sync level to 100% white level). 3. 1H memory This block consists of DRAM resident line memory for 1H delay. The 3-line comb filter is configured from two pairs of line memory. 4. Vertical edge enhancement circuit (VENH) This block enhances the uncorrelated components among the three lines of the luminance signal following coring. There are three enhancement level selections of HIGH (1.9dB), MID (1.0dB) and LOW 0.5dB). The luminance signal, obtained by subtracting the chrominance signal from the composite video signal, is added to the vertical edge enhancement component and output through the D/A converter. However, this output signal is limited to the pedestal level (fixed internally) by the pedestal clipping circuit (except for the sync tip level). 5. Horizontal band-pass filter (BPF) In this block, with fsc as the center frequency of the BPF, the chrominance signal is extracted from the 0H, 1H and 2H delayed composite video signal. Since the BPF for the chrominance signal output can be controlled (ON or OFF), the chrominance output can therefore be switched between a narrow band width and a wide band width. 6. Vertical dynamic comb filter (DCF) This block comprises a band-pass filter that extracts the vertical component of the chrominance signal. Using Toshiba original logic, a correlation of the three lines is sought for. The absence of correlation is taken as an indication of a luminance signal, at which time chrominance signal output is suppressed. 7. 1-line dot correction circuit Previously, a 1-line-only chrominance signal was processed as a luminance signal resulting in dot crawl. This circuit prevents this problem by extracting the 1-line dot component and adding it to the dynamic comb filter output. This circuit block can be set ON or OFF. 8. Clock and memory timing generator (RTIM) This block supplies a 4 fsc (PLL 4X multiplied) buffered signal to the other circuit blocks, and also generates a timing signal for the memory. 9. D/A converter (DAC) This block comprises a high-speed 8bit D/A converter. It provides Y output at approximately 1.5Vp-p and burst-level C output at approximately 572MVp-p- 1997-11-18 4/14

KILLER | CBPF_|VENHO|VENH1|1_LINE KCORING Pap [= [= [— | — Wie separation OFF [B/W mode (killer Chrominance signal L horizontal band width Passes through or for t WIDE chrominance signal outpu Chrominance signal horizontal band width Does not pass through BPF for NARROW omii e signal outpu’ P= rentcal enhance OFF — [No vertical enhancement | H L Vertical enhance level | Vertical enhancement level MID 0.5dB L H Vertical enhance level | Vertical enhancement level LOW 1.0dB H H Vertical enhance level Vertical enhancement level HIGH 1.9dB PF ine cotor ON |1 Tine dot correction circuit ON | — | — | — | — | H | — |1 line color OFF 1 line dot correction circuit OFF a Coring circuit ON pO Jcoring OFF J Coring circuit OFF | RATINGS AND CHARACTERISTICS The following specifications were obtained in part from the test circuit shown on page 8. MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING UNIT Power Supply Voltage Input Voltage -0.3~Vpp +0.3 sipation [ROATIN [300 TeannTar-| °° 82° | apg —] (Note) Ta=75°C RECOMMENDED OPERATING CONDITIONS CHARACTERISTIC SYMBOL TEST CONDITION | man. | t¥e. [ max. | UNIT Power Supply Vohage | Vop | — | 475] 50] 525] v_| input Voltage [vy fp -| of — [vp | v_| Operating Temperature | Top | =| =| — | 75] “c | 9997-11-18 5

ELECTRICAL CHARACTERISTICS

DC CHARACTERISTICS (Ta = 25°C, Vpp =5V) TEST CHARACTERISTIC SYMBOL | CIR- TEST CONDITION TYP. | MAX. | UNIT CUIT Power Supply Voliage Supply Current [pp 1 | [- 40[—60| 80] mA | pure voto et esr | Ess rof—er| | Output Voltage Level 1 Vv | 3.9] 40] 41] VREFL | 14] 15] 16! [ ADIN | |ctock=3.579545mHz = |_15[ 1.6] 1.8] Pin Voltage Level [ BIAS, | VREF1 =3.0V [| o8[ 16[ 2.6) v BIAS3 1/2Vpp =2.5V [ 24] 34] 4.4] CLAMPC VIN =No input (Note 2) [ 20] 3.0] 4.0] [0s] +9] 29] [+5] 22] 30] [High tevel | Vin [7 | [alt= = | I Volt npr veneer a ADIN Pin Input Capacitance | — | so] — | pF | Pull Down Resistance [fro | 1 | [50] 700] | (Note 1) External bias must be applied at Pin9 and Pin 26. (Note 2) Ipp is Vijj=modulated lamp wave. 1997-11-18 6/14

Y output (Ta=25°C, Vpp=5V, Clock frequency 3.579545MHz, 0.5Vp-p, $1 =2, VREF1 =3.0V) TEST }_cianacrensnc | sro. |H¢| test conormon [van] re. [ax | unr CUIT input Level O=T40IRE [= [7516] Vos | Low Frequency Gain GV VIN = 15.734kHz, 1.5Vp-p 0.5 Vde =2.5V S4=1, $5=2 Frequency Response ViIN=1.5V ened 2 - - wef gcse [arn ol =o $2=2, $3=2, Comb Characteristics comb | 1 [S4=1,S5=2 2/83 45 VIN = 1-5Vp-p Vde =2.5V ls 1 $2=1, $3=1, yusy2 oe $4=1, $5=2 Linearity (Fig.1) . % L 1 Vin =5 step signal, s/Y2 57 y 1.5Vp-p (Fig.2) $2=1, $3=1, $5=2 VIN = 15.734kHz, 1.5Vp-p Output Impedance 1 Vde=2.5V 700) 2 Zo =e x 400 on v2 V1: $4=1, V2: $4=2 Clock Leakage $2=2, $3=2, $4=1, S5=1 (4f,¢ Components) fe | + | Vin =No input | - | 5.0 20 |mVrms Fundamental Clock Leakage L $2=2, $3=2, S4=1, S5=1 10 mv, (f5¢ Components) sc Vin =No input : rms 1997-11-18 7/14

C output (Ta=25°C, Vpp =5V, Clock frequency 3.579545MHz, 0.5Vp-p, $1=1, VREF1 =3.0V) TEST CHARACTERISTIC SYMBOL | CIR- TEST CONDITION Typ. | MAX. | UNIT CUIT Difference of amplitude WIDE BWwcw 1 |between 1fs¢ and 1fs¢- 503496Hz BPF VIN= 1.5Vp-p, Vde = 2.5V Characteristics $2=2, $3=2, S4=1, S5=2 Difference of amplitude NARROW | BWCN 1 |between 1fsc and 1fs¢— 503496Hz VIN=1-5Vp-p, Vde = 2.5V $2=2, $3=2, a S4=1, $5=2 Comb Characteristics Comb VIN =430mVp.p, 3/42 30 35 Vde =2.5V Differential Gain 1 |Vin=5 step signal, 5] % Y = 1401RE = 1.5Vp-p C=AOIRE (Fig.2) Differential Phase DG = (Comax - Comin) / 2 5 Comax (Fig.3) $2=2, $3=2, $5=2 VIN =15.734kHz, 1.5Vp-p Vde=2.5V Output Impedance © , 250 700} Q Zp ate? x 400 on V2 Clock Leak $2=2, $3=2, $4=1, S5=1 Fundamental Clock Leak L S2=2, $3=2, S4=1, SS=1 mv (f¢¢ Components) s¢ Vin=No input rms #1 = 15.734kHz, f2 =3.587412MHz, f3 =3.595279MHz, f4 = 4.783216MHz PLL CIRCUIT CHARACTERISTICS TEST CHARACTERISTIC SYMBOL | CiR- TEST CONDITION TYP. | MAX. | UNIT CUIT Pullin Frequengy Range | ek [1 [| -387) 358] 358 | maz | Input Amplitude (fs¢ Components) Vek 1 Vp-p 1997-11-18 8/14

T Tot T REPT tack Te bet | g at fete ss 13) jst es st 1° Tope ogg a Tope 1A m2 Spectrum ~ ° ° Vector id Pg 3 = s gl 1997-11-18 9/14

Linearity test (Fig.1) 5 Step signal (Fig.2) Cin 3.58MHz (40 IRE) 2] 5 | al a s| = «| 2 iS 8} = £|£ |= c| e| < Ele g]c ff] oc e Es Ea —+ > — > 2]? 2/2 1H 63.5ys Chroma differential gain (Fig.3) x z e o REFERENCE DATA (Fig.4-a) Definition of vertical edge enhancement INPUT b ourut ore! FAT, (Note) The output signal, to which the vertical edge enhancement component is added, is limited to pedestal level by the pedestal clip circuit. 1997-11-18 10/14

(Fig.4-b) Vertical edge enhancement characteristic 40 ON 30 a S

20 Go ge,

-10f 0 eT a wr" -20 an, -30 NG pf ~40 Yy -50 300 = 100 100 300 a (Fig.4-c) Vertical edge enhancement characteristic (detail) The relation between a and b. (refer to Fig.4-a) a: The difference in luminance level is in the 10 enhanced part of the edge. 8 b: The component of vertical edge enhancement 6 that is added to the luminance signal. Both are expressed as digital values. b ; — (A) Enhance Value HIGH 77+ (8) MID -==~* (C) LOW ? — = (0) Enhance value HIGH — = (£) MID —-- (F) LOW -8 A,B, C: Coring=OFF , E, F : Coring=ON -10 -30 -10 10 30 a (Fig.5) Frequency characteristics of chroma output (a8)

0 T T T T T

i i ! i ' toy — Wide band width ~ 605 ? H é 3 ==++ Narrow band width (MHz) 1997-11-18 11/14

3, your cour > 8 = 8 § 8 10 pF I" ue g 10. Oo Et [Om OME OM OMI OME OME ORE OME OREO REC) s s frh.«| cers fs eh ch (ee F598 78h [et Bee ts] be Tot 7B = Je” als] te] 72) Pee 2 [| 10«0 . e Aa i] Go 10K, cuock Fs 20 5V e @ VIDEO IN ra ? os «SBT 1-18 12/14

SDIP28-P-400-1.78 Unit : mm Yo 28 15 7 nooo ° ) q ° = 38 ep “CITICICICICICICICICI CITI & 1 14 26.1MAX 25.6+0.2 po Sg HTT OU esos | zig —3s 3 L243TYP 1,010.1 0.46+0.1 (G[o.16 Weight : 1.7g (Typ.) 1997-11-18 13/14

SOP28-P-450-1.27 Unit : mm 28 15 ; HEHEHE RHUDHOO pm) p | ik | si | 1 | ROH HERR G GET “I 4 14 O.995TYP 0.4320.1 10.25 @ 19.0MAX 18.5+0.2 jp ba |B i be TOT, 8 @ 3 5 70.1] 3 3 1,0#0.2 Weight : 0.8g (Typ.) 1997-11-18 14/14