TC9090AN

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 23

Technical content

TENTATIVE TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC9O90AN, TCIO90AF MULTICOLOR SYSTEM VERSION 3-LINE DIGITAL Y/C SEPARATION IC The TC9090AN and TC9090AF separate luminance (Y) and TC9090AN chrominance (C) signals from a multicolor system composite video signal. It employs the Toshiba logical comb filter to realize high performance Y/C separation at low cost.

FEATURES

© TV systems : NTSC, PAL, N-PAL, M-PAL, 4.43NTSC SPIP28-P-400-1.78 TC9O90AF @ PLL 4x multiplication circuit @ Sync tip clamping circuit a @ Internal 8bit A/D converter a an © Internal 8bit D/A converters (2ch) NY Ve qALUet . e@ 4H line memories @ Dynamic comb filter SOP28-P-450-1.27 4; . So Weight @ 1-line dot interference correction circuit SDIP28-P-400-1.78 : 1.7g (Typ) © Vertical edge enhancement circuit SOP28-P-450-1.27 : 0.89 (Typ.) @ Color killer mode (Y/C separation OFF) @ Chroma output band width selectable e (?C bus control @ SDIP28/SOP28 package @ 5V single power supply 1 2001-06-19

O—-O HW 7 ouput | = saan Tf Dynami Tine dot K—— | feoac] y Bus TERMINAL CONNECTION DIAGRAM vrerH (1) 28) Vssa Vssi Q] 7) Vopa aon GY [58 vaers Vop1 @) [25) out vrert G} (23) aias2 aast @] [3 cour pis @) (22) Bias3 soa @] b) 1/2vpp sc. Q} Bd ve. reset GO (9) cxin rest! GY [9 voo2 TesT2 (2 11?) Vss2 xituer (J [9 vss3 pLiset Ca} (5) Voo3 (TOP VIEW) 2 2001-06-19

rN | NAME FUNCTION INTERFACE CIRCUIT VREFH ADC bias higher limit reference voltage. This defaults internally to approximately 3.5V, so this pin should c normally be connected to ground through a 0.01F § capacitor. 5 Ss S ER 3 Composite video signal input. H -—~ L al [4 [Vop1 [ADC Power supply (+50. [= VREFL ADC bias lower limit reference voltage. This defaults internally to approximately 1.5V, so this pin should cd normally be connected to ground through a 0.01uF 3 capacitor. 5 g BIAS1 ADC bias voltage. This defaults internally to approximately 1.3V, so this pin should normally be oO) connected to ground through a 0.01F capacitor. 13V 5 7 |P/S Control mode select. L_: PC bus control H_: Pin control om SDA PC bus | Data input, acknowledge output. 1/0 (Tvsw1) © —be pr | TV system select. || 3 2001-06-19

rN | NAME FUNCTION INTERFACE CIRCUIT SCL PC bus | Clock. (Tvsw2) a ee RESET [PC bus [Data reset SCS (tvsw3) [Pin __| TV system select. [1 | 11 =| TEST1 C bus | Test terminal. Normally connected to digital (VENHO) ground. " 2 TEST2 VC bus | Test terminal. Normally connected to digital & (VENH1) ground. [Pin _| Vertical edge enhancement level select. [1 | 13 | KILLER | Color killer mode select. L_: Color H_: Black and white PLLSEL | PLL circuit select. (Switches input clock frequency.) L_: PLL ON, fsc input H_: PLL OFF, 4fsc input @® = | 15 |Vpp3 Power supply for digital components (+5V). Se Vss3 Ground for digital components. [—-[ =F Vss2__ [PLL ground Sa Vpb2_ [PLL power supply (+5V). Se CKIN Clock input. After applying a capacitor for DC cut, input a color-burst-synchronized fsc/4fsc clock signal to this pin. ® r>° 20kQ. ‘| Connect a VCO filter to this pin. ee 4 2001-06-19

PIN FUNCTION 1/0| INTERFACE CIRCUIT NAME 1/2Vpp | Bias for line memory. This pin requires 2.5V external bias. 2000. ie BIAS3 Bias for DAC. This defaults internally to 3.5V, so this pin should normally be connected to ground through a 0.01F capacitor. 3.5V 5 : COUT Chrominance signal output. : BIAS2 Bias for DAC. This defaults internally to 1.6V, so this pin should normally be connected to ground through a oO 0.01F capacitor. 1.6V, 5 YOUT Luminance signal output. VREF1 DAC bias lower-limit reference voltage for. This pin requires 3.0V external bias. @ : 2002. at Vppa [DAC power supply (+5V). Se [28-[vssa [DAC ground. Se 5 2001-06-19

FUNCTION BLOCK DESCRIPTIONS 1. Input clamp (CLAMP) This block performs sync tip clamping of the composite video signal. It provides a feedback signal for clamping A/D-converted minimum data at Y/C separation to the internal DC bias level. 2. A/D converter (ADC) This block comprises a high-speed series-parallel 8-bit A/D converter that accepts an input video signal of 1.5Vp-p (from sync level to 100% white level). 3. Line memory This block consists of DRAM resident line memory for 1H delay. There are four pairs. The line memories are combined to produce a 3-line composite video signal for each TV system type. 1H delay of the line memory [Detay loca] 970] as] 97 | 909 | — | 4. Band-pass filter (BPF) In this block, with fsc as the center frequency of the BPF, the chrominance signal is extracted from the line-memory-delayed composite video signal. The same logic is used for NTSC, PAL, M-PAL and N-PAL input signals, but the characteristics differ since each TV system uses a different fsc and system clock. Since the BPF for the chrominance signal output can be controlled (ON or OFF), the chrominance output can therefore be switched between a narrow band width and a wide band width. This can be controlled by the I?C bus only in I?C bus control mode. In pin control mode, the chrominance output is set to a fixed wide band width. Separate BPF logic is used for the 4.43NTSC system type. 4.43NTSC MODE 1 BPF CHARACTERISTICS 10 C OUTPUT CHARACTERISTICS. ELT LL TT] a a g ped aoe Pe ee > a CETL EN TT eg ee ee & -20) Ny é VP TTT al Nf NA 3 ; Teena = aw PETTITT TTT > ot l 8 a0 8 olf Mi | | TV A I 3 3 i e ORTEEL LL wegen > of) yt | ttt TA - nae “IE ELLE TTT | se | 3 LL TTT mre FY cw Eh 1 5 7 1S 1 0 2 4 6 8 FREQUENCY (Xfsc) FREQUENCY (MHz) 6 2001-06-19

1. Dynamic comb filter (DCF) This block comprises a band-pass filter that extracts the vertical component of the chrominance signal. Using Toshiba original logic, a correlation of the three lines is sought for. The absence of correlation is taken as an indication of a luminance signal, at which time chrominance signal output is suppressed. 6. Vertical edge enhancement circuit (VENH) This block enhances the uncorrelated components among the three lines of the luminance signal following coring. The luminance signal, obtained by subtracting the chrominance signal from the composite video signal, is added to the vertical edge enhancement component and output through the D/A converter. However, this output signal is limited to the pedestal level (fixed internally) by the pedestal clipping circuit (except for the sync tip level). Eight levels of enhancement (0dB to 1.94dB) can be selected by I?C bus control and four levels of enhancement (0dB to 1.49dB) can be selected by pin control. This block can be used with any of the TV system types except SECAM. (i) Input signal with edge component White level! — $A J LL (ii) Output signal White level! — $A A i ee Enhance level = 20fog -2*®- (4a) 7 2001-06-19

Vertical edge enhancement characteristic aS

40 OoN

20 Z Meads “Seng

10 wo ttt, Lupton ~ bo 5 10 eee TS = aD -20 Tee Y ~30 NG pH \\ A -40 vy -300 -100 100 300 a Vertical edge enhancement characteristic (Zoom) The relation between a and b. a: The difference of the luminance level in part of the edge. 10 b: The component of vertical edge enhancement which is add 8 to the luminance signal.

6 Both are expressed by digital value

4 A] Wowever, this graph only shows adjustable enhance value of the

wee TE] device pin) b 0 pee = — (A) Enhance Value : 1.49dB 2 — = (0) Enhance value : 1.4948 6 sesees (8) 1.0248 sees (Q 0.5308 -10 ~30 -10 10 30 A,B,C: Coring=OFF D, E, F : Coring=ON a 8 2001-06-19

1. 1-line dot interference correction Previously, a 1-line-only chrominance signal was processed as a luminance signal resulting in dot crawl. This circuit prevents this problem by extracting the 1-line dot component and adding it to the DCF output. This function is used with the NTSC system only, and can be set ON or OFF under PC bus control. Under pin control, it is always ON. (i) Input signal (ii) 1-line circuit output : OFF Color dot noise poy” Chroma component is decreased vour cour (iii) 1-line circuit output : ON 8. PLL (4x clock signal multiplier) This block supplies a 4fsc (PLL 4x multiplied) signal for use as system clock. An fsc or 4fsc input clock is selectable under I?C bus control. Under pin control, the external clock signal is used, bypassing the PLL circuit. 9. Clock and memory timing generator (RTIM) This block supplies a buffered system clock signal to the other circuit blocks, and also generates a timing signal for the memory blocks. 10. D/A converter (DAC) This block comprises a high-speed 8bit D/A converter. It provides Y output at approximately 2.0Vp-p and burst-level C output at approximately 572mVp-p. 9 2001-06-19

@ Signal processing 1-LINE DOT TV SYSTEM METHOD OF Y/C SEPARATION VENH CIRCUIT | Coprection CIRCUIT NTSC 3-line (OH, 1H, 2H) O(tiW) [ O- [PAL __[3:line (OH, 2H, 4H) CGH [| — ‘4 N-PAL _[3-line (OH, 2H, 4H) Oth | M-PAL _[3-line (OH, 2H, 4H) Ott [| 4.43NTSC [Chroma BPF OW [| = | SECAM__|Bypass (Input>ADC>DAC>Output) PT @ Signal flow chart 1. NTSC system OH Vertical Ed Dar | Dynamic tine dot ar | BPE I] comb sitter |] Sozrection _=7 | @) ¢ output A 2. PAL, N-PAL, M-PAL systems [2n_| Vertical Ed: Ler] Dynamic Ltt com rite ana) ® couout 10 2001-06-19

1. 4.43NTSC system OH Lit] Vertical €¢ 4. SECAM FUNCTION CONTROL There are two ways to control TC9090AN and TC9090AF functions : through the I?C bus or through the device pins. The method used is selected with function control selector switch P/S (pin 7). @ Function table CONTROL TV System Selector tvsw_ [ O | O NTSC, PAL, N-PAL, M-PAL 4.43NTSC, SECAM IC bus control : 8 steps (OdB~1.94dB) VENH Level Selector VENH fo fo] Pin control : 4 steps (0dB~1.49dB) Color Killer Switch KILLER | O | O [Color, B/W Coring Switch | coRING | O | ON |Coring circuit on, off tine Dot Correction LINE 1-line dot correction circuit on, off Switch Chroma Band-Width CBPF Wide | Wide band width, narrow band width Selector PLL Selector PLLSEL | O | © [fsc input, 4fsc input (PLL off) For KILLER and PLLSEL, pin control is also possible even in I?C bus control. When you set to “1” or “H” in either control, however, these settings have priority. Example : PC bus: 1 Pin: L_ — PC bus : 1 has priority. PC bus: 0 Pin: H — Pin : H has priority. 11 2001-06-19

PC BUS CONTROLLED FORMAT SUMMARY Bus controlled format of TC9090AN and TC9090AF are based on IC bus control format of Philips. Data transfer format Cae [we Teme] { rer { { %* 5 : Start Condition MSB MsB MsB P : Stop Condition A: Acknowledge (1) Start and stop condition (2) Bit transfer Start condition ‘Stop condition vy . { : : SDA cannot change SDA can change (3) Acknowledge (4) Slave address soa ™ High impedance —_ Litotitiptoftotyi} o | SDA High impedance rom \\ / slave save LS. Purchase of TOSHIBA I?C components conveys a license under the Philips I?C Patent Rights to use these components in an I?C system, provided that the system conforms to the I?C Standard Specification as defined by Philips. 12 2001-06-19

PC BUS CONTROL DATA REGISTERS Value in tables are default initialization values. DATA1 A TVsW1 Tvsw2 TVvsw3 VENHO VENH1 VENH2 CBPF KILLER 0 0 0 0 0 0 0 0 TVSW1~3 : Selects the TV system. 000 = TEST (not used) 001 =M-PAL 010 =N-PAL 011 =PAL 100 = 4.43NTSC 101 =SECAM 110 = 3.58NTSC VENHO~2 : Sets level of vertical edge enhancement. 000 = 0dB 001 =0.27dB 010 =0.53dB 011 =0.78dB 100 = 1.02dB 101 =1.26dB 110 = 1.49dB 111=1.94dB CBPF : Selects the chroma output band width by switching on or off the BPF that follows DCF. 0=Wide band width 1=Narrow band width KILLER : Switches color killer circuit. 0=Color mode (color killer circuit OFF) 1=B/W mode (color killer circuit ON) 73 2001-06-19

pwse | | ET te 1LINEDOT | CORING PLLSEL 0 0 0 1LINEDOT : Switches 1-line dot correction circuit on or off. O=ON 1=OFF CORING : Switches coring circuit on or off. O=ON 1=OFF PLLSEL : Selects input clock frequency. O=fsc input, PLL circuit is used 1=4fsc input, PLL circuit is bypassed PIN CONTROL PIN7 PINS PINS PIN 10 PIN 11 PIN 12 | PIN 13 | PIN 14 ACTION P/S SDA SCL RESET TEST1 TEST2 | KILLER | PLLSEL TVSW1 ‘VSW2) | (TVSW3) | (VENHO) | (VENH1 prs [rccontrol Tt PT = [| = [| — [| = | =~ [=f = | A [rest = = = TH [MPpaL PP eT eK = | ~~ TT = [NpaL PP RH tsw frac = fT = TK fT jaasntsc TK OT KP ee = P= TK | = [secam TT KP = fT = TK TH [ssentsc | KT KT KT ce | = | = TP KH TH [VENH circuit OFF | OH fT = | — [| — fot tT te [= [=| veny VENH level=o.53d8 | H | — [| — | — [ t [ok [- | =| [VENH level=1.02d8 [ H [| — | — [ — | # [ tf —-f— | lafscinput | — 14 2001-06-19

RATINGS AND CHARACTERISTICS The following specifications were obtained in part from the test circuit shown on page 19. MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING UNIT Power Supply Voltage Vss~Vss + 6.0 Input Voltage -0.3~Vpp +0.3 ssipation TCS0308N [900 Power Ossnaion Fresepoar|° (ote | —gp—| Storage Temperature -55~125 (Note) Ta=75°C RECOMMENDED OPERATING CONDITIONS CHARACTERISTIC SYMBOL TEST CONDITION ran. | ve. [as UNIT Power Supply Vattage | Vpp | ~*~ | SOO] SB] input Voltage [Win [=

ELECTRICAL CHARACTERISTICS

DC CHARACTERISTICS (Ta =25°C, Vpp = 5V) TEST CHARACTERISTIC SYMBOL | CIR- TEST CONDITION TYP. | MAX. | UNIT CUIT Power Supply Vartage | Vpp | 1 | Supply Current | 'oo | | |_ 60 | 80 | 100 | ma | Output Voltage Level OUT | 29] 3.0 | 3a | a0, a2 | VREFL [a2 [15 | 18 | vaEFH| — |ctock= [32] 35] 38 | ADIN 4.43361875MHz (PAL) | 1:3 | 1.6 | 19 | BIASI [os 7317] Pin Voltage Level v 9 VREL1 = 3.0V [ 10] 16 [22 | BIAS3 1/2Vpp =2.5V | 25] 35[ 45 | VFL [os | 18] 25 | CKIN ViN=No input | 18 | 24] 3.0 | spout Vonage [High Level [Vin [7 | [«[-T-T,y put Voltage Tow Level | vu | 1 | a ADIN Pin Input Capacitance | cin | 1 | [= | 50] — |r| Pull-Down Resistance [Rep [1 | [25 [50 | 100 | Ka 15 2001-06-19

Y output (Ta=25°C, Vpp =5V, Vrer1 =3.0V, Input Clock : fsc, 0.4Vp-p, $1 =2) TEST, CHARACTERISTIC SYMBOL TEST CONDITION mn] re, |e UNIT CUIT, Input Level [Vn ftp = = TST 16 [ Vp | Response [f47f [=35[-25[-16 | 3.58NTSC Lame a Response fa7f1 VIN=15Vpp Vde=2.5V 0 [=3.5 [-2.5 |= 166 | PAL Comb rec [econ] |rewwerwomme: [| ef —| ain (in) — Gain A wpa, [Response [fa7f1 [=3.5 [=25 | -16 | ° Comb cee 2/43] YCOMnp Comb characteristics : | | 4] — | Characteristics Gain (comb top) Frequency 2/71 -Gain (comb bottom) | =2.5 | -2.0 | -0.9 | M-PAL Response 4/41 | =3.5 | -2.5 | -1.6 | : Comb aaantsc|freaueny [15/71 | =3.0 [-2.5 [-19 | meee | | =| Linearity VIN =5-step signal % cle | fe aT ell $2=2, $3=2, $5=2 Vin=fH 1.5Vp-p Vde=2.5V Output Impedance Zo= V1-V2 x 300 a V1: $4=1, V2: S4=2 G20 -06- TT

TEST| CHARACTERISTIC SYMBOL | ciR- TEST CONDITION TYP. | MAX. | UNIT CuIT| Clock Leak $2=2, $3=2, S4=1, S5=1 (4fsc Components) Vin =No input | — | 50] 20 |mVrms Fundamental Clock Leak lsc $2=2, $3=2, S4=1, S5=1 mv, (fsc Components) Vin =No input rms| (Note) f1 =f, f2=fsc, f3 (NTSC) =fsc+1/2fH, £3 (PAL) =fsc + 1/4fH + 25Hz, f4 =3/4fsc 3587412.13 | 4437550.00 | 3585987.50 | 357954506 | — | 4772726.67 | 591149167 | 4776075.00 | 476748199 | — | Unit : Hz C output (Ta =25°C, Vpp =5V, VReF1 =3.0V, Input Clock : fsc, 0.4Vp-p, $1 = 1) TEST| CHARACTERISTIC SYMBOL | ciR- TEST CONDITION Typ. | MAX. | UNIT CUIT| CC aE Character- VIN =1.5Vp-p Vde=2.5V 3.58NTSC | istics BWCNn (fsc - 503496Hz) - (sc) | -1[-05] — | Comb Characteristics | CCOMn ViN=430MVp-p Vde=2.5V 30} 35 | - | BPF Characteristics | BWp VIN = 1.5Vp-p Vdc =2.5V -0.2 PAL (fsc — 500000Hz) - (fsc) Comb Characteristics | CCOMp VIN =430mVp-p Vde=2.5V 30 35 | - | 17 2001-06-19

TEST) CHARACTERISTIC SYMBOL | CIR- TEST CONDITION TYP. | MAX. | UNIT CUIT, BPF Characteristics BWnp VIN =1.5Vp-p, Vde =2.5V N-PAL (fsc - 500000Hz) - (fsc) Comb Characteristics | CCOMnp VIN =430MVp.p, Vdc =2.5V | 30| 35] — | BPF Characteristics BWmp VIN =1.5Vp-p, Vde =2.5V M-PAL 1 | (fsc - 503496Hz) — (fsc) Comb Characteristics | CCOMmp VIN=430mVp.p, Vdc =2.5V | 20] 35] — | BWN4n VIN=1-5Vp.-p, Vde=2.5V -19]-1.5 4.43NTSC | BPF Characteristics (fsc - F) - (fs) BWWan BWNgn : F=500kHz -20|} -16] -13 BWWapn : F=1.5MHz Differential Gain VIN =5-step signal % Y = 140IRE C=40IRE Differential Phase DG= (Comax - Comin) /Comax $2=2, $3=2, $5=2 VIN=fH 1.5Vp.p, Vde=2.5V Output Impedance 2o=VI=V2_ 399 a Clock Leak $2=2, S3=2, S4=1, S5=1 Lck ‘ ‘ ‘ 20 Fundamental Clock Leak lsc $2=2, $3=2, S4=1, $5=1 03 mv, (fsc Components) Vin =No input : rms PLL CIRCUIT CHARACTERISTICS TEST) CHARACTERISTIC SYMBOL | CIR- TEST CONDITION TYP. | MAX. | UNIT CUIT, Pullin Frequency Range [fk | 1 | — | 387 | — | aaa [we | Input Amplitude (fsc Components) Vek 03 Vp-p 18 2001-06-19

sa] |e 5) lge| | € &| je< & Py wh” $3 6 PN a6 2 : Ux +a i > : ade Pode : joFsdze i re : S > Leon goss , cx +, - UD0E o_ AMY e aL * Pavor > 3 70 z x S pase ¢ ie cr at let bed ASL 4, 8 é & A947] Ag 4701 3 g]" jayor 47/01 8% 13 8 4IV0606)1 ‘NV060691L - . ASL ° . 0 a Ee avout | | 3 aT] gs < 5 28 sO ne 2 be g of a ¢ s a 220 Mair _* 8 19 2001-06-19

+5V IN fo) GQ) vrcen Yssa28—pz Sudizls = Vss1_ VoDa 0.47 uF /50V Salt ree pe o 100.4H VIDEO, [Pe | +p ~ol+ 12k: o-{ ur vy 100 2H @voo1 Yours) © Your 0.01pF 0.01 pF eS ph 0.01 F CJ sias1 Cour [23> © Cour SDA O @) soa 1/2Vpp 2) scl © Oa vei 20) 100 /16V _ (Tvsw2) 82002 0.01 uF a= reser can = 0 cock m

2 GJ rest: Yoo2 (9—4r v

= osye oF: @rest2 Vss2 vss3 [1 > Analog GND @ KILLER $83 { Su, S> 1 ouqs Ee £ pigital cno rt PLLSEL_VDD3 PT 700.4 Y PLLGND (Note) About PCB design : To reduce input/output signal noise, isolate the analog, digital and PLL circuits from one another. 20 2001-06-19

SDIP28-P-400-1.78 Unit : mm 28 15 T fiririririririri rm ciriririm od ) i o =| 8 | 3 a hj 1 14 26.1MAX 25.640.2 PO gg AAAS & = 2 | | = g a 3 3 6 Weight : 1.7g (Typ.) 21 2001-06-19

SOP28-P-450-1.27 Unit : mm 28 15 ; HEHEERAEAE Aaa J ! al 3 al = ) 3] 3 Ee | in | POPP C TTT “I u 14 0.995TYP 0.4320.1 10.250) 19.0MAX 18.5#0.2 lJ $ 3 8} | Tannen Fe El 3 Lega : L rei] # a 1,010.2 Weight : 0.8g (Typ.) 22 2001-06-19

RESTRICTIONS ON PRODUCT USE 00070768 @ TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. @ The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. @ The products described in this document are subject to the foreign exchange and foreign trade laws. @ The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 23 2001-06-19