TC9028AF

TC9028AP TOSHIBA | Alldatasheet

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TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC9028AP, TC9IO28AF INFRARED REMOTE CONTROL TRANSMITTING CMOS LSI WITH MICROCONTROLLING TC9028AP, TC9028AF is CMOS LSI for Infrared Remote TC9028AP Control Transmitting suitable for Remote Controlling TV, VCR, Video Disk, CD-Player etc. a Using a 4bit Microcontroller, various transmittings are a _— _ al structured by a programming. he an Ar 1 iv

FEATURES

DIP20-P-300-2.54A @ Low voltage operation : 2.0~4.0V 0-P-300-2.5 TC9028AF @ Low power dissipation : S1A (at Hold Function) @ Program memory (ROM) capacity : 768 x 8bit @ Data memory (RAM) capacity : 16x 4bit f yy © Instruction : 4akinds NEA FES { s @ Timer /Counter > 10~15bit @ 1/0 port (15pins) SOP20-P-300-1.27 1/0 : 2ports 8pins Weight : i DIP20-P-300-2.54A : 1.4g (Typ.) Input + Iport 4pins S0P20-P-300-1.27 : 0.489 (Typ.) Output : 1port 3pins (Including High Current Output) @ Subcarrier frequency : fosc/ 12, fosc/8 PIN CONNECTION (TOP VIEW) fosc/24, fosc/ 16 (Option) © Oscillating frequency : 400~800kHz vss Ho 2° Yoo Xr 2 19 fl ps3 @ Instruction execution time : 11s (at 455kHz) x 18 ps2 © Package : DIP20 [TC9028AP] ae, be vpest Poo WS 16 fh P23 SOP20 [TC9028AF] Pore 1 fh p22 (Note) This device is Vulnerable to surge voltages. P02 7 149 p21 Take it into account when using this device in your system. ros Bs 13 fl P20 Piolo 12 P13 pit 10 11 PP pt2 9g0s0geBA2 malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In ceveloping your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook 1998-07-08 1/20

POWER {yop SUPPLY “Wss Ce [on DATA [| MEMORY ‘y: way PROGRAM STACK | ett KL ei | \\ ae / zs GENERATOR RESONATOR us qt connecting £174 HOLD TIMER CARRIER fi | ot | it ath H H 1 ocr PORT Le JLe dhe] P53 P52 PS Pos P13 P23 5 ‘ 5 Poo P10 P20 eo, OUTPUT PORT INPUT PORT 170 PORT PIN FUNCTION |} 1 | Mss | Power Supply Vpp = 2.0~4.0V, 3V (Typ.) | 2 | x | Output for Osc. | Resonator connecting pins. Connects ceramic resonator with | 3 | Xz [Input for Osc. | capacitor. Built-in feedback resistance. | 4 | RST [Reset Input RST for going reset. Be held to “L” (23 instruction cycles) | 5~8 |P00~P03|Input Port PO | 4bit input port. Built-in pulldown resistance. P10~P13 |1/O Port P1 Abit 1/O ports with latch. Input/output mode can be specified by [MOV A, P] instruction. 13~16 | P20~P23 |1/O Port P2 Built-in pulldown resistance. Output Port P51 |Pch open drain output port. | 18 | P52 | Output Port P52 | High current output port. For driving indication LED. [19 | P53 [Output Port P53 [High current output port. For driving infrared LED. 980508EBA2" 3 The products described in this document are subject to foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property Or other rights Of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others @ The information contained herein is subject to change without notice. 1998-07-08 2/20

1. Configuration (1) Program counter (PC) (2) | Memory bank register (MBR) (3) Stack register (STACK) (4) Data counter (DC) (5) | Program memory (ROM) (6) —_L register (LR) (7) Data memory (RAM) (8) | Arithmetic and Logic Unit (ALU), Accumulator (9) Flags (10) Clock generator, Timing generator (11) 1/0 ports a. Port register (PR) b. Command register (CR) (12) Timer counter a. Timer register (TR) b. Timer counter output c. Watch dog timer output (13) Hold mode control circuit (14) Reset circuit Following is a description of the hardware configuration and operation of the components listed above. 2. Internal CPU functions

2.1 Program counter (PC)

The program counter is a 10bit binary counter which holds the program memory address of the next instruction to be executed. The program counter is normally incremented for each instruction fetch. When branch instructions and subroutine instructions are executed, the values specified in Table 2.1 are set. The program counter is initialized to 0 at reset. 1998-07-08 3/20

Address within page Address Page [-00 H 000 H a 001 3E ose 3F 03F 00 040 0 oat 3E ore 3F o7F 00 080 2| o1 081 | 1 i al! ! 3E 2BE 3F 2BF 00 2c0 01 2c1 8] 1 i 3 2Fe 3F 2FF Figure 2.1 Program memory configuration Table 2.1 Program counter values depending on conditions PROGRAM COUNTER (PC) NS RON OR CONDITION PAGE ASSIGNMENT | ADDRESS SFECIFICATION SF=1 (when branch Memory bank Value directly specified by BSS LD MBR, #k condition is satisfied) register contents instruction SF=0 (when branch

2 Lower 6 bits of No ch Value directly specified by

3 sper [address# 111111 9 change _|instruction x BSS a ~ Lower 6 bits of 1 Value directly specified by © address = 111111 * instruction

2 Value directly speci-

es Ce Value restored from stack Instructions other +1 than above [Reset 1998-07-08 4/20

2.2. Memory bank register (MBR) The memory bank register is a 4bit write-only register. It holds the page specification (upper 4 bits of the program counter) when a branch is made anywhere in program memory.

2.3 Stack register (STACK)

The stack is a 10bit register. When the [CALLS a] instruction is executed, the stack register saves the contents of the program counter (return address) before the program jumps to the processing routine. Only one level of subroutines can be used. When there are two calls, the first return address is overwritten when the second return address is saved to the stack register. When the program returns from the processing routine, execution of the [RET] instruction restores the contents of the stack register to the program counter.

2.4 Data counter (DC)

When fixed data stored in the data table in program memory (ROM) are read, the data counter (DC) are used to specify 4 bits of the address. In addition to transferring data to the accumulator, the data counter is also equipped with increment and decrement functions and can therefore be used as a general-purpose register. Fixed data stored in the data table can be read using the table look-up instruction. When the table look-up instruction is executed, the upper 6 bits of the ROM address are "101111" and the lower 4 bits are the contents of the data counter (DC). These bits specify the last 16 bytes (addresses 2FO~2FFH) of program memory for fixed data.

2.5 Program memory (ROM)

Program memory stores program and fixed data. The next instruction to be executed is read from the address indicated by the program counter. Physical program memory doesn’t exist in addresses 300~3FFH. When this area is read on the program, 7FH ( [NOP] instruction) is read. Address 768 x 8bit 000 H CT oe Entry address for subroutine OIE call by [CALLS a] instruction 2F0 {LDL A, @DC) i [LDH A, @Dc} L Data conversion table for oFF instructions. 1 7FH ( [NOP] instruction) 1 Figure 2.2 Program memory map 1998-07-08 5/20

2.6L register (LR) The L register is a 4bit register. It is used as a data memory (RAM) address pointer. It can also be used as a general-purpose register. 2.7. Data memory (RAM) Data memory stores data to be processed by the user. There are two data memory addressing modes. One is register indirect addressing mode, where the L register specifies an address. The other is direct addressing mode, where the lower 3 bits of the instruction field directly specify an address. Figure 2.3 shows the L register and data memory configuration. The data memory contents are undefined at reset. Make initial settings using the initialization routine. L register (A) 302 1 Data memory address specification WYWW$wwwWCGGG LTT TT TTT aa). (Note) Y : Area directly addressable Figure 2.3 L register and data memory configuration 2.8 ALU, Accumulator i.

2.8.1 ALU \\ x /

The ALU is a circuit which performs various c operations on 4bit binary data. z [s* | The ALU performs operations according to ae . instructions and outputs results (4bit), carry data (Note) Cin indicates carry input . specified by instruction. (C) and zero detection data (2). 2.8.2 Accumulator (ACC) Figure 2.4 ALU and flags The accumulator is a 4bit register. It stores source data and results. MsB LsB 3 2 1 ° Figure 2.5 Accumulator 1998-07-08 6/20

2.9 Flags (FLAG)

There are two types of flags: carry flag (CF) and status flag (SF). These are set and cleared according to conditions specified by instructions. The status flag is initialized to 1 at reset.

2.10 Clock generator, Timing generator

Figure 2.6 shows the clock generator and timing generator configuration. xt @) | e Clock generator Timing generator xt ® wrth HOLD control system clock Figure 2.6 Clock generator and timing generator 2.10.1. Clock generator The clock generator is a circuit which generates the fundamental clock pulse (CP) as the basis for the system clock supplied to the CPU. The fundamental clock is easily established by connecting the oscillator to the XT and XT pins. A clock can also be input from an external oscillator. Clock input to the XT pin is used as the fundamental clock. The clock generator stops oscillation during hold mode. xT xT aT xT ; (open) ° co l Gi a oh (@) Ceramic oscillator (b) External oscillator Figure 2.7 Typical oscillator connections

2.10.2 Timing generator

The timing generator is a circuit which uses the fundamental clock to generate various system clocks for the CPU and peripheral hardware. 1998-07-08 7/20

2.10.3 Instruction cycle

Instructions and internal hardware operations are executed in sync with the fundamental clock. The minimum unit of instruction execution is called the instruction cycle. TC9028AP and TC9028AF has 1 and 2-cycle instructions. An instruction cycle consists of 5 states (SO-S4). Each state consists of 1 fundamental clock. Therefore, the instruction cycle time is 5/fc[s]. 3. Peripheral hardware functions

3.1 Ports

The following functions are executed using |/O instructions (4 types): key scan, send signal output, send display output, internal circuit control. This system features the 2 types of ports listed below. Addresses (00-05H) are allocated to these ports: ® 1/0 ports : key scan, send signal output, send display output @ Command register : internal circuit control Ports are selected by specifying port addresses with I/O instructions. The port register controls input and output of programmable |/O ports.

3.1.1 Port register (PR)

The port register is a 4bit write-only register. It is used for selecting input or output mode for programmable |/O ports. Since an option is used to select input or output mode during hold, the port register cannot select the mode. Port register (PR) 3 2 1 0 (Initial value: 0000) [ — [as JptHs] pis] Selects |/O mode for ports P2. L_{ 0 : Input mode for P23~P20 1: Output mode for P23~P20 Selects |/O mode for port P1. (upper 2 bits) 0 : Input mode for P13 and P12 1: Output mode for P13 and P12 Selects 1/O mode for port P1 (lower 2 bits). 0 : Input mode for P11 and P10 1: Output mode for P11 and P10 Figure 3.1 Programmable |/O port control using port register 1998-07-08 8/20

3.1.2 1/O ports TC9028AP and TC9028AF has 4 1/0 ports with 15 pins. (1) Port PO: 4bit input (2) Ports P1, P2 : 4bit programmable input/output (3) Port P5: 3bit output (P52 and P53 are for large current output) (1) Port PO (PO3~P00) Port PO is a 4bit input port. All its pins are equipped with hold mode cancellation function. (2) Ports P1 (P13~P10), P2 (P23~P20) Ports P1, P2 are 4bit programmable |/O ports with latches. Input or output can be selected by program. (8 types) Latches are initialized to 1 at reset. Pins which can be switched using an option to input mode during hold mode are equipped with hold mode cancellation functions. Port PO (port address IP00) 3 2 1 0 [pos [poz | por | poo _| HCANO3 | HCANO2 | HCANO1 | HCANOO Port P1 (port address OP01/IP01) 3 2 1 0 (HCANTS) THCANTO) Port P2 (port address OP02/IP02) 3 2 1 0 (HCAN23) | (HCAN22) | (HCAN21) | (HCAN20) Figure 3.2 Ports PO, P1 and P2 (3) PS (P53~P51) port Port P5 is a 3bit output port with a latch. P51 is for P-ch open-drain output. An option allows it to be used for push/pull output. The latch is initialized to 0 at reset. P52 is for large current output for driving the send display LED. The output latch is initialized to 1 at reset. 1998-07-08 9/20

P53 is for large current output for driving the infrared LED. Resetting the output latch to 1 outputs fOSC/12 (duty 1/3) or fOSC/8 (duty 1/2) sub-carrier frequency for modulation. An option allows selection of fOSC/24 (duty 1/3) or fOSC/16 (duty 1/2) sub-carrier frequency. Sub-carrier frequency (duty) is selected by the command register. The latch is initialized to 0 at reset. The LSB (P50) of the port P5 is used for selecting the sub-carrier frequency (duty) output from P53 using the write-only command register. The latch is initialized to 0 at reset. Although port P5 is an output port, when an input instruction is executed, P5 can read timer/counter output (IT3~ITO). Port P5, Command Register (port address OPO5) and, Timer /Counter Output (port address IP05) 3 2 1 0) [ps3 J p52_ 7 p51_ [CR | (initial value: 0100) Sub-carrier frequency 0 : fosc/ 12 (duty 1/3) 1: fosc/8 (duty 1/2) Option 0: fosc/24 (duty 1/3) 1: fose/ 16 (duty 1/2) Figure 3.3 Port P5

3.2 Timer/ counter

The timer/counter is a 17 step binary counter used to divide the fundamental clock. It outputs a pulse with a cycle selected from steps 10 through 15. The timer/counter is a 17 step binary counter used to divide the fundamental clock. It outputs a pulse with a cycle selected from steps 10 through 15. The uses of the timer/counter are listed below. The timer/counter is cleared to 0 at reset, when a timer reset instruction (TMRST) is executed, and when hold mode is cancelled. ® Timer generating fc /2'°~f¢/2'> [Hz] pulses @ Watchdog timer @ Warming-up timer when hold mode is cancelled 1998-07-08 10/20

3.2.1 Timer register (TR)

The timer register is a 4bit write-only register. It selects the mode when the timer status is read. The timer register is initialized to 0 at reset. Timer register (TR) 3 2 1 0 IBNS TIBS (Initial value: 0000) Selects number of bits to be read as timer status. 0: Read 1bit data from P53 (IT3) At this time, the P52~P50 data (IT2~ITO) are 0. 1: Read 4bit data from P53~P50 (IT3~ITO). The cycle for each bit is as follows. (Fixed) P53 : 215/f¢ P52: 2°4/fe P51: 2/f¢ P50: 2"2/f¢ Selects timer cycle /duty Valid only when IBNS is 0 000 : Cycle 2'°/f, duty 50% 001 : Cycle 2''/f,, duty 50% 010 : Cycle 2''/f¢, duty 75% 011 : Cycle 2'?/f¢, duty 50% 100 : Cycle 2"2/fc, duty 75% 101 : Cycle 2'3/f¢, duty 50% 110 : Cycle 2'3/fc, duty 75% 111: Cycle 2'4/f., duty 50% Figure 3.4 Timer/counter output mode control using timer register 1998-07-08 11/20

3.2.2 Timer counter output (IT3~ITO)

The timer counter is cleared to 0 at reset. It is incremented, from 0, each time the fundamental clock is input. The timer counter output transfers the inverted value of the timer counter to the accumulator or data memory using port P5 input instructions [IN %IPO5, A] and [IN %IP05, @LR]. Thus, 1 is read at reset. (Decrement) Timer counter Frequency fe Wt Warming-up output Watchdog when hold mode is cancelled = [ [ tH timer output V|U}U &lelelaelelalele BSR R/RP Rl RIS Port PS input instruction ul ou ub ud d Port PS input (Walid when IBNS =0) SISSIES le (Wolld when IBNS= 1) a U TiBs 73 IT3~1T0 (TR2~TRO) Timer counter output Figure 3.5 Timer counter configuration

3.2.3 Watchdog timer output

The watchdog timer output becomes active 2'°/fc(s) after the timer is reset. If the timer is not reset again before timer reset, TC9028AP and TC9028AF regards this as a CPU runaway and resets the CPU. 4. Low power consumption operation TC9028AP and TC9028AF features a hold mode for low power consumption operation.

4.1 Hold mode

The hold function stops system operation and holds the internal states in effect immediately before stopping. The hold function is controlled by the port hold mode cancellation function and by the hold instruction [HOLD]. The hold cancel function is valid with pins POO~P03, and with pins P10~P13, P20~P23 (HCAN pins) which are switched using and option to input mode during hold mode. 4998-07-08 12/20

4.141 Hold mode

Hold mode is activated by executing the hold instruction [HOLD]. Hold mode continues as long as the HCAN pins are at low level. The following states are held during hold mode. ® Oscillation stops and all internal operations stop. @ The timer counter is cleared to 0. @ Data memory, registers, and port latches hold the states immediately before entering hold mode. (Note that the status flag is set to 1.) @® The program counter holds the 2 addresses after the hold instruction. (After hold mode is cancelled, execution resumes with the instruction following the hold instruction.)

4.1.2 Hold mode cancellation

Hold mode is cancelled and normal operation resumes when high level is input to the HCAN pins during hold mode. Hold mode is cancelled in the following sequence. ® Oscillation begins. @® Warming-up for the time required to stabilize oscillation. Internal operation remains stopped during warming-up. The warming-up time is 2''/f¢(5). @ After the warming-up time has elapsed, normal operation resumes from the instruction following the hold instruction. (Note) The fundamental clock is divided by the interval timer. If the oscillation frequency fluctuates after hold mode is cancelled, the warming-up time is not exactly the same as the value given above. Thus, the warming-up time has allowance. Hold mode is also cancelled by setting the RST pin to low level. In this case, the reset operation is performed immediately. Since normal operation begins at the same time the reset operation is cancelled, the RST pin must be kept at the low level for the warming-up time until oscillation becomes stable. If input to the HCAN pin is at high level, executing the hold instruction does not enter hold mode but instead moves immediately to the cancellation sequence (warming-up). The warming-up time in this case is an undefined value between 0~2"'/fc(s). Therefore, when the hold instruction is executed, input to the HCAN pin must be set to low level. 4998-07-08 13/20

1. Reset If the RST pin remains at low level for more than a minimum of 3 instruction cycles (15 fundamental clocks) when the power supply voltage is within the operating voltage range and oscillation is stable, the system is reset and the internal states are initialized. When the RST pin is set to high level, the reset operation is cancelled and execution of the program at address 000H begins. Table 5.1 Initialization of internal states by reset see descrint ee description [status Flag (SA) Tt | Output Latches (1/0 ports) |e 7G Circuits Instruction list | rweron | wwone immer femora) ON rte FUNCTION MNEMONIC OPERATION CYCLES Lo A, QLR 0000 0110 06 Acce-RAM (LR) 1 Lo Ax 1001 Oxxx 90+x Acce-RAM ( x) 2 LoL =A, @pc_—f 01100111 67 Acce-ROM ( DC) L 2 LDH =A, @DC 0110 0110 66 Acce-ROM ( DC) H 2 IST A, @LR 0111 0110 76 RAM (LR) Acc 1 ST #k, @LR- | 0011 kkkk 3k RAM (LR) <-k 1 Ist Ax 1001 1xxx 98 +x RAM (x) <Acc 2 Transfer Lo A, #k 0001 kkkk tk Acce-k 1 Lo L, #k 0010 kkkk 2k LR 1 Mov LA 0000 1111 oF Acce-LR 1 Mov AL 0000 1100 oc LRRAcc 1 Mov D,A 0000 1110 OE Acce-DC 1 Mov A,D 0000 1101 (>) DCeAce 1 Mov A,P 0111 1110 7E PReAcc 1 Mov _A,T 1000 1010 8A TReAcc 1 IN %p, A 0110 Oppp 60+p Acce-PORT ( p ) Z| 2 IN %p, @LR | 0110 ppp 68+p RAM (LR) PORT [ p) Zz 2 Input / Output ) OUT A, %p 0111 Oppp 70+p PORT ( p) Acc 1] 2 OUT @LR, %p | 0111 ppp 78+p PORT ( p) RAM (LR) 1 2 1998-07-08 14/20

FUNCTION MNEMONIC OPERATION CYCLES ADD A, @LR 0000 0011 03 AcceAcc + RAM ( LR ) —|c IADDC =A, @LR | 0000 0100 04 Acce-Acc + RAM ( LR) +CF cle ADD A, #k 0100 kkkk 4k AcceAcc +k —|¢ ADDL, #k 0101 kkkk 5k LRELR +k —|¢c . ISUBRC A, @LR 0000 0101 05 Acce-RAM ( LR) -Acc-CF cic Operation 2 (Arithmetic & Inc @LR 0000 1001 09 RAM (LR) RAM (LR) +1 —|c Logical) DEC @LR 0000 1000 08 RAM (LR) RAM (LR) -1 —|c¢ INC D 0000 1011 0B Dcepc +1 —|c Dec oD 0000 1010 ON Dcepc-1 —|c AND A, @LR 0000 0000 00 AcceAcc\\ RAM ( LR) —|Zz OR A, @LR | 0000 0001 01 AcceAccV RAM ( LR) —|z XOR__ A, @LR 0000 0010 02 Acce-Acc¥-RAM ( LR ) —|z cLR = @LR, b 1000 O1bb 84+b RAM ( LR) be-0 Bit Manipulation |SET @LR, b 1000 00bb 80+b RAM (LR) be-1 TEST @LR, b 1000 11bb 8C+b SFe-RAM (LR) b CLR OCF 1000 1011 8B CFO 2 Flag Manipulation |SET CF 1000 1001 89 CF 2 TESTP CF 0110111 7 SFR-CF 1 BSS a 11d dddd Cord if SF=1 then PCea else null, 2 Branch a=PC9.¢-d Lo MBR, #k | 1011 kkkk Bk MBRe-k 1 fave fe "form to] ae fresace [ELT GI ‘Subroutine RET 01101110 6E PCe-STACK 2 fovcewt wit in| [een FELL CPU Control ; NOP oi 1411 7F No operation [a oa Cr Control (Note 1) C : Carry from the highest digit for addition and non-borrow to the highest digit for subtraction. Z : Zero detection data are 1 when data transferred to the accumulator or RAM are 0000B. * : Value specified by operation is set. _: No flag change. (Note 2) The PC contains the address following the instruction being executed. 1998-07-08 15/20

AND | oR | XOR | ADD [ADDC|suBRC| LD DEC | INC | DEC | INC | Mov | mov | mov | mov APA) AT A) Ay AY A THON) @inta@ir| o | o farlaoloal La | | ” onal ae | 3 | * mon | «| App NK ee LDH | LOL IN %p, A AA IN %p, @LR RET @pcJ @pdc, ST TESTP Mov

7 OUT A, %p A, OUT @LR, %p

@LR set |mov] cLR ET @LR, LR @HL, MRST| TEST @LR, |e | serene | aren frvasl SS] sree | a a a a fo (Note 1) Blank code is undefined. (Note 2) [_]+-cycte instruction LJ 2-Cycle instruction 1998-07-08 16/20

MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING UNIT Power Supply Voltage = 0.3~5.0 Input Voltage Vss - 0.3~Vpp + 0.3 jours [ 20 mA | Power TC9028AP [350 we age mW Dissipation TC9028AF Operating Temperature Storage Temperature —40~125

ELECTRICAL CHARACTERISTICS

RECOMMENDED OPERATING CONDITIONS (In *marked items, Ta = -20~75°C, unless otherwise specified, Vcc = 3.0V, Ta = 25°C) TEST CHARACTERISTIC SYMBOL TEST CONDITION fn. [ve max UNIT CUIT Operation Power Supply Vakage*| Vop |— | — | 20, — | 40] Vv _| Oscillation Frequency * [Foss |= [= | #00 || a00 |e | A Vv | vm | = | Except Hysteresis Input ww | — | voo | “H" Level v - Vv ne Poses [8 | — [| Input Voltage - v Lv || Except Hysteresis Input | o| - | we “L" Level v = Vv i RST DD DC CHARACTERISTICS (Vpp =3.0V, Ta = 25°C, unless otherwise specified) TEST CHARACTERISTIC SYMBOL TEST CONDITION fn. [ve max UNIT CUIT Operation Power Supply Current | Ipp | — [fc=455kHz | — [| — | 10 | ma | Static Dissipation Current |_Igp_| — [at Hold Function [| — | — | 10] 2A | Pulldown Resistance [8p | — (Po, Pr, P2) [700 | — [400 [kn] a level Vouts=26 | -04[-14| — | Output Current VoH (P53) = 1.5V [-10[ — | — | [tevel | tor = Vor Psa)=tsv— sf} — | — | input Leak Current Ti, [= Win=Vop, Vss [exo — [10 [za | 1998-07-08 17/20

TLN11SA, scarier ¢ ® OO OOO @ @ @ @ Yop P53 P52 P5128 P22 P21 P20 IS Pla TC9028AP, TC9028AF vss %] Xr FST Poo pot p02 03 PIO Prt ORORORO) bebbe r O-O-O-O-O-O-O-O cat : EbEbSSESS TT LTT Sb $ssss E6b4bS54h4b4 aaeaeeee TTT 9-07-08 18/20

DIP20-P-300-2.54A Unit : mm Boome ooooms 3 | Is a 25.1MAX Nag ME Pests j__'2. oO o Weight : 1.4g (Typ.) 1998-07-08 19/20

SOP20-P-300-1.27 Unit : mm 20 1 HH HAHAH AE J ) | i | wl oN 2 1 10 0.685TYP 0.43+0.1 510.25 13.3MAX 12.8+0.2 bel a3 z at 2 ¢ ryr to <3 S Lapa ad o 0.810.2 Weight : 0.48g (Typ.) 1998-07-08 20/20