TC8830AF

Toshiba Semiconductor

The TC8830AF is a single chip CMOS LSI for voice recording/ playback using the ADM(Adaptive Delta Modulation )

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Me 9097249 0024994 414 METOS3 _ TC8830AF-1 i TOSHIBA (UC/UP) b4E D° 1. GENERAL The TC8830AF is a single chip CMOS LSI for voice recording / playback using the ADM ( Adaptive Delta Modulation ), It composes a voice recording system with a static RAM for voice memory and an audio circuit including a microphone, speaker, amplifier, ele. as an external circuit, 2. FEATURES

1 SRAMs ( Static RAM ) are used as a voice data memory up to 4 pieces of 64Kbit, or 4 pieces of

256Kbit. CO It’s possible to expanse at memory up to 8Mbit by external circuit, C2 It’s connectable to microprocessor easily and controlled by 11 kinds of command, Cl Capable of recording / playback maximum 16 phrases at the manual control, 0 4kinds of bit rates ( 32K, 16K, 11K, 8K bps) are provided.

1 Recording playback time is up to sixty four seconds ( with four 256Kbit SRAMs and bit rate to be

16K bps), (1 On-chip microphone amplifier for recording and band pass filter for playback. C1 It's possible to memory back up by standby function, © On-chip ceramic oscillation circuit, =y—| CO Single 5V power supply. = C1 67-pin flat package, ° The bit rate means the number of bits per second to be used. = 311

i TC8830AF-2 mm 9097249 0024995 450 METOS3 TOSHIBA (UC/UP) BYE D~ 3. BLOCK DIAGRAM AND SYSTEM CONFIGURATION

3.1 TC8830AF Block Diagram

VDD VSS1, VSS2 CET~CES, CE,R/W,ALE AO~A14 D0~07 MICIN Cl C2 MICOUT ADI DAO Amp [serene ADM ANALYSIS / ADDRESS COUNTER SYNTHESIS CIRCUIT DIA I>] CONVERTER VOLTAGE FOLLOWER ADDRESS COMPARATOR TIMING GENERATOR STOP ADDRESS REGISTER CONTROL CIRCUIT INDEX REGISTER STATUS BAND PASS REGISTER FILTER OSCILLATION XIN XOUT EOS ACL, PHO~PH3 pO~P3 STAY, RU, WK CPUM, 256K FILINFILOUT 312

mm 9097249 0024956 797 METOSS TC8830AF-3 il TOSHIBA (UC/UP) b4E D-

3.2 Block Diagram Description

(4) Address counter The 20-bit counter to indicate address of the external SRAMs and counted up with 8 sampling under recording and playback, Values can be set or read by commands at the CPU control. (2) Stop Address register ‘The 20-bit register to indicate address to stop recording / playback. Values can be set by commands at the CPU control, but can not be read, (3) Address comparator When the contents of the address counter agree with those of the stop address register, the address counter is stopped. (4) Index register ‘The register to indicate address of the index area on SRAMs in the label index mode ( Refer to section 5.3), (6) Status register ‘The 4-bit register which shows the status of TC8830AF, When RD pin is L label, 1C8830AF gives this contents to data bus (PO~P3) at the CPU control. _- (6) CPU interface aoe The interface circuit for the external microprocessor. This circuit has also the chattering — elimination circuit in the manual control. ‘This chattering elimination circuit has an effect on PO —— to P3 pins ( Start and Stop ete. ). = (7) Sram interface = ‘The interface circuit for the external SRAM. SS (8) Microphone amplifier — Output of MICOUT pin is biased Lo Vref level, and can be connected directly to ADI pin. —— (9) Band pass filter == On chip the 1’st order high pass filter and 2’nd order low pass filler. >= 313

| TC8830AF-4 mi 9097249 0024997 b23 METOS3 TOSHIBA (UC/UP) BYE D

3.3 Example of Voice Recording System

33.1 CPUControl Type

me. Ame. oP, =<] D oom) [>| I tr ye 15ko. iy" C4 "| MICIN: C1 2) MIC ADI DAO FILIN FILOUT our AO~ANA Ky po~ra RE cpu Ac RO~ATA RD WR spam | Ssorute ‘STBY — TCB830AF ero? V, ew pp er xNote 2 uM or | RAM, Vop —+| wa Note 1 256K 4 & i D0~D7 -—t__, XIN___XOUT ret iten Apes.) Syke a ch o.tyr * Notes —-BESKceg ) Refer to section 4.1 Pin Description 314

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1 Playback "3 =_ ww

Standby oy | stay Note 2 cr fi RAM, a Reset SI Laer aw an = i b—!tL— _ 256K D0~D7 ——4 Voo Ve cPum sham == 81 xn XOUT Vet (tax 4pcs.) == Tae cE 0.1 uF = Tivo xa] i w Note} 256K =z) Referto section 4.1 Pin Description 315

il TC8830AF-6 ME 9097249 0024999 4Tb METOS3 TOSHIBA (UC/UP) buE D ~ 4. PIN ASSIGNMENT eraa wp S52 Ble imple TAAAGUATHUN A TOPO AA RPA RAH AAR H 54 33 £0s CTT ss ac Coo cpum Co 32a Vref C—O Ir) A2 micin C—O} fir A3 a =r voo CIT) TOP VIEW rr“ as o2caod Ea S000 — =r wicont =r I abi C—IT} fro A8 ee Fae FILIN C—O 67 2 Foal , 1 HATTA BYUESYSESYR YAR a eS eSas 378 geen E 3 316

Mm 9097249 0025000 416 METOS3 T ee 8830AF-7 TOSHIBA (UC/UP) bHE D

41 Pin Connection

4.2 Pin Desctiptions

i] TC8830AF-8 Mm 9097249 00e5001 752 METOS3 TOSHIBA (UC/UP) b4uE D Manual control CPU control Functional explanation Pull-up/ | 17, | Pull-up/ down down CET | 35 Chip enable output pins for SRAMs. CEZ | 36 At the CPU control, this pins are high CEI | 37 impedance by DMA function. . cea | 38 sTey | 39 | in| None | inputpin# standby mode. XIN. | 40 tn - | Input and vutput pins of the ceramic xouT | 41 Out oscillator. 256k | 42 | in | None | in None _| input pin for SRAM capacity select. RIW Out Read or write strobe output pin for SRAMs. Connect to R/W pin of SRAMs. At the CPU control, this pins are high impedance by DMA function. ALE Out Address latch enable pin for memory capacity up. At the CPU control, this pins are high impedance by DMA function. WR Pull- In the CPU control mode, input pin for write down strobe (PO to P3). In the manual control (at STBY mode, used for bit rate with RD. =L) Pull- In the CPU contro! mode, input pin for read down strobe ( PO to P3 ). In the manual control (at STBY mode, used for bit rate with WR. =L) pHa | 47 Pull- Pull- | Input pins for phrase select in the manual PH2 | 48 down down | control mode. PHI | 49 (at sTBY (at sTBY PHO | 50 =L) =L) p3 | 51 Pull! | 1/0 In the CPU control mode, these are 2 | 52 down bidirectional data bus for commands or PL 53 status between CPU and TC8830AF. po | 54 In the manual control flowing, 1) PO start input 2)P1 stop input 3) P2 auto phrase function select 4) P3 recording or playback select 318

mm 9097249 0025002 699 METOS3 TC8830AF-9 il TOSHIBA (UC/UP) BYE D ~ down down Eos Output pin for end of speech. Gives high level signal under the recording / playback waiting, and low level signal under the recording / playback. cpum | 57 Input pin for mode change. Fix to low level at the manual contro! mode, to high level at the CPU control mode. Vref 0 v0 Pin for connecting the capacitor to the reference voltage circuit of the on-chip Op- Amp. . MICIN Input pin for on-chip MICAMP( First stage ). Microphone should be connected to this pin through capacitor. a [#[o Ge Output pn for on-chip MICAMP( Fist tage — C2 Input pin for on-chip MICAMP ( second a stage ). C1 should be connected to this pin SS through capacitor. Se MIC Out Output pin for on-chip MICAMP ( second — OUT stage). —= ADI Input pin of the voice analysis circuit. —= Connected to MICOUT. Otherwise, signal ES== should be input via a coupling capacitor. == Out Output pin of the voice synthesis circuit Ss with voltage follower. Output signal is = biased to Vref. No voice appears at SS recording. . ——— SS [run [er [im | =m | [input pins of the on-chip band pasriter == 319

i TC8830AF-10 @@ 9097249 0025003 525 METOS3 TOSHIBA (UC/UP) BYE D

5 SPECIFICATIONS

5.1 Recording / Reproducing Part

D/AConverter | 10-bit voltage type Bitrate 32K/16K/11K/8K bps At the manual control 16 phrases

5.2 Others

Microphone . amplifier Two-stage, Gain = 46dB (TYP. ) On chip filter for nd order low pass + todas igh past Up to 4 pcs. of 64Kbit, or 4 pes. of 256Kbit. RAM forstoring voice | Example of usable memory ( Access time ) 320

mM 9097249 0025004 4b1 MTOS3 TC8830AF-11 i] TOSHIBA (UC/UP) BYE D.

5.3 Operations and Functions

‘When composing a voice Recording / playback system with ‘TC8830AF, control method is classified into the CPU control and the manual control using switches,

5.4 Manual Control

5.4.1 Selection of Phrase

Using 4 input pins of PHO~PH, ‘The recording / playback of maximum 16 phrases can be performed. Before starting the recording / playback, And using auto phrase function ( refer to section 5.4.7), maximum 68 phrases can be performed, Phrase No. should be specified in 4bit code. Phrase number is as follows, and should be selected at sequence from low order phrase at the recording, but can be selected at random at the playback, Table 5.1. Example of phrase number (sb) (sb) Phrase No PH3 PH2 PHO No.0 0 0 No.1 0 1 * : * | 1=Hlevel => No.15 1 1 [o=t tevet — Recordin: Recording is made in order of phrase NO.1, NO.2, NO.3 = Phrase 0001(NO.1) X Phrase 0010(N0.2) X 0010(NO.2) X Phrase 0011(NO.3) SS Playback Playback is made in order of phrase NO.3, NO.1, NO.2 Phrase 0011(NO.3) X Phrase 0010(NO.2) =| Phrase 0001(NO.1) Fig.5.1_ Example of phrase selection 321

| TC8830AF-12 ml 9097249 0025005 378 METOS3 a buE D TOSHIBA (UC/UP)

5.4.2 Selection of Bit Rate

‘The TC8830AF can use 4 kinds of bit rates as shown in Table 5.2, 8K, 11K, 16K and 32K bps, which are selected by WR and RD pins, ‘The bit rate should be select under the recording waiting state or playback waiting state. Table 5.2 Bitrate WR Bit rate ee a

5.4.3 Recording

The TC8830AF has the 20-bit address counter, and voice data is wrilten into SRAMs from the address designated by it’s value. When the recording newly, first, it is necessary to reset the address counter and index area ( refer to section 5.6 ) by ACL signal. Setting the P3 pin to 11 level results in the recording waiting state. When the PO pin goes to H level ( Start input ), the recording starts and the address counter is added successively, When the P1 is set at H level ( Stop input ) or when the value on the address counter reaches the maximum address ( Refer to section 5.5.6 ) of SRAMs by ADDRESS OVER FLOW DETECTOR ( refer to section 5.6), the recording is stopped. Since this maximum address is changed with SRAMs capacity. Further, the recording is stopped when error address in the SRAM, However, when the SRAMs capacity is fully used, subsequent recording is not allowed to protect the data stored previously in SRAMs, Therefore, the address counter should be reset by the ACL . signal before new recording. ‘When the recording starts, a value of the address counter at the start (Start address ) and when the recording ends, that at the stop ( Stop address ) are automatically written into a part of SRAM, respectively, : 322

Mi 9097249 0025006 234 METOS3 Tess30AF-13 |] TOSHIBA (UC/UP) BYE D -~

5.4.4 Playback and Pause Function

Setting the PS pin to L level results in the playback waiting state, When the PO pin is set at H level, the TC8830AF starts the playback after loading the start address and stop address, which have been written at the recording, into the address counter and stop address register, respectively. When the P1 pin is set at H level during the playback, the playback is paused. Playback is continued when the PO pin is set at H level under this condition, ‘The playback is stopped when the P1 pin is set at H level during the playback pause state or when the value of the address counter agrees with the stop address by ADDRESS COMPARATOR FLIPFLOP ( refer to section 5.6.7).

5.45 Timing of Recording / Playback

P3(recording) __/ PHo~PH3 = Z/77X__Phrase A X7/7/7 7777 777K Phrase 8 XT7TTTTTTTTTTT TT. PO (start input) P1 (stop input) s> EOS — ‘Address over flow ™, detector SU rrr nnn nnn nnnnnnn nad aan anancncananaasbecanaancunaune set Seosemene Recording i Recording , Recording —— waiting state Recording | waiting state Recording | waiting state == Recording Recording of phrase A of phrase B == TC8830AF not receive start input under the recording Fig.5.2. Timing of recording 323

il TC8830AF-14 mm 5097249 0025007 170 METOS3 TOSHIBA (UC/UP) we oD HIBA (UC/UP) bUE D P3 (recording) \\ PHO~PH3 X— Phrase AX PO (startinput) P1 (stop input) EOS ‘address comparator) | eect | {lipflop Playback Playback watting state Playback _ walting state Playback of phrase A TC8830AF not receive start input under the playback Fig.5.3. Timing of playback P3 (recording) ——\\ PHO~PHS X_Phrase AX PO (start input) P1 (stop input) EOS ‘Address comparator ec eeceeeneeene {lipflop merennnsachansannsannnaccncaeccacamanncasecacas bases Playback Playback waking state Playback warting state Playback of phrase A Fig.5.4 Timing of playback stop 324

mm 9097249 0025008 007 mTOS3 TC8830AF-15 |] TOSHIBA (UC/UP) BYE D~ P3 (recording) \\ PHO~PH3 X Phrase X oo PO (start input) P1 (stop input) EOS ‘Address comparator my flipflop ens enn Cea hae Mommmnenennnns Playback Playback walting state Playback Playback waiting state Playback Playback of phrase A continue of phrase A Fig.5.5 Timing of playback release

5.4.6 Restriction of Start Input =

When the recording and playback starts, there is the following restriction between PO pin ( start = input) and Pi pin ( recording ). PO(startinput) P3 (recording ) Je ST Je- = ST Recording . Playback chattering —— ts7=32ms fouk =512Kiz Fig.5.6 Timing of change at recording / playback 7 325

| TC8830AF-16 mm 9097249 0025009 T43 METOSS TOSHIBA (UC/UP) B4E D

5.4.7 Auto Phrase Function

Phrase No, can be increased automatically at the recording and playback. Initial value of phrase No. setting by PHO~PHS pins. This function is enabled when the P2 pin is set to H level under this state, Valid phrase is No, 0~62. ifover the No. 62, lost to content of SRAM, And over the phrase No. 16 is not direct playback aitate ee eee ae Initial phrase | X13 XXXXXXXXXXXXXYXRXXEX! 4 XXXXXXXXNXXXKMAMKKXKNA a PO( start) naw) LT stop stop stop stop stop stop Internal phrase [| 3(set) [ afauto) [ S(auto) | 1aset) [15 (auto) [16 (auto}| Fig.5.7 Auto phrase recording 3 (recording) \\\\\\Y\\ Bitrate ee ae Initial phrase [OX] 3 XXXXXXXXXXXXXXKXNXEX| 4 XXXXXXXXXKXKXXXKXKKKXA start start start t t + t 4 stop stop stop stop stop Internal phrase | | Stset)_[ aCautop ase) (auto) "| : Fig.5.8 Auto phrase playback 326

MH 9097249 0025010 765 METOS3 - TC8830AF-17 il TOSHIBA (UC/UP) buE D ~

5.4.8 Status Change at The Manual Control

PO (start) P1(stop) Po(start) — fF fo , Recording Recording ; Recording waiting 1 (stop) i . P3 (recording ) Automatically recording stop by . ADDRESS OVER FLOW DETECTOR P3 (recording) =H . PO (start) P1 (stop) Po(start) fF a Playback Playback <) = waiting — Ler s=— Playback Rinbeietaketerell —= Automatically playback stop by ——s ADDRESS COMPARATOR FLIPFLOP = Pr(stop) — Pi (stop) (stop PO (start) = pause = Fig.5.9 Status change at the manual control 327

iI TC8830AF-18 @ 9097249 0025011 bT1 METOSS TOSHIBA (UC/UP) b4E D

5.4.9 Chattering Elimination Circuit

Atthe manual control, the chattering elimination cireuit is actuated to prevent from malfunction due to the switches connected to the PO~P3 pins. PO, P1, P2 and P3 pins teh | ton jt tof —| ton | 32800/fcik toit_ | 32800/fc.k ton, toff is about 64 ms, at fo.k =512 kHz : Fig.5.10 Chattering elimination circuit Input signal should be applied stably for more than ton and torr. Start and stop signals should be applied stably for more than ton and torr.

5.4.10 EOS Delay Time at Manual Control

[an] 16400 / feux | 32800// ferk tep is about min 32 ms, max 64 ms, at fe = 512 kHz Fig.5.11 EOS delay time at manual control 328

mi 9097249 0025012 538 METOS] Tcses0AF-19 |] TOSHIBA (UC/UP) BYE D-

5.5 CPU Control

At the CPU control, the operation is controlled by 11 kinds of commands and a CPU can read the status of TC8830AF by 4bit status register. In addition, the TC8830AF has the ADDRESS OVERFLOW DETECTOR ( Note 1 ) and ADDRESS COMPARATOR FLIPFLOP ( Note 2) which control the recording and playback operations.

5.5.1 Howto Write Commands

As shown in Fig, 5.12, Dusing RD pulse, read status from TC8830AF and check BUSY flag @If not busy state, after setting up command in PO~P3, write a command using WR pulse. In case of such 3 nibble commands as LABEL, keep at command processing time ( refer to section 5.2.5 ), @write the 2nd and 8'rd nibbles. After the 1’st and 2’nd nibbles of a 3 nibble command, other commands can not be written. This also applies to 7 nibble commands like ADLD1 and ADLD2. How to write DIRD and ADRD commands, refer to section 5.5.2 RD fT = More than command processing time. WR Check for busy = a. a — or ® Command @ ° —— Yi Output state Fig.5.12 How to write command = 329

i] TC8830AF-20 mm 9097249 025013 474 mTOS3 TOSHIBA (UC/UP) BYE D

5.5.2 Commands of TC8830AF

(1) Should notbe issued 03 [o[ofofo]oo (2) NOP(1nibble) D3 [ofofo]:] Do No operation. But under the recording waiting state, this command sets into the playback waiting state. In addition, this command is used to reset OVR flag in the status register. (3) START(Lnibble) D3 [ofo[sfo] bo ‘This command is used to start the recording / playback in the DIRECT MODE from the address shown by the address counter, In addition, this command is used to set EOS flag in the status register. (4) STOP(1 nibble) v3 [o[o]1]1] 00 When this command is executed under the recording, the recording is stopped. A value of the address counter is written into the INDEX AREA of SRAM as the stop address, In addition, this command is used to reset NOS flag in the status register. When this command is executed two times under the playback, playback stops, to reset BOS flag in the status register. (©) ADLD1(6nibbles) 03 [o]1 JoJo] 0 Sets the successive 6 nibbles data in the address counter. Resets the ADDRESS COMPARATOR FLIPFLOP, In addition, this command sets into the playback waiting state. (6) ADLD2(6nibbles) 03 [o]s[o[1] po Sets the successive 6 nibbles data in the stop address register. Sets the ADDRESS COMPARATOR FLIPFLOP. Set a value of ADLD2 is more than ADLD1, In addition, this command sets into the playback waiting state, (7) CNDT(2nibbles) 03 [o]1]1[o] 0 Specifies bit rate and enable / disable of ADDRESS OVER FLOW DETECTOR with the successive 1 nibble data, In addition, this command sets into the playback waiting state, (8) LABEL (3 nibbles) v3 [ofa] ifi]oo Specifies Phrase No. by the successive 2 nibbles data and starts the recording / playback. When this command is issued under the recording waiting state, the contents of the address counter is written into the index area of SRAM and recording starts, In the playback waiting state, starts the playback after reading start address and stop address from index area of SRAM. 330

mm 9097249 0025014 300 MTOS3 TC8830AF-21 il TOSHIBA (UC/UP) BYE D (9) ADRD(1 nibble) 03 [1] o[o]o] vo Reads the contents of the address counter. ‘The contents are come out by 4 bits at a time from the low order address side against 5 successive read accesses, During this period, the contents of the status register can not be read, Next command should not be issued without performing 6 read accesses, In addition, this command sets into the playback waiting state. (10) REC (1 nibble) o3 [1 Joo] 1] v0 7 Changes the playback waiting state to the recording waiting state. (11) DIRD(1 nibble) o3 [1 Jo[1Jo] po Reads out data of SRAMs in 8 bits data from the address shown by the address counter for the successive 2 read access, During this period, the contents of the status register ean not be read, the address counter isnot increased, In addition, this command sels into the playback waiting state, (12) DTWR(2nibbles) 03 [1Jo[1] 1] bo Writes 8 bits of the successive 2 nibble data into SRAMs from the address shown by the address counter, the address counter is not increased. In addition, this command sets into the playback waiting state. (18) Should not be issued (14) Should not be issued = o3 [11 To] 1] 00 (15) Should not be issued v3 [1] 1] 10] vo SS (16) Should not be issued — Under the recording/ playback, any command other than STOP should not be —— issued. 331

Mme 9097249 0025016 183 METOS3 TC8B30AF-23 || TOSHIBA (UC/UP) bB4E D.

55.3 Status Register

‘The status register consists of 4 bits, When the RD pin is set to L level at the CPU control, data of the status register is came out to PO~P3 pins and the internal operating status of the TC8830AF can be checked, Each flag of the status register is explained in following (‘Table 6.4 ), (1) OVR flag It is indicated that the recording ends as the address counter exceeded maximum address of SRAMs under the recording, This status is reset by NOP commands. (2) BUSY flag ‘When this flag is set, it indicates that the TC8830AF is in reset state or processing a command internally, Don’t give any command from microprocessor, If the command is given, the internal status may possibly becomes uncertainty, When the ADLD1, ADLD2 and LABEL command is issued, until input of required data ends, this flag is not released. (3) EOS flag ‘This flag becomes set under the recording / playback waiting state, and reset during recording or playback. ‘The value is the same as a value appeared at the EOS pin, Table 5.4 Status register [_stausregiter [| ovn | ausy

5.5.4 BUSY Flag =

Conditions for setting BUSY flag set are broadly classified into the following conditions, =—— : (1) Reset process ——| ‘When the ACE pin becomes L level, BUSY flag becomes set. When the ACL pin returns to H level again, the internal state of TC8830AF is initialized and after all are completed, BUSY flag becomes reset. (2) Command process ‘When it is detected that WR pins have become H level from I, level at the CPU control, BUSY flag becomes set, When the process of command is completed, BUSY flag returns to reset again, ==] ‘The command process is actually started after return of WR pin to H level has been detected. 333

|| TC8830AF-24 mm 9097249 0025017 O17 MBTOSS tan CUCJUP) ED TOSHIBA (UC/UP) bu

5.5.5 Command Processing Time

‘Times required for processing commands are shown below. When commands is issued ‘successively, issue them at intervals of more than these command processing times, Table 5,5. Status register Reset process (ACL)* 24600/ fcxk (sec) NOP, START, STOP, ADLD1, ADLD2, CNDT, REC, DTWR 35/fcik (sec) commands write LABEL, DTRD, ADRD commands write 70/ fc. (sec) Data write of ADLD1, ADLD2, CNDT, DTWR command 35/ fuk (sec) Data write of LABEL command 70 / fcxx (sec) Read access after the DTRD, ADRD command 70 / fox (sec) *Note; No count Oscillation rise time ( Oscillation rise time is several mS in case of CSB512) fei = Oscillation frequency (Hz)

5.5.6 Address Overflow Detector

When the address counter exceeds maximum address that is detected by this detector during the recording with LABEL command at the CPU control. Enable or disable of detector is selected by CNDT command, This detector is enable only at the manual control. When the address overflow is detected, the recording is stopped, a value of the maximum address is written into the index area of SRAM as the stop address, and then the address counter is preset at address 100 ( HEX ). In addition, the OVR and EOS flag in the status register is set.

5.5.7 Address Comparator Flipflop

‘When this flipflop has been set, the recording / playback is stopped if the contents of the address counter agree with those of the stop address register. When it has been reset, the recording / playback is not stopped until the STOP command is given, (Exception : Address overflow in the preceding item 334

mm 9097209 o02s0u8 TSE mMTOSS TC8830AF-25 |] “TOSHIBA (UC/UP) bHE D®

55.8 Change of Internal Blocks

Table 5.6 Change of internal blocks Te command Stop Address output (ACL . “eels = | ia = ad (1004) |_srarr [star {trove Ps | |_stor [stor | et TO |v | ts Pe ee a |_| | cor | fT || Jw fos [os fos tt a a — RD = ee oe |---| a | | = a a es = S:SET = R: RESET == START : Address counter Operate == STOP : Address counter stop = Brank : No change = (Note) EOS flag means that set is ‘1' and reset is 0" —— 335

|] TC8830AF-26 mm 9097249 0025019 992 METOS3 TOSHIBA (UC/UP) b4uE PD.

5.5.9 EOS Delay Time at CPU Control

[ea] feik = Oscillation frequency Fig.5.13 EOS delay time at CPU control

5.5.10 Modes in CPU Control

‘There are two modes about both recording and playback at the CPU control. (1) Direct mode Designate start/stop address, and bit rate by each command. (2) Label index mode Designate phrase by LABEL command, start / stop address are written into the sgme part (Index area ) of SRAM. Refer to section 5.3 LABEL INDEX MODE. 0000H QOOFFH |... RAM 1 (Can not be used as data area) O7FFFH OFFFFH Data area RAM 4

1 FFFFH

Fig.5.14 Memory map (In case of 256K SRAM) 336

mM 9097249 0025020 bO4 MTOS3 TC8830AF 27|| TOSHIBA (UC/UP) BYE D ~

5.5.11 Status Change at The CPU Control

At the CPU control, the TC8830AF is controlled by 11 kinds of command, ‘The relations between the recording and playback state and commands which are concerned with the recording and playback operations are as follows. Table 5.7 Status change table at the CPU control SEE] ere [tome | aoa) Recording Starts recording Starts recording Keptin the recording waiting state waiting Recording Don't give the START Don't give the LABEL Stop recording and returns to the command command recording waiting state Playback Starts playback Starts playback Keptin the playback waiting state waiting Don’t give the START Don't give the LABEL Placed in the playback waiting state command command (executed two times) START command = LABEL command === STOP command Recording Recording waiting STOP command Recording 7 = = NOP command Ss ~ en * ADLO1 command Automatically recording stop by —— ADLD2 command ADDRESS OVER FLOW DETECTOR CNDT command ADRD command DTRD command REC command DTWR command START command LABEL command layba Playback | stopcommand (Playback STOP command Playback aN _ltwortimes) — s “7 = Automatically playback stop by / ADDRESS COMPARATOR FLIPFLOP: Fig.5.15 Status change at the CPU control 337

| TC8830AF-28 mi 9097249 0025021 S40 mETOS3 TOS sn Ta HIBA (UC/UP) buE D

5.5.12 Example for The Flowchart of Recording / Playback at LABEL INDEX MODE

(1) Recording In case of changing __thebitate, i cnoTcommand |. [ Selection of bit rate. : REC command . [ Recording waiting state. Selection of Phrase. The TC8830AF is stars TABEL command) [ recording when the command process is terminated [a <a cone [ Check recording starts with FOS flag or EOS pin. ves [ves Check recording exceeds the SRAMs capacity oman with EOS flag or EOS pin, > - <ren [ Decide to stop the recording or not. YES STOP command). [ Recording stop. Next phrase ? os oof Decide to continue next phrase. NO Fig.5.16 Recording procedure at the LABEL INDEX MODE 338

m™ 9097249 O025022 447 MMETOS3 TC8830AF-29 i TOSHIBA (UC/UP) buE D ~ (2) Playback Incase of " bit rate. 0 TT f i co [ Selection of bit rate. TABELeommand Selection of Phrase. The TCB830AF starts terminated, Ln <n cel Check playback starts with EOS flag or EOS pin. YES bse <oser “ [ Check the end of playback with EOS flag or EOS pin. YES s= se { Decide to continue next phrase, = via = Fig.5.17 Reproducing procedure at the LABEL INDEX MODE SS 339

| TC8830AF-30 M™ 9097249 0025023 313 METOS3 TOSHIBA (UC/UP) bUE D ~

5.5.13 Example for The Flowchart of Recording / Playback at DIRECT MODE

(1) Recording In case of changing VW thebitrate. a, : Sek ia { Selection of bit rate. ADLD} command ~ { Designation of start address. APL oman - f Designation of stop address. START command soe f Recording start. Lie <“ses vo Check recording starts with EOS flag or EOS pin. YES [2 ses oe { Check the end of playback with EOS flag or EOS pin. YES [ Decide to continue at other or same address. NO Fig.5.18 Recording procedure at the DIRECT MODE 340

mm 9097249 0025024 257 METOS3 TC8830AF-31 il TOSHIBA (UC/UP) BYE D ~ (2) Reproducing In case of s dhe bitrate. “22 i t ‘ND DI bre <“sne cu { Check playback starts with EOS flag or EOS pin. Yes == SS “[ Check the end of playback with EOS flag or EOS pin. YES <n of Decide to continue at other orsame address. NO Fig.5.19 Reproducing procedure at the DIRECT MODE —— 341

i TC8830AF-32 mm 9097249 0025025 196 mMTOS3 TOSHIBA (UC/UP) BYE D.

5.5.14 Write / Read Data of SRAMs

(1) Data write ADLD1 Aa a { Designation of the write address. <n of Check end of all data write. NO Fig.5.20 Data write procedure (2) Data read Al ; DIRD command [ omeenmand |. . [ Data read mode. of Input of 8 bits data. <n > [ Check end of all data read, NO Fig.5.21. Dataread procedure 342

mm 9097249 o025026 O22 mETOS3 TC8830AF-33 || TOSHIBA (UC/UP) BYE D’.

5.5.15 Read Address

ADRD command is used to read a content of address counter at stop of recording and playback <Reinen> { End of read. YES Fig.5.22 Address read procedure

5.5.16 Howto DTRD/ ADRD Commands —

More than command processing time —S Mts tao —= RR ——_+-++ —| jee len een ee = PO~P3 == Command output ata input = DTRD = ADRD WK Output state = Fig.5.23 How to DTRD/ ADRD command = 343

i] TC8830AF-34 me 9097249 GO25027 TET MBTOS3 TOSHIBA (UC/UP) buE D .

5.6 Label Index Mode

‘The recording / playback methods for manual control and the LABEL INDEX MODE at the CPU control are described here, At the manual control (LABEL command under CPU control ), the address is indirectly specified using phrase number and index area in which TC8830AF writes the start addresses and stop address ofeach phrase, The memory maps of SRAMs at the LABEL INDEX MODE are as follow. 0000H 00000H \\ Index area } Index area OOFFH }- RAM 1 ~ OOOFFH }-- RAM 1 FFFH O7FFFH RAM 2 RAM 2 3FFFH Data area OFFFFH ? Dataarea RAM 3 RAM 3 SFFFH 17 FFFH RAM4 RAM 4 TFFFH 1FFFFH 64K SRAM 256K SRAM Fig.5.24 Memory map in the LABEL INDEX MODE Maximum address that can be changed varies depending upon type and quantity of connected SRAMs. In any case, address 0 ( HEX ) ~ FF ( IIEX ) are used as the index area, and the succeeding address 100 ( HEX ) and up become the voice data area. Start address and stop address are recorded in the index area by the TC8830AF at the recording. And data read out from this area are loaded on the address counter at the playback.

5.6.1 Recording of Phrase

In performing the recording newly, Reset the TC8830AF by the ACL signal then address counter is preset to 100 ( HEX ) and 0 clear to index area. A bit rate anda phrase No. are specified and start signal is issued, then the recording starts, The contents of the address counter ( Start address ) is written into the index area of SRAM before recording. During the recording, the value of the address counter is increased successively, When the stop signal is issued during the recording, the recording ends and the contents of the address counter ( Stop address ) is written into the index area, ‘Thereafter the value of the address counter are added with one to prepare for next recording. 344

Mi 9097249 o025028 ITS METOSS TC8830AF- 35 |] TOSHIBA (UC/UP) buE D. To perform the recording for other phrase successively, phrase No. is newly designated and the Index _area , Data area H H Current address counter i} Phrase 1 Phrase2 / Unused H * 0100H Phi 2 . / rase Phrase 1 Presa eS Stop address Phrase 2 Phrase 1 Start address Start address (Phrase 1 Stop address +1) Fig.5.25 In case of recording two phrases

5.6.2 Playback of Phrase

When any recorded phrase No. is selected and start input is given, voice corresponding to that phrase No, is reproduced. Phrase No, can be designated irrespective of sequence of the recording. Giving the two stop input during playback, this phrase stop. — If the playback is started by designating phrase No, that was not used for the recording, not sound 2 at this phrase, —| ‘The playback is started after the start address and stop address are set in the TC8830AF from the index area of SRAM. When the playback ends, the value of the address counter are added with (+ 1) ==

5.6.3 Addition of Phrase

First, reproduce the last phrase at the recording completely so that the address counter can an indicate the address next to the stop address of the last phrase. Change the playback waiting state to the recording waiting state, Don't reset the TC8830AF at this state. When the recording is made by designating any more than end of recorded phrase No. to be added. 345

i] TC8830AF-36 me 9097249 0025029 431 METOS3 PERETTI buE D TOSHIBA (UC/UP)

5.6.4 Label Index Mode Operations

‘The operations of the TC8830AF and SRAMs in LABEL INDEX MODE are described in the following. @ The index register addresses an —>| register To nwecant astartinput. index @ Avalue of the address counter is area written into the index area of counter (Start address) Ttopaddress | \\_Po-07@v01-v00} Data area register TCBB30AF ‘SRAM (256K) Note: | ADManalysis and synthesis circuit ice register @ ao-ata register (ADI Vo ® Voiceis analyzed (recorded) by +" ADM analysis circuit and voice data is written into the data area counter of SRAMS, Voice data © The address counteris counted ‘00~07 @uo1~vot and steps @ and ® are register (lode = 1 Bitrate) index Jao~ara dares © Theindex register addresses an Stop input i sr ereertt na MC index area of SRAM according to 9p inpy register © wan gist ee ® Avalue of the address counter is : counter (Stop address) ®\\ |oo-v7 vor~108 ® The address counter is counted Stop address | “g—————>+ upand the recording ends. register Fig.5.26 Recording 346

Mi 9097249 0025030 553 METOS3 TC8830AF-37 i TOSHIBA (UC/UP) BYE D- “Address co} rh. index register addresses an register nooate @ Start address, stop address and bitrate are loaded to TCB830AF from the index area. counter ‘Stop address 190-07 @uo1~Voy register Note: ADM analysis and synthesis circuit, UJ @ The address counter addresses a A0~A14 Address data area of RAMs. Index i if register . . register ROAR ® Voice datais fed into ADM analysis and synthesis circuit to B +e | iedex produce voice. “Address © The address counter of TC8830AF counter is counted up. Ito © The address counter and the sto, Stop address p0~07 @vo1~vor Data area address register of the TCHBBOAP. — Tegister $ ? are compared and when they —— a agree with each other, the == (DAO) playback stops at next address. f not, steps @ and © are Ba repeated. SS Fig.5.27 Playback >= 347

il TC8830AF-38 @ 9097249 0025031 44T METOS3 TOSHIBA (UC/UP) bYE D

5.6.5 TheIndex Area

‘The index area is used for the recording / playback at the manual control and LABEL INDEX MODE at the CPU control. This area consists of 2K bits from address 0 ( HEX ) to FF ( HEX ), securing for 63 phrase ( 32 bits per phrase ). At the recording, start address and stop address of each phrase are written into index area, And at the playback, the contents of this area are read out and set in the address counter, ete, ‘The contents of the index area for each phrase are shown in the table 5.8. A0~A19 denote the start address and A19 represent the most significant bits of them respectively. Further, stop address equal start address of next phrase. To read out the contents of the index area, obtain the top address of the index area corresponding to each phrase from phrase No. , and after setting it in the address counter by the ADLD1 command, read it in unit of 8 bits by the DIRD command. On the contrary, to write data into the index area, after setting the top address of the index area in the same manner as above, write data by the DIWR command, ‘The index area is cleared to by the ACL signal. A Don't select the start and stop address in index area by ADLD1 or ADLD2 commands at the DIRECT MODE. 348

mE 9097249 0025032 326 METOS3 TC8830AF-39]| TOSHIBA (UC/UP) B4E D Table 5.8 Memory map of index area Address [suf [as [as [na oa fa [an | no | ee ee | ee ee eee AA Sartadaressof [95 | Ais | Ald | A13| Ai2_[ Ait | aio | ad | _aB_| LT DN | oa, | az | as [as [aa [as [az [ar | ao | a re ee | [ --

1 Hi 1 1 H 1 1 1 i 1

f] i H Hi i H i i i H 1 Hq H Hl { | i i { i i fl == re eee =| Startaddressof p54 [AIS | Ald | Ata A12 [AN |-AtO == [Fn pf [ren | a7 | as Aa = Startaddressof [“rgy [Ais | Ala A13 an Taio fag at pivesenog? Fay | - |= | = | - [ats [ais — A OO = wonuiewa — prraeto TT rey [= [= | = P= Pais | ate At | AI | —= [ofa === 349

iI TC8830AF-40 mi 9097249 0025033 2b2 METOS3 TOSHIBA (UC/UP) . b4E D-

5.7 DMA Function

‘The TC8830AF has the DMA function at the CPU control. When both the RD and WR pins are set to L level at the CPU control, the AO~A14, DO~D7, CE, CE1~CIE4 and IW pins are placed in the high impedance state. ‘This function is possible to release the connected SRAMs from the TC8830AF, WR TN RB ooTFEee AWA > nnn nnn nnn X OO . __ CE1~ Cea Wrenn no -----<X —_ RW ) aiatatetetetatatabatatetetetete 4 Fig.5.28 Timing of DMA function ‘This function selecting at the recording waiting state or playback waiting state, Placing DMA function, set the RD pin at H level after setting the WR pin at L level, Ifthe RD pin is first set at L level, the PO~PS pins are placed in the output state until the WR pin becomes L level, Releasing DMA function, set the WR pin at H level after setting the RD pin at H level, write the NOP command into the TC8830AF. 350

mm 9097249 GO25034 179 MMTOS3 TC8830AF-41 il TOSHIBA (UC/UP) BYE D

5.8 Standby Function

When the STBY pin set at H level under the recording waiting state or playback waiting state, the ‘TC8830AF is placed at standby state. ‘The status is shown below, (1) Oscillator stop and low power state, (2) Sets the CE and CET~CEA pins at H level, and external SRAMs places to the minimum standby current mode. At this state, the contents of RAMs can be remained. (3) AO, A2~A14, DO~D7, ALE and R/W pins at L level, (4) AlandEOS pins at Hlevel. (6) _ Internal pull down resisters are unconnected (P0~P3, RD, WR PHO~PHS ). (6) D/Aconverter stops and low power state, (7) ‘The microphone amplifier and band pass filter stops and low power state.

5.9 Reset Operation

5.9.1 The Status Under Reset Operation

When the ACL pin is set at L level, TC8830AF stops all operation such as recording! playback. Further, BUSY flag in status register becomes sot during this period. ——

5.9.2 The Status After mRset Operation =a

When the ACL pin becomes from L to H level, the internal state of 'C8830AF is initialized as == shown below. a= (1) Set the playback waiting state. == (2) Address counter and stop address register are preset to 100 ( ITEX ). = (3) 0 clear to index area of SRAMs, ADDRESS OVERFLOW DETECTOR is enable state and SS ADDRESS COMPARATOR FLIPFLOP is reset. — (4) Atthe CPU control, bit rate becomes 8kbps. == (5) OVE flag in status register are reset, => After terminating the above completely, BUSY flag is reset. = 351

i] TC8830AF-42 mm 9097249 0025035 035 METOS3 TOSHIBA (UC/UP) UC/UP ) buE D

5.9.3 Reset Processing After Power On

When the after power on, the following items become unstable, (1) Recording and playback state, (2) Address counter. (3) ADM analysis / synthesis circuit, (4) Other processing circuits such as start and stop processing. ‘Therefore, to initialize this unstable condition and assure proper operations, apply ACL signal. ‘(KCE signal to be given after power ON and it’s pulse width are shown in Fig.5.29, Power source | le toa ; a —| Jetaa i {4 14s(min. ) : | initialize time i i 48ms (max. ! 1 (Refer to section 5.2.5) 1 Fig.5.29 ACL pulse width However, if width of tpa after power ON is long, the unstable status lasts and causes malfunction (start recording / playback, etc, ) in Fig.6.29, So, a power on reset circuit is constructed by attaching a 1F capacitor to the ACL pin, makes the system initialization is possible immediately alter power ON as illustrated in Fig.5.30. — R(5kN~20kN) ACL 1a ake C - TC8830AF Fig.5.30 Power on reset circuit 352

ME 9097249 0025036 T?7L mETOS3 TC8830AF-43 | TOSHIBA (UC/UP) b4E D. Power source VIH Sy, VIL +} ' a 7 ot tact (Determined by time constant of CR, —st bet about 6.7ms at R=7kQ) Fig. 5.31 ACLinput at power on reset However, the power on reset is effective only for a rapid step power rise and when power rise is . gentle or power on/off is repeated in short cycle, no system initialization is performed. Further, if the ACL pin can be controlled by a CPU regardless of power on / off at TC8830AF side, the system initialization can be made as shown in Fig. 5.32 Power source fo Xai i —>! }<— (Varying depending upon stable status of {| power rise, several ms are required ) =s=— Fig. 5.32 System initialization by CPU control 353

iI TC8830AF-44 =m 9097245 0025037 908 mETOS3. “TOSHIBA (UC/UP) BYE D

5.10 Access Timing at SRAM

SRAM access timing is different at manual control and CPU control. Each access timing is shown below and AC characteristics refer to section 6.4.

5.10.1 Recording / Playback at Manual Control

(1) Recording ( Force the stop input ) ‘P3(REC) PO(START) Pi(sTOP) owas YY LMMMak XX XllakK X XX XHK XX XK X X ME power YW, wasn Yak KX XUX-»_/ XXX _/ WX XX E. RW [ \\ / \\ STITT nr nr Saag / tieteresoa) fo eure _/ (2) Recording ( Address overflow ) ‘P3(REC) PO(START) i = aoraia YY wirio Yd XX XWIX X XX -XUK XX XMIIX X XW power Wj wenn WMMUK X X XK -»_/ WW-XK _/ WX X XE RW [ \\ | \\ eT TT nnn ann etn / trteresioay J vag / Fig. 5.33 Recording at manual control | 354

“Mm 9097249 0025038 844 m—TOS3 TC8830AF-45 il TOSHIBA (UC/UP) 7 buE D . (3) Playback ( Force the stop input) P3(REC) ee ‘PO(START) Pause Stop PA(sTOP) BO a i ef ao-ars Virwinso VX XX XK XX -XK-XZX XK LLL o-0r Irn ZY TTT YIIT ar 0 0 Y, RW A ye Or (4) Playback ( Auto stop) PO(START) = BOS a ao~are Yrinw YK XX XK XX XUAXK XK -XIX XL = or Fry TIT WITT et 0 . CCGz dl ww NN "Ne Sesang—// _reang—_// resdcyn _/ = Fig. 5.34 Playback at manual control 355

il TC8830AF-46 wi 9097249 0025039 780 METOS3 TOSHIBA (UC/UP) BYE D.

5.10.2 Recording / Playback at CPU Control with LABEL INDEX MODE

(1) Recording ( Force the stop command) . iting Yd of 0 conan sree comunatvting | | i eee. ro~aie YH WLM XX XX X XX XW XX MMMX X¥ X Mt co~-or WY VM XK XU »_/ WX XG _ "WWM X X_ Mz RW rn, tneterostoay—\\ J ning —_/ (2) Recording ( Address over flow ) tng edd Le conmaed Wa a | I neneinnaeeneemnerere ao~ala YY wisn Yak X X KWAK X XX XWX XX X)]JWHUK X X XH co~or Wg wino YYWWUUAK XX XU »_/ WW XX )_/WZX_ X X MW RW | = AA Ana anna ving —_/ tmtewsieay\\ J neg —_/ Fig. 5.35 Recording at CPU control with LABELINDEX MODE 356

mm 9097249 OO25040 4T2 MMTOS3 TC8830AF-47 |} TOSHIBA (UC/UP) BYE Dé (8) Playback (Force the stop command )

7 Welung 3'ed data of LABEL command ee ae

a | rs | i es AYO ODD OAD AD) W UMMM w/o =e naa owing esdng—_// teaderte _/ : (4) Playback ( Auto stop) Address comparator flipflop =| ec TY DOO) Ud @ MMM von Gy TT Te Te EEL ww Fa >"—eeeeee a = San ara oan / tending —_/ readyte _/ — Fig.5.36 Playback at CPU control with LABEL INDEX MODE a 357

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5.10.3 Recording / Playback at CPU Control with DIRECT MODE

(1) Recording ( Force the stop command) . ies SOP command ring | | i es savas WIT ws VTITTIIIIETIEEIEIEEEXXX-XXEEX XXXL XXXL vo-or mans TLEEEX_IWXZELEX)_ EEX XXX (iaterosa).\\ Jo aving —_/ (2) Recording ( Auto stop ) stant command wrtng des compuatortpep i eee. no~ae Y/Y wor YY YI XX X XU X_X XMM X X Ql voor Yj win YY MX »_/ WX XXX )_ WWMM“ X_ X¥$ cy WY 0 (reterostoay\\ fo Nitog —_/ Fig.5.37 Recording at CPU control with DIRECT MODE 358

| 9097249 ooeso42 275 METOS3 TCass0AF-49]| TOSHIBA (UC/UP) HE D (8) Playback (Foree the stop command ) scantonmantene STorconmandwring _STOFcommandwaing rn | | | nomais Viwino VM Xa Xk XM po~pr Yiwunso W/MMMUN T % RW a [ay rs | a | resderte _/ (4) Playback ( Auto stop ) START command wating i | c= Address comparator flipflop es | = es aowars Viva VM Xa Xa XL SS . vo~o7 Ypwunie WYMMLN l LT CMBPBji>ha—ae. RW / \\ Fig.5.38 Playback at CPU control with DIRECT MODE 359

i] TC8830AF-50 me 9097249 0025043 101 MTOS3 TOSHIBA (UC/UP) BYE D

5.10.4 Write Cycle

At the recording, TC8830AF is check for number of connected SRAMs. Write timing is explained in following, Further, pulse width ete, refer to section 6.4 AC characteristics. Output H level by pull up resistor RW / \\ ALE r\\ Fig.5.39 Write cycle timing CEI~CEA pins select to 4 pieces SRAM. CH(1)~(4) are CGE) Dummy cycle, invalid CE(2) Writing L level to SRAM. CE(3) Reading the data of step (2). In case of connected SRAM, read out the data is L level, if not connected, the data is II level by internal pull up resister. Stops to recording when . the read out data is H level. CE(4) When the read data of step (3) is H level, valid of voice data writing to the SRAM, ALE pin of fig.6.89 means Address Latch Enable, it’s possible to expanse SRAMs up to 8Mbit, 360

mm 9097249 goeso44 048 MBTOSS TC8830AF-51 “TOSHIBA (UC/UP) BYE D-

5.11 Precautions

5.11.1 At The Both CPU Control and Manual Control. (1) Under the recording / playback, other than stop should not be issued. (2) When the ACE pin is L level,0 clear to index area of SRAM, (8) In case of use for standby function, this mode sets at recording/ playback waiting state. 5.11.2 AtThe Manual Control. (1) The recording phrase number select at sequence from low order phrase. (2)'The maximum address is auto check under the recording, if bad address at SRAMs, stop the recording, (3) In case of use for auto phrase function, not direct access of more than phrase No.16.

5.11.3 AtThe CPU Control

(1) Label index mode © The recording phrase number select at sequence from low order phrase. e The maximum address is auto check under the recording, if bad address at SRAMs, stop the recording. (2) Direct mode = = ° Don't setting the start and stop address at index area. ° Setting to stop address more than start address. (3) Other © Keeps at command processing time for data read of DIRD and ADRD command. = © Releasing DMA function, set the WR pin at H level after setting the RD pin at H level, write the NOP command into the TC8830AF. 361

| TC8830AF-52 @™ 9097249 o025045 Tay mTOS] TOSHIBA (UC/UP) - /UP) b4E D

5.12 Connection of SRAMs

The TC8830AF uses SRAMs ( Static RAMs) for the storage of voice data, Up to 4 pieces of 64K or 256Kbit SRAMs are directly connected to the TC8830AF. But it is impossible to connect together with different capacity SRAMs in capacity, Select of capacity for 64K / 256K is 256K pin. Voo (Note) | Usable access time of SRAMS tee (1) At the manual control ( LABEL INDEX MODE of CPU [ee control ) : 200n$ max, . < 4 i (2) At the CPU control ( DIRECT MODE of CPU control ) BME Zé lsieleicie + 250nS max. SSS FEEEEE S 2s max a ath, TCB830AF a EH Ve COO aati wt HELLA cH poe EAR tanne at voo F 4 b if 2 a ol a a t—| “ a a fe st ——— ties wos a eno Fig.5.40 Connection of SRAM (in case of 256K DRAM) 362

Wm 9097249 0025045 410 TOSS TC8830AF-53 || TOSHIBA (UC/UP) BYE D Fig.5.40 shows the connection with SRAM, In case of two or more SRAMs, CEI pin of TC8830AF must be connected to the CE pin of ist SRAM, the CE2 to the CE of 2nd SRAM and so on, That is, CEI~CE4 pins must be connected to the Gli pins of each SRAM respectively. Other pins for SRAM of ‘TC8830AF may be connected in parallel to every SRAM,

5.13 Clock Generator

‘TC8830AF has clock generator, ceramic resonator and capacitor are connected between XIN and XOUT pins. fusing external clock, it should be fed to XIN pin directly, (XOUT should be left open ). TC8830AF TC8830AF XIN xOUT XIN xOUT 0 open 100pF t CSB512 1 100pF P.G. {a) Using internal oscillator (b) Using external oscillator = Fig.5.41 Oscillator 363

il TC8830AF-54 mm 9097249 0025047 457 METOSS TOSHIBA (UC/UP) B4uE D

5.14 Analog Circuit

‘The TC8830AF incorporates microphone amplifier and band pass filter, Therefore, voice recording / playback system is easily composed with a microphone and an audio amplifier circuit, 5.14.1. Microphone Amplifier Part (Caution) & Aol Be careful for wiring. The signal from zs a3 e 3 microphone is so small thatit is easily 22efe5698 influenced by noise from surroundings. awe 2 oe Further, the ground of the analog part should be separated from that of the digital part on = pce. ; Oty tw Digital ground Analog ground Fig.5.42 Connection of microphone Microphone amplifier includes two slage. @Between MICIN and C1 — Gain is about 26dB @Between C2 and MICOUT ~* Gain is about 204B So, there are three ways @, @, and @+@. One is selected according to the type of microphone. C1 or MICOUT pin should be connected to ADI pin at the case of D, ®, and © +, respectively. 364

mM 9097249 0025048 793 METOS3 TC8830AF-55}| TOSHIBA (UC/UP) bYE Dp. Gv oa TTT TTT) SET Ect PO Pe

40 KH 01T|

2of LCT Pr) [Try HI Cn Lr rr ol LETTE TTT) 102 103 104 (Hz) Fig.5.43 Frequency characteristics of microphone amplifier (Between MICIN and MICOUT) Fig.5.48 Shows microphone amplifier characteristic between MICIN and MICOUT with couplings Cl and C2, = == Further, when on-chip Microphone amplifier is not used, it is possible to apply voice signal ——— directly into ADI pin, If a voice signal which is applied to ADI pin is not biased to Vref level, a coupling capacitor of about 0.1 ,-F~ 1iF should be inserted into the circuit. Microphone amplifier not operating under the others of recording waiting state and recording. in = case of use for on-chip microphone amplifier, should be a waiting time for change playback waiting == state to recording waiting state, This time is about 100ms at the case of connected 0.1 uF between Cl and C2 pins, = 365

i| TC8830AF-56 mm 9097249 0025049 b2T mTOS3 TOSHIBA (UC/UP) BHE D..

5.142 Filter Part

‘The frequency characteristic of the band pass filler which is on chip the 'TC8830AF is shown in Fig.5.44. ‘The band pass filter consists of a combination of the 1’st order high pass filter and 2'nd order low pass filter. cv “TT 0 pal TH] “CTT NHI N cool_L LLM TIN 102 103 104 (Hz) Fig.5.44 Frequency characteristics of band pass filter (Between FILIN and FILOUT ) ‘TC8830AF Vpo fuout aie loop vaol —e_] IS ae 10ka: 100 nF une 7 y= sss 3 a [[_ sp cen) 0.014F TA7368P = Digital ground ‘Analog ground Fig.5.45 Connection of audio amplifier 366

“mm 9097249 0025050 341 MMTOS3 TC8s30AF-57 || a TOSHIBA (UC/UP) BYE p-

5.14.3 Equivalent Circuit

o > o MICIN a c [ MICOUT Microphone amplifier o—1i re } is FILOUT J, : Band pass filter Fig.5.46 Equivalent circuit of analog part 367

i TC8830AF-58 mm 9097249 0025051 288 METOS3 TOSHIBA (UC/UP) B4E D 6. ELECTRICAL CHARACTERISTICS

6.1 Absolute Maximum Rating

6.2 Recommended Operating Conditions

soppy votape wee |v Vow Input voltage 0 ~ Voo v Vour | Output voltage 0 ~ Yoo v ex [ostintenenn [se | o | 368

mm 9097249 0025052 1b4 mMTOS3 TC8830AF-59 i TOSHIBA (UC/UP) BYE D-

6.3 DC Characteristics (Vpp = 5V + 10%, Ta = 25°C)

[Boe | re] conor [eo] faux Operating frequency 1 Manual control or LABEL Operating frequency 2 DIRECTMODE atcPUcontrol_ | 250 | 512 | 1000 Input high current 1 Pe] (P0~P3, WR, RD, PHO~PH3) Viw=Vop »cPuM SL Pofe bel [soiree ——fieceacswemer—[—-=fat ce or [esting 2 esate [a [vcr stoning rem] ee — [6 Joneses vesesv ee a ee ee Fe fetta Seen foresees ffs Pa [earliest Frappr [vet a = Precautions: 1) Each TYP, value is measured under VDD =5.0V, Ta= 26°C. SSS 2)MIN. MAX. valuos are dofined by their absolute values, = 3) Supply current measured by external oscillator of 512k! lz. 369

i TC8830AF-60 mm 9097249 0025053 O50 mTOS] TOSHIBA (UC/UP) b4E D- 6.4 AC Characteristics (Vpp = 5V, Ta = 25°C, CL. = 50pF )

6.4.1 Data Write

(1) Except data write after the DI'WR command ( command write ) tos _ [Data set up time o | - [| - tox _ [Data hold up time 2 | — | — ce , ‘wae wR Via — (IN) vu — ' te ton PO~P3 Vit — ww (a Input level Comparison level © Vin = 2.6V ° Vin = 2.4V ° Vn = 0.6V e Va = 08V * VoH= 2.4V ° Voi = 0.8V (2) Data write after the DITWR command tows _|Data write set up time ° towH. Data write hold time 500+ tH ‘ty = Data hold time of SRAM. __twae WR Vin — (IN) Vi — tows town | jew | PO~P3 Vin — a f vau) 370

mm 9097249 0025054 T97 METOS3 TC8830AF-61 i TOSHIBA (UC/UP) buE D<

64.2 DataRead

(1) Status read 200 [too _ [Output disable time 200 RD Vin — (IN) vu — tace top PO~P3 = VoH— . (2) Address read [tao [Readaisabletime | vortex | = = Tee |__| == RD Vin — (iN) vi — tace top tacc top SS

123 Keg =

PO~P3 = Vo — (8) Data read after the DTRD command = | trop _| Data read RD pulse width 3+tac a tac = Access time of SRAM [<—_tROP_, RD Vi — (IN) vit — trac Ito Po~P3 = Von— 371

i] TC8830AF-62 Mm 9097249 0025055 923 METOS3 TOSHIBA (UC/UP) BYE D

6.4.3 Write Cycle of Start Address and Stop Address

MH 097249 0025056 BbT MTOSS TC8s30AF-63 || TOSHIBA (UC/UP) buE D

6.4.4 Read Cycle of Start Address and Stop Address

(at the Manual contro! and LABEL INDEX MODE in the CPU control ) | twas _[Memoryreadcommandsetuptime | — | avfax | — | twan _|Memoryreadcommandholdtime | — | t/arcix | — ‘| tmac__|Memory read write cycle anak | — | | tcesa | Memory data set up time = [tcen _ [Memory data hold time fo {-ft- | ture cep | | * = Vor CET Vo. — 5 y } ao~ae WRK EXD Ce = nw yOu | Vou — : Ty + oor WI NOY NOY WN J teesa SH - i [ten = tcep : : tee —— = Memory access time should be tcep - tcesa or less. 373

il TC8830AF-64 mM 9097249 0025057 ?Tb METOS] TOSH uP) ep IBA (UC/UP) BYE D

6.4.5 Voice Data Write Cycle

[ae Poe | ie [oe | High order address hold time 1847 feux | 2807 (CLK Livery value is typ, value A0~A4 High order address (A15~A19) i Low order address (AO~Ad) woo) OKO POO RAV —s CEI~CES than iF as — eS a | im ALE J twe 374

mm 9097249 0025058 b32 MTOS3 TC8830AF-65 | TOSHIBA (UC/UP) b4E D

6.4.6 Voice Data Read Cycle

rae tcax | 2567 sri] | tar _ [Read address set up time aricux | asfcuk Ar iCLK Evory value is typ. value A0~A4 {High order address (A15~A19) Low order address (AO~A4) Xf _ I m fe | Ci~tea tan 4 tar ind = ALE C_! SI Do~D7 Oo Je te — 375

i] TC8830AF-66 @™ 90972459 0025059 579 mETOS3 TOSHIBA (UC/UP) buE D

6.4.7 DMA Function

twrt__ | Write to read disable time [is _| tawt__ [Read to write disable time [= | [ton |eeaeoytine vo twee i trwt wm {| YY Ds - Po Po~Ps ZN NOP ORKRITZZLIL tow} |. DO~D7 esa w eee wwe ennn Hiz Cei~ tea RW oo-+-- +--+ 376

mm 9097249 Go2s50b0 290 METOS3 TC8830AF-67 il TOSHIBA (UC/UP) BYE D~

6.5 Characteristics of Analog Circuit

(Unless otherwise specified : VSS1 = VSS2 = OV, VDD = 5V, Ta = 25°C, fin=1 kHz)

6.5.1 Microphone Amplifier

6.5.2 Band Pass Filter

Yuu = voltage FILIN, Vin= 1.0Vp-, Pass band gain weeere dB —FILOUT | Output load = 100kQ,, 30pPr Total harmonic FILIN THO Vin = 1.0Vp-, - % distortion ~rour | "PP R Output FILOUT ka ‘our impedance 377

i] TC8830AF-68 mm 9097249 00250b1 127 METOS3 TOSHIBA (UC/UP) =—s—s—S*~*«HE, OD =.

6.5.3 Audio tn

Vw |Range of input ADI a |v ™ |voltage . ore

6.5.4 Audio Out

Fa] — wa [ rm] san [ome [re R Output ka ‘our | impedance 378

“ml 9097249 O0250b2 O63 MNTOS3 TC8830AF-69 i 7. OUTLINE DRAWINGS

67 PIN FLAT PACKAGE

(67-4-85) Unit in mm | tr 0.3540, HOC HHA AA RA RAR A RA RAR AR AA ___ 54 33 ie rT = Pate corr tI} ol ¢ 4 | Fa 8 = ole L. ~ nS = 1 2 HARARE BREWER SO) IUUUUIUUUUCUIUOLU 2.0TYP | 20.020.2 24.120.5 > =] ors 8) oy f heron 2.25MAX 4A NNOORAAAARAANAAANAOD A, | | t jo 1.3520.3 otstot t 379

il TC8830AF-70 __-*™ 097249 0025063 TTT mTOS3 TOSHIBA (UC/UP) GUE > 8. APPLICATION CIRCUIT MANUAL CONTROL TYPE IA} |S ut az ot ct otd dd d yyy he 100pF * 0.1 ,F capacitor is needed S12kHz each SRAM. * Other pit f TCBB30AF CSCC E EE HSS S 2 = a [sslclals i Ack D Ne so) TC8830AF s ‘i fenkihers a Ms oor ee mm ee REST MO Tr t]2]3]4 hihzhis}ias) f, soo] PREP TT Be J Ton + it oor eSEESEn ia aoe (\\*., LSPS EEE TCSS257 88855 )s Tres TBs +5V ° ji6] iia i <n | ap =opF 380

Product Information

TC8830AF specifications and overview.

Summary

The TC8830AF is a single chip CMOS LSI for voice recording/ playback using the ADM(Adaptive Delta Modulation )

Description

The TC8830AF is a single chip CMOS LSI for voice recording/ playback using the ADM(Adaptive Delta Modulation )

Source title TC8830AF Datasheet(PDF) - Toshiba Semiconductor

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