TC8521AP TOSHIBA | Alldatasheet
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TC8521AP, TC8521AM (Real Time Clock II ) 1. GENERAL DESCRIPTION The TC8521AP/AM is an 1-chip C-MOS LSI to be used for __ — the real time clock fabricated as the peripheral IC of the — | microcomputer. Ge ett yt Rr The TC8521AP/AM has the crystal oscillation circuit of } Wag a wry } [ue 32768Hz, the counter for clock and calendar, the alarm OY YY ee function, and the 26 x 4-bit RAM. ve Since the package is of 18-pin DIP, 20-pin SOP and the DIP18-P-300-2.54A battery back-up is possible, the time counting system provided with the non-volatile RAM can be fabricated with the crystal and the battery. 2. FEATURES Y ALAC “ CO Low power dissipation realized by Si-gate CMOS technology $1020-P-300-1.27 ©) Clock function (hr, min, sec, date, day of week, year and Fen neta Can my Set Gate day of week [wno [vo [ PRnane leap year) Auto-calendar Ps . p22) Tt cs O Clock system of 24-hour or 12-hour (AM/PM) is selectable. 3 GL LADS (1 +£80-sec correction function, Alarm signal, or pulse of 16Hz = |} sy] 1. ar or 1Hzcan be output. po 6 6) A poo? Pc O Built-in 26x 4-bit RAM eee es eee a a ee O Directly connectable with CPU bus. | io [| Gc fT Gnp Pinca wr O 4bit bidirectional data bus p21) Tio To p32) Tio ST O 4bit address input | 15 (14) [io [ps O Capable of battery backup | tes) | of -ALaRM | poiz Tc po igce) ft xin } i917) | oT xouT [20g Pv vce | note) (1)~(18) are PIN number of DIP. 98091068A2 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and t0 avoid situations in which & malfunction of failure of 2 TOSHIBA. product could cause lost of human life, bodily injury or damage to property. In. developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. @ The products described in this document are subject to the foreign exchange and foreign trade laws. © The information contained herein is presented only as a, guide for the applications of ur products. No responsiblity is assumed by, TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted By implication or otherwise under any intelectual property or other rights of TOSHIBA CORPORATION or others @ The information contained herein is subject to change without notice. 1999-03-10 1/25
- TC8521AP/AM and APPLICATION SYSTEM
3.1 INTERNAL BLOCK DIAGRAM
ALARM REGISTER ee “ALARM HOLD COMPARATOR — 4 26 x4 BIT TIMER | RAM ADJUST r 7 \\ CARRY HOLD : ADDRESS : / Bus DATA BUS READ/WRITE CONTROL cs -cs -RD -WR- AO0~A3 DO~D3 ADJ The comparator compares the contents of the timer and the alarm register to output the coincident signal. The signal ORed with the output of the comparator and 16Hz or 1Hz signal which is generated from the divider is output to the alarm terminal through the ALARM SELECT circuit. Each of these three signals can select the output ENABLE or the output DISABLE independently. The 1S CARRY HOLD circuit holds one second carry signal generated from the divider during the TIMER DISABLE for one time, and output it to the TIMER after the TIMER ENABLE state is selected. The ADJUST CARRY HOLD circuit also holds the carry signal made by the ADJUST. 1999-03-10 2/25
3.2 SYSTEM CONFIGURATION
The RTC can be backed up by the battery. LE —_— > Power DO~D3R 7 ons vec Supply xt ~ XIN Oo A0~A3 AO~A3 ¢ end Pad ° D2 N a -WR Go ~ 8 7 ee ee -CS u t Bb Power Down cs ADJUST et Detection FIG.3.2 SYSTEM CONFIGURATION Even ifthe input terminal to be interfaced with the CPU and the data bus come into the state of floating, this IC does not operate abnormally when the input is set to ”0” (Low level). * Output stabling resistance (about 250k) is built in oscillation circuit. * CG=10pF to 30pF * CD=10pF to 30pF 1999-03-10 3/25
- PIN DESCRIPTION note) (1)~(18) are PIN number of DIP. | no. | PIN NAME FUNCTION When -CS is “0” and CS is "1", RTC is selected making read and write 1 (1) -cs operations possible. -CS is connected to CPU to be used. CS is connected to POWER DOWN 2 (2) | cs DETECTION CIRCUIT of peripheral circuit power supply to be used. Second adjustment is made by this signal. Set this signal at “High” 3 (3) | ADjusT level when second indication is 0 to 29, and the indication becomes 0. When the second indication is 30 to 59, the minute indication is carried up and the second indication is made 0. } 4 ao ft | 5_(5) ee Address input for selecting RTC register. Connected to address bus of 5 (far [1 Jorusiee a@ftas [| 9 (8) Set this terminal at “0” during the state the chip is selected, and CPU can read the contents of RTC register. 10 (9) | GND ——s|_- G_| Ground of IC. Connected to ground of system. 11(10) | -wr Set this terminal at “0” during the chip is selected, and CPU can write data into RTC register. wa) | oo | 0 13 (12) Bidirectional data bus (4 bits) for exchanging the data to and from cPUside. Es ee 16(15) | -ALARM Alarm signal and clock pulse of 16Hz and 1Hz are output. Open drain output. 18 (16) [xin ft Crystal oscillator connecting terminal. 19(17) | xouT | o | 20 (18) +5V of IC plus power supply is supplied. 1999-03-10 4/25
- FUNCTIONAL SPECIFICATION
5.1 FUNCTIONAL DESCRIPTION
5.1.1 DESCRIPTION of ADDRESS
PAGE 0 (TIMER) DATA BUS CONTENTS 1OHEXA- REMARKS fofofofo[ o [sses [asec [2secs [isec |tsecdigit | Foftofotiaft 1 | -¢1 [aosecs [20secs [10 secs | 10-sec digit fofo}{itof 2 [aemins [4 mins [2 mins [1 min [i-mindigit | fofofitaf 3 [ - [4omins [20 mins [10 mins [10-mindigit | Fo{rfotof 4 [ers [ans [ahs [ihr [thrdigit | 1 5 20 hrs 10 hrs ae Fo{+{itof 6 To - fT wa Twi] wo [Week digit 2) Potafrtat 7 [es days [4 days [2 days | 1 day [1-day digit Jr1tofotoft s | - [= [2odays 10-day digit [1 {o}o}a] 9 [8 months | 4 months | 2 months | 1 month [1-monthdigit | Pr1fotitof a To - [= [= fro months {10-month digit Prtoltitit 8 [8 years [4 years | 2 years | 1 year |1-yeardigit [1 {r1}fotol c [aoyears [40 years [20 years [10 years | 10-yeardigit 1 TIMER ALARM PAO . " Pr1trtrtoft ec [rests [rest2 [rest1 [testo | TesTregister (*4) 1 1Hz 16Hz TIMER ALARM + ” Py ety ye | ENABLE JENABLE | RESET RESET RESET register (*5) 1999-03-10 5/25
PAGE 1 (ALARM) TOHEXA- REMARKS Fofofofof o fT - To - To - fF -en To | pofofofif a1 [| - To - fo - fT - To Jotofs}tof 2 [emins [mins | 2 mins [1 min [atarmi-mingigit | Jofofitif 3 [ - [ao mins [20 mins [10 mins [auarm to-minaigit_| Fo{rto}fo] 4 [ans [ans |[2ns | thr [atarmionraigit | 5 20 hrs 10 hrs ee eT Te | Lenny ['P* asmsomae |
2 Ge a
("2) potafrtat 7 [edays [4 days | 2 days | 1day [atarmidayaigit | }i1foftofo{ se [ - [ - [aodays [10 days [avarm 10-day aigit_| ee ee ee eee Pitofrtof a fo - fT - fo - J 242 [ranrseteceniecre | Prtofrtaf oe fot fur JT v0 eapyearaisiner | Pi1tafofof « [| - TT - [| - fT - To TIMER ALARM PAO — | PAGE register (*3) ENABLE | ENABLE Pi tafrtolt ec rests [rest2 [rests [testo [restregistercay | 174 1 Fo faHz 16Hz TIMER ALARM | acces register (45) ENABLE _|ENABLE | RESET RESET register PAGE 3, 4 (RAM) PAGE address 10 and 11 are RAMs of 13 X4 bits Notes: O Address 01¢ to Dig Read and write are enabled. Cl Address E1¢ to Fig Only write is enabled. Ci Address Dig to F1g Unrelated to MODE. 4999-03-10 6/25
(#1) ”—" is neglected at writing and turned into ”0” at reading. (*2) Day of week is a numeral from 0 to 6. (*3) PAGE register TIMER ENABLE Timer starts at ”1”, and stops counting the time follows second at”0” ALARMENABLE ALARMENABLE at”1”. Signals of 16Hz and 1Hz are output even at 0” without any relation to ENABLE and DISABLE states of alarm. PA1 or PAO bit of PAGE register is selected as shown in the table below. Pa Toop | eros | o | o | PaGEO _ setting and reading of time. Fo [1 | pacer | Setting and reading of ALARM, 12-hr/24-hr and leap year. | 1 | 0 | PaGe2 [Writing and reading of RAM. Li [| 1 | pace3 [Writing and reading of RAM. (*4) TEST register Since this is the register for high-speed test at shipping, set all the contents of the register at ”0”. As no normal operation can be expected when the data other than ”0” is input, care must be taken. (*5) RESET register DO="1” Alarm register is reset. D1="1” Timer is reset D2="0" 16Hz clock is output to ALARM. D3="0” 1Hz clock is output to ALARM. (*6) 24 hour select bit When D0="1”, 24-hr system, and when D0=”0”, 12-hr system is selected. In 12 hour, when D1 of 10-hr digit =”1”, PM, and when D1 =”0”, AM is selected 1999-03-10 7/25
(#7) Leap year digit When both U1 and U0 are 0”, leap year is selected. The year carry is made simultaneously with that of 1-year digit to this leap year digit U1, U0. At setting, caution must be exercised for inputting the correct years elapsed after the leap year. If this year is the year after the "leap year”, input U1=”0” and U0=”"1”, and if this year is the year two years after the "leap year”, input U1=”1” and U0="0”. At the time three years after the "leap year”, input ”1” both to U1 and U0. This is used to facilitate the setting of a leap year, using the fact that in general, a leap year occurs once every four years. However, note that a leap year is not necessarily once every four years. The year 2000 is a leap year but the years 1900 and 2100 are not. Thus, if the user sets the incorrect data in the leap year digit, operation is not guaranteed. (#8) Year 2000 This product only has lower two digits to set the year. Therefore, the year after the year 99 is the year 00. In the user system where the product is used, the user must control the digits for hundred years and thousand years. If the user system uses four-digit years, take care during changeover from the year 99 to 00 that the system does not revert to the previous century; for example, from 1999 to 1900 instead of 2000. 1999-03-10 8/25
5.2 APPLICATION METHOD
5.2.1 DESCRIPTION of CS and -CS
When the terminals of CS and -CS are respectively ”1” and ”0”, the following circumstances are turned out. * WR and -RD signals from outside become ENABLE. * Ifthe CS terminal is at ”0”. All the inputs become disabled, and even if the input terminal is in the floating state, the through current does not flow. However, the input voltage of the CS terminal is required to be at VCC level or GND level. * The output of the power-down detection circuit is usually connected to the CS terminal. By means of connecting this circuit, the CS terminal is fixed at low level, the erroneous operation of the RTC is prevented and the data is maintained undestroyed. cs -CS -WR -RD The other input terminal 1999-03-10 9/25
5.2.2 READING of DATA
Caution must be exercised because the erroneous data is possibly be read if the carry signal is input during the series of reading operations. The data is correctly read through the procedures below. 1. READ TWICE Read the timer data twice and compare the contents to confirm the carry. If the contents are found different to each other during the data comparison, read the data twice again because this means that the carry has been made. START Read the timer data (1st) Read the timer data (2nd) mo 1999-03-10 10/25
- DISABLE THE TIMER When ”0” is written to D8 of the address "D”, the timer is made DISABLE, the carry is inhibited and the erroneous operation can be prevented by the CLOCK HOLD circuit. The CLOCK HOLD circuit holds one second carry from the divider preceding to second counter during the DISABLE state, and the held carry will regenerate after the timer is made ENABLE so as to adjust the time. However, when the ENABLE state of the timer continues over one second, the timer becomes delayed. At this time, care must be taken because the system power supply sometimes goes down during the DISABLE state of the timer (the timer is left stopped and the time indication begins to lose). Therefore, when the power-down is detected during the timer DISABLE state, it is necessary to set CS to 0” after restoring the timer ENABLE state. START Read the timer This period is within data one second. TT 55-05-10 11705
- USE 1HZ OUTPUT OF ALARM Use 1Hz signal which is output from the ALARM terminal to read the data at its leading edge. START 1Hz Enable (16Hz disable) (Alarm disable) O No YES O YES Write the timer This period is within data 0.5 second. 1999-03-10 12/25
5.2.3, WRITING of DATA The expected data can not be written if the carry signal is input during the series of writing operations. The data is correctly written through the procedures below. 1, RESET THE DIVIDER The 15-stage divider for generating 1Hz signal from 32.768KHzis built in the RTC. When this divider is reset, the timer carry is not coming out for a second and during which time, the data can be written safely. START Timer reset (Reset the divider) D1=1inaddress F This period is within data 0.5 second. 2. DISABLE THE TIMER The same procedure as that of "Reading the data”. START Write the timer data 1999-03-10 13/25
- USE 1Hz OUTPUT OF ALARM The same procedure as that of "Reading the data”. START 1Hz Enable (16Hz disable) (Alarm disable) O No. Yes O ono yes. Write the timer This period is within data 0.5 second. In the RTC, the 12-hr or the 24-hr system can be selected as the time digit. This selection is simultaneously made at the timer data writing. The 12-hr system is turned out when DO=”0” in the address ”A”, AM when D1="1”. The 24-hr system is turned out when DO="1”. The data such as ”A” and ”B” (hexadecimal) can be written as the contents of the timer data, however, if the data other than the data of 0 to 9 is written, the correct timer operation can not be guaranteed. 1999-03-10 14/25
5.2.4 DESCRIPTION of ALARM
When the contents of the timer and the alarm register coincide in the four items, minute, hour, day of week and day in the ALARM ENABLE state, ”0” is output at the -ALARM. On this coincidence condition, the items not written at all after the alarm reset are considered to be coincident regardless of the timer contents. Therefore, when the alarm is required to be output at the same time every day, it is enough only to set. the hour and the minute after the alarm reset. When the alarm reset is made, all the contents of the alarm register are cleared to ”0”. However, when ”0” is required to be compared (when ”0” is necessary to be individually set at the digits of hour and the minute for example at setting just noon), be sure to write ”0”. Caution must be paid for the alarm reset, because when the reset is made in the ALARM ENABLE state, all the items become don’t care and the alarm is output until the alarm is set. Therefore, alarm reset is necessary to be made after the alarm DISABLE is performed. ALARM ENABLE ALARM ON - - 1Hz ENABLE 16Hz ENABLE “ALARM 1Hz, ON =p 16Hz, ON 1999-03-10 15/25
- ELECTRICAL CHARACTERISTICS
6.1 ABSOLUTE MAXIMUM RATINGS (Note 1)
PARAMETER SYMBOL RATINGS UNIT Supply Voltage =05 ~ +7.0 Input Voltage -0.5 ~ VeC+05 Operating T -40 ~ +85 °c Temperature OPR * Storage Temperature -65 ~ +125 Note1) The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. Note2) The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified AC and DC values etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to.
6.2 DC CHARACTERISTICS (VCC =5V + 10%, Ta = -40to +85°C)
PARAMETER SYMBOL CONDITIONS [In| Max. | UNIT High Level Input Voltage XIN, ADJUST excluded. VCC +0.3 Low Level Input Voltage XIN, ADJUST excluded. | -o3 | os | v | High Level Input Voltage ADJUST only VCC +0.3 Low Level Input Voltage ADIUST only | -o3 | os | v | High Level Output Current VOH = vec -o.41V] | | 0s | ma | Low Level Output Current VoL=0.41V) | 2 | | ma | Input Leak Current VIH=0t0 vec Consumption Current at BACK UP fo =32.786KH2 VCC =2.0V | | cs [oa Operating Consumption | H: Current lec2 RD, WR cycle 100KHz vA Operating Minimum Voltage . _ 959, of Timer Vemin | Ta=25°C v (VCC = 3V, Ta = -40 to + 85°C) PARAMETER YMBOL CONDITION: STANDARD VALE UNIT ARAN . a [w. Tmax. | High Level Output Current von=vec-oam | |= 0.3 | ma | Low Level Output Current VoL=0.41V) ee eee Operating Consumption \\ RD, WR cycle 100KHz | co na | icc2 Current RD,wegcesxKHe | | a5 | va | 1999-03-10 16/25
6.3 AC CHARACTERISTICS
(VCC =5V 410%, Ta= -40to + 85°C) STANDARD VALUE PARAMETER SYMBOL CONDITIONS [_min. | _Max. _| UNIT (VCC = 3V, Ta= -40 to +85°C) PARAMETER SYMBOL CONDITIONS [ min. | max._| UNIT psieseuptine | tw | | wo | | READ TIMING (VCC =5V 410%, Ta= -40to + 85°C) PARAMETER SYMBOL CONDITIONS [ min. | max._| UNIT (VCC = 3V, Ta= -40 to + 85°C) STANDARD VALUE PARAMETER SYMBOL CONDITIONS [_min. | _Max. _| UNIT 1999-03-10 17/25
6.4 TIMING CHART
6.4.1 WRITE OPERATION (CS = "H”)
-cS —\\ [.——— twa A0~A3 WD DO~D3 faw = tow ——>| -WR 6.4.2. READ OPERATION (CS = "H”) -CS ee \\ ee I< tra A0~A3 tDH DO~D3 tAR <— tro -RD
6.4.3 AC TEST WAVEFORM
A\\ Point A\\ 0.4v 0.8V 0.8V 1999-03-10 18/25
Characteristic of Consumption Current at BACK UP (Cg =20pF, Cp =30pF, Ta = 25°C) v v a P=] U c ° by fl f © Range y fluctuation o: product. . \\ c o U c ° 10 . . . . c ie) Supply Voltage Vcc[V] 1999-03-10 19/25
Supply Voltage Dependence of Oscillation Frequency (Cp =30pF, Ta = 25°C) a a Ww NX v fay Range by fluctuation of 5 [pF product \\ [pF v ov 10 [pF] o uo = 30 [pF] an 30 ° ° ° * External Cg fe} -50 Supply Voltage Vcc [V] 1999-03-10 20/25
Temperature Characteristic of Oscillation Frequency (External Capacitance : Cg = 20pF, Cp = 30pF, Vcc =5V) a a _ Range by fluctuation of a product. NX v o o fa) v o ov o rs -240 -40 -20 0 20 40 60 80 100 120 Temperature Ta [°C] 1999-03-10 21/25
Temperature Characteristic of Oscillation Frequency (External Capacitance Cg = 20pF, Cp = 30pF , Vcc =2V) —_— Range by fluctuation of product < 40 VY vu ao x iv) o ie) -220 ° ° . . . ° . -240 -40 -20 O 20 40 60 80 100 120 Temperature Ta [°C] 1999-03-10 22/25
Temperature Characteristic of Consumption Current (Cg =20pF, Cp = 30pF) KS v - Range by fluctuation of a prod uct ™~ a Vv o ” 20h o
3 Vec=5V
Y \\ 2 10} + ° a ° Vec=3V ¥ nH Vee = 2V\\2 : 0 a - -40 -20 0 20 40 60 80 100 Temperature Ta [°C] 1999-03-10 23/25
- PACKAGE DIMENSION DIP18-P-300-2.54A Unit : mm we Bomonoon e [ 3 sf | . ry 22.5MAX 10.95+0.1 i “ WE is |_i 3 ——.T_ a
SOP20-P-300-1.27 Unit : mm 20 1 HOooOaeaaaaaAgD AA AA A A A AA Pe | a] My] E | wl oN @ tT oy WW oo ooo oS HORRHAREEE “I 1 10 0.685TYP 0.43+0.1 re lhesso. ipo 13.3MAX 12.810.2 a 3 =. ~3 ere oF ryr to 70.1] ad o 0,810.2 note) SOP20-P-300 is capable of solder dip and Near infrared mounting. (See TOSHIBA Package Manual (Page 69). However, we don’t guarantee in case of TC8521AM. PACKAGE OVERALL HEATING METHOD. OCALIZED HEATING METHOD number of leads mm) diepadsize |_ dip J infared | topand bottom heating Iron_| heater © : Mounting is capable If you have any question, we will appreciate. 1999-03-10 25/25