TC850ILW

TC850 MICROCHIP | Alldatasheet

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Technical content

© 2006 Microchip Technology Inc. DS21479C-page 1 TC850 Features:

• 15-bit Resolution Plus Sign Bit
• Up to 40 Conversions per Second
• Integrating ADC Technique: - Monotonic - High Noise Immunity - Auto-Zeroed Amplifiers Eliminate Offset Trimming
• Wide Dynamic Range: 96 dB
• Low Input Bias Current: 30 pA
• Low Input Noise: 30 μVP-P
• Sensitivity: 100 μV
• Flexible Operational Control
• Continuous or On Demand Conversions
• Data Valid Output
• Bus Compatible, 3-State Data Outputs: - 8-Bit Data Bus - Simple μP Interface - Two Chip Enables - Read ADC Result Like Memory
• ± 5V Power Supply Operation: 20 mΩ
• 40-Pin Dual-in-Line or 44-Pin PLCC Packages Applications:
• Precision Analog Signal Processor
• Precision Sensor Interface
• High Accuracy DC Measurements Device Selection Table Package Types Part Number Package Temperature Range TC850CPL 40-Pin PDIP 0°C to +70°C TC850IJL 40-Pin CERDIP -25°C to +85°C TC850CLW 44-Pin PLCC 0°C to +70°C TC850ILW 44-Pin PLCC -25°C to +85°C TC850CPL TC850IJL ANALOG COMMON CBUFB BUFFER INTIN INTOUT COMP 40-Pin PDIP/CERDIP DGND CINTA CBUFA CINTB IN- IN+ REF- TEST OSC2 OSC1 BUSY DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 CS CE WR RD CONT/DEMAND OVR/POL L/H VSS VDD REF1+ REF2+ CREF1+ CREF2+ CREF1- CREF2- NC = No Internal Connection 44-Pin PLCC COMP 18 19 20 21 23 24 43 42 41 40 25 26 27 28 TC850CLW TC850ILW NC NC NC TEST DGND OSC2 OSC1 DB0 DB1 DB2 DB3 DB4 NC DB5 DB6 DB7 CS BUFFER BUSY CE WR RD CONT/DEMAND REF- VDD REF1+ CREF1+ CREF1- IN- IN+ REF2+ CREF2+ CREF2- ANALOG COMMON CBUFB CINTA CBUFA CINTB INTIN INTOUT VSS OVR/POL L/H 15-Bit, Fast Integrating CMOS A/D Converter

© 2006 Microchip Technology Inc. General Description: The TC850 is a monolithic CMOS A/D converter (ADC) with resolution of 15-bits plus sign. It combines a chopper-stabilized buffer and integrator with a unique multiple-slope integration technique that increases conversion speed. The result is 16 times improvement in speed over previous 15-bit, monolithic integrating ADCs (from 2.5 conversions per second up to 40 per second). Faster conversion speed is especially welcome in systems with human interface, such as digital scales. The TC850 incorporates an ADC and a μP-compatible digital interface. Only a voltage reference and a few, noncritical, passive components are required to form a complete 15-bit plus sign ADC. CMOS processing provides the TC850 with high-impedance, differential inputs. Input bias current is typically only 30 pA, permit- ting direct interface to sensors. Input sensitivity of 100 μV per Least Significant bit (LSb) eliminates the need for precision external amplifiers. The internal amplifiers are auto-zeroed, ensuring a zero digital output, with 0V analog input. Zero adjustment potentiometers or calibrations are not required. The TC850 outputs data on an 8-bit, 3-state bus. Digital inputs are CMOS compatible while outputs are TTL/ CMOS compatible. Chip-enable and byte-select inputs, combined with an end-of-conversion output, ensures easy interfacing to a wide variety of microprocessors. Conversions can be performed continuously or on command. In Continuous mode, data is read as three consecutive bytes and manipulation of address lines is not required. Operating from ±5V supplies, the TC850 dissipates only 20 mΩ. The TC850 is packaged in a 40-pin plastic or ceramic dual-in-line package (DIPs) and in a 44-pin plastic leaded chip carrier (PLCC), surface-mount package. Functional Block Diagram BUF INT IN Buffer Pinout of 40-Pin Package Integrator Comparator DB7 TC850 REF- RINT CINT INT OUT IN+ 6-Bit Up/Down Counter REF2+ REF1+ DB0 9-Bit Up/Down Counter . . . . WR CONT/ DEMAND Analog Mux IN- COMMON +5V –5V OSC2 L/H OVR/ POL RD CS CE OSC1 A/D Control Sequencer Data Latch Octal 2-Input Mux 3-State Data Bus Clock Oscillator Bus Interface Decode Logic

© 2006 Microchip Technology Inc. DS21479C-page 3 TC850 1.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings* Voltage Reference Input: + 0.3V to GND – 0.3V Ambient Operating Temperature Range Package Power Dissipation (TA ≤ 70°C) *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. TABLE 1-1: TC850 ELECTRICAL SPECIFICATIONS Electrical Characteristics: VS = ±5V; FCLK = 61.44kHz, VFS = 3.2768V, TA = 25°C, Figure 1-1, unless otherwise specified. Symbol Parameter Min Typ Max Unit Test Conditions Zero Scale Error ±0.25 ±0.5 LSB VIN = 0V End Point Linearity Error LSB -VFS ≤ VIN ≤ +VFS Differential Nonlinearity ±0.1 ±0.5 LSB IIN Input Leakage Current pA VIN = 0V, TA = 25°C 1.1 nA -25° ≤ TA ≤ +85°C VCMR Common Mode Voltage Range VSS + 1.5 VSS – 1.5 V Over Operating Temperature Range CMRR Common Mode Rejection Ratio dB VIN = 0V, VCM = ±1V Full Scale Gain Temperature Coefficient ppm/°C External Ref. Temperature Coefficient = 0 ppm/°C 0°C ≤ TA ≤ +70°C Zero Scale Error Temperature Coefficient 0.3 μV/°C VIN = 0V 0°C ≤ TA ≤ +70°C Full Scale Magnitude Symmetry Error 0.5 LSB VIN = ±3.275V eN Input Noise μVP-P Not Exceeded 95% of Time IS+ Positive Supply Current 3.5 mA IS– Negative Supply Current 3.5 mA VOH Output High Voltage 3.5 4.9 V IO = 500 μA VOL Output Low Voltage 0.15 0.4 V IO = 1.6 mA IOP Output Leakage Current 0.1 μA Pins 8 -15, High-impedance State VIH Input High Voltage 3.5 2.3 V Note 3 VIL Input Low Voltage 2.1 V Note 3 IPU Input Pull-Up Current μA Pins 2, 3, 4, 6, 7; VIN = 0V IPD Input Pull-Down Current μA Pins 1, 5; VIN = 5V IOSC Oscillator Output Current 140 μA Pin 18, VOUT = 2.5V Note Demand mode, CONT/DEMAND = LOW. Figure 8-2 timing diagram. CL = 100 pF. Continuous mode, CONT/DEMAND = HIGH. Figure 8-4 timing diagram. Digital inputs have CMOS logic levels and internal pull-up/pull-down resistors. For TTL compatibility, external pull-up resistors to VDD are recommended.

© 2006 Microchip Technology Inc. CIN Input Capacitance pF Pins 1 - 7, 17 COUT Output Capacitance pF Pins 8 -15, High-impedance State TCE Chip-Enable Access Time 230 450 nsec CS or CE, RD = LOW (Note 1) TRE Read-Enable Access Time 190 450 nsec CS = HIGH, CE = LOW, (Note 1) TDHC Data Hold From CS or CE 250 450 nsec RD = LOW, (Note 1) TDHR Data Hold From RD 210 450 nsec CS = HIGH, CE = LOW, (Note 1) TOP OVR/POL Data Access Time 140 300 nsec CS = HIGH, CE = LOW, RD = LOW, (Note 1) TLH Low/High Byte Access Time 140 300 nsec CS = HIGH, CE = LOW, RD = LOW, (Note 1) Clock Setup Time 100 nsec Positive or Negative Pulse Width TWRE RD Minimum Pulse Width 450 230 nsec CS = HIGH, CE = LOW, (Note 2) TWRD RD Minimum Delay Time 150 nsec CS = HIGH, CE = LOW, (Note 2) TWWD WR Minimum Pulse Width nsec CS = HIGH, CE = LOW, (Note 1) TABLE 1-1: TC850 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: VS = ±5V; FCLK = 61.44kHz, VFS = 3.2768V, TA = 25°C, Figure 1-1, unless otherwise specified. Symbol Parameter Min Typ Max Unit Test Conditions Note Demand mode, CONT/DEMAND = LOW. Figure 8-2 timing diagram. CL = 100 pF. Continuous mode, CONT/DEMAND = HIGH. Figure 8-4 timing diagram. Digital inputs have CMOS logic levels and internal pull-up/pull-down resistors. For TTL compatibility, external pull-up resistors to VDD are recommended.

© 2006 Microchip Technology Inc. DS21479C-page 5 TC850 FIGURE 1-1: Standard Test Circuit Configuration VDD VSS TC850 0.01 μF Input +1.6384V +0.0256V 100 MΩ

120 MkW

1 μF* 1 μF* 0.1 μF 0.1 μF 0.1 μF 0.1 μF 0.1 μF 0.1 μF BUFFER OSC1 OSC2 INTIN INTOUT CINTB CBUFA CBUFB CINTA RINT CINT COMP TEST NC 61.44 kHz -5V +5V DGND NOTES: Unless otherwise specified, all 0.1 μF capacitors are film dielectric. Ceramic capacitors are not recommended. NC = No Connection *Polypropylene capacitors. ** 100 pF Mica capacitors. DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 BUSY CS CE WR RD CONT/DEMAND OVR/POL L/H IN- IN+ REF- ANALOG COMMON REF1+ REF2+ CREF1+ CREF1- CREF2- CREF2+

© 2006 Microchip Technology Inc. 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table . TABLE 2-1: PIN FUNCTION TABLE Pin Number (40-Pin PDIP/CERDIP) Pin Number (44-Pin PLCC) Symbol

Description

Chip Select, active HIGH. Logically ANDed, with CE to enable read and write inputs (Note 1). CE Chip enable, active LOW (Note 2). WR Write input, active LOW. When chip is selected (CS = HIGH and CE = LOW) and in Demand mode (CONT/DEMAND = LOW), a logic LOW on WR starts a conversion (Note 1). RD Read input, active LOW. When CS = HIGH and CE = LOW, a logic LOW on RD enables the 3-state data outputs (Note 2). CONT/ DEMAND Conversion control input. When CONT/DEMAND = LOW, conversions are initi- ated by the WR input. When CONT/DEMAND = HIGH, conversions are performed continuously (Note 1). OVR/POL Overrange/polarity data-select input. When making conversions in the Demand mode (CONT/DEMAND = LOW), OVR/POL controls the data output on DB7 when the high-order byte is active (Note 2). L/H Low/high byte-select input. When CONT/DEMAND = LOW, this input controls whether low-byte or high-byte data is enabled on DB0 through DB7 (Note 2). DB7 Most Significant data bit output. When reading the A/D conversion result, the polarity, overrange and DB7 data are output on this pin. 9-15 10-17 DB6-DB0 Data outputs DB6-DB0. 3-state, bus compatible. BUSY A/D conversion status output. BUSY goes to a logic HIGH at the beginning of the de-integrate phase, then goes LOW when conversion is complete. The falling edge of BUSY can be used to generate a μP interrupt. OSC1 Crystal oscillator connection or external oscillator input. OSC2 Crystal oscillator connection. TEST For factory testing purposes only. Do not make external connection to this pin. DGND Digital ground connection. COMP Connection for comparator auto-zero capacitor. Bypass to VSS with 0.1 μF. VSS Negative power supply connection, typically -5V. INTOUT Output of the integrator amplifier. Connect to CINT. INTIN Input to the integrator amplifier. Connect to summing node of RINT and CINT. BUFFER Output of the input buffer. Connect to RINT. CBUFB Connection for buffer auto-zero capacitor. Bypass to VSS with 0.1 μF. CBUFA Connection to buffer auto-zero capacitor. Bypass to VSS with 0.1 μF. CINTA Connection for integrator auto-zero capacitor. Bypass to VSS with 0.1 μF. CINTB Connection for integrator auto-zero capacitor. Bypass to VSS with 0.1 μF. ANALOG COMMON Analog common. IN– Negative differential analog input. IN+ Positive differential analog input. Note This pin incorporates a pull-down resistor to DGND. This pin incorporates a pull-up resistor to VDD. Pins 1, 23 and 34 (44-PLCC) package are NC “No Internal connection”.

© 2006 Microchip Technology Inc. DS21479C-page 7 TC850 REF2+ Positive input for reference voltage VREF2. (VREF2 = VREF1/64) CREF2+ Positive connection for VREF2 reference capacitor. CREF2– Negative connection for VREF2 reference capacitor. REF– Negative input for reference voltages. CREF1– Negative connection for VREF1 reference capacitor. CREF1+ Positive connection for VREF1 reference capacitor. REF1+ Positive input for VREF1. VDD Positive power supply connection, typically +5V. TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin Number (40-Pin PDIP/CERDIP) Pin Number (44-Pin PLCC) Symbol This pin incorporates a pull-down resistor to DGND. This pin incorporates a pull-up resistor to VDD. Pins 1, 23 and 34 (44-PLCC) package are NC “No Internal connection”.

© 2006 Microchip Technology Inc. DS21479C-page 9 TC850 4.0 ANALOG SECTION The TC850 analog section consists of an input buffer amplifier, integrator amplifier, comparator and analog switches. A simplified block diagram is shown in Figure 4-1. 4.1 Conversion Timing Each conversion consists of three phases: Zero Integrator Signal Integrate Reference Integrate (or De-integrate) Each conversion cycle requires 1280 internal clock cycles (Figure 4-2). FIGURE 4-1: Analog Section Simplified Schematic FIGURE 4-2: Conversion Timing RINT INTIN INTOUT CINT INT INT INT Buffer* BUFF Integrator* Comparator* To Digital Section DE1 (+) DE DE DE DE DE1 (+) DE1 (-) DE1 (-) DE2 (+) DE2 (-) DE1 (+) DE1 (-) REF2+ TC850 CREF1+ CREF2- CREF2 CREF1- CREF2- REF1+ REF1- CREF1 IN+ IN- ANALOG COMMON *Auto Zeroed Amplifiers Conversion Phase Internal Clock Signal Integrate Zero Integrator Reference Integrate

1280 Clock Cyles

. .

© 2006 Microchip Technology Inc. 4.2 Zero Integrator Phase During the zero integrator phase, the differential input signal is disconnected from the circuit by opening inter- nal analog gates. The internal nodes are shorted to analog common (ground) to establish a zero input con- dition. At the same time, a feedback loop is closed around the input buffer, integrator and comparator. The feedback loop ensures the integrator output is near 0V before the signal integrate phase begins. During this phase, a chopper-stabilization technique is used to cancel offset errors in the input buffer, integra- tor and comparator. Error voltages are stored on the CBUFF, CINT and COMP capacitors. The zero integrate phase requires 246 clock cycles. 4.3 Signal Integrate Phase The zero integrator loop is opened and the internal dif- ferential inputs are connected to IN+ and IN-. The differ- ential input signal is integrated for a fixed time period. The TC850 signal integrate period is 256 clock periods, or counts. The crystal oscillator frequency is ÷4 before clocking the internal counters. The integration time period is: EQUATION 4-1: 4.4 Reference Integrate Phase During reference integrate phase, the charge stored on the integrator capacitor is discharged. The time required to discharge the capacitor is proportional to the analog input voltage. The reference integrate phase is divided into three subphases: Fast Slow Overrange de-integrate During fast de-integrate, VIN- is internally connected to analog common and VIN+ is connected across the pre- viously-charged reference capacitor (CREF1). The inte- grator capacitor is rapidly discharged for a maximum of 512 internal clock pulses, yielding 9 bits of resolution. During the slow de-integrate phase, the internal VIN+ node is now connected to the CREF2 capacitor and the residual charge on the integrator capacitor is further discharged a maximum of 64 clock pulses. At this point, the analog input voltage has been converted with 15 bits of resolution. If the analog input is greater than full scale, the TC850 performs up to three overrange de-integrate sub- phases. Each subphase occupies a maximum of 64 clock pulses. The overrange feature permits analog inputs up to 192 LSBs greater than full scale to be correctly converted. This feature permits the user to digitally null up to 192 counts of input offset, while retaining full 15-bit resolution. In addition to 512 counts of fast, 64 counts of slow and 192 counts of overrange de-integrate, the reference integrate phase uses 10 clock pulses to permit internal nodes to settle. Therefore, the reference integrate cycle occupies 778 clock pulses. TINT = 4 x 256 FOSC

© 2006 Microchip Technology Inc. DS21479C-page 11 TC850 5.0 PIN DESCRIPTION (ANALOG) 5.1 Differential Inputs (IN+ and IN–) The analog signal to be measured is applied at the IN+ and IN– inputs. The differential input voltage must be within the Common mode range of the converter. The input Common mode range extends from VDD - 1.5V to VSS +1.5V. Within this Common mode voltage range, an 80 dB CMRR is typical. The integrator output also follows the Common mode voltage. The integrator output must not be allowed to saturate. A worst-case condition exists, for example, when a large, positive Common mode voltage, with a near full scale negative differential input voltage, is applied. The negative input signal drives the integrator positive when most of its available swing has been used up by the positive Common mode voltage. For applications where maximum Common mode range is critical, integrator swing can be reduced. The integrator output can swing within 0.4V of either supply without loss of linearity. 5.2 Differential Reference (VREF) The TC850 requires two reference voltage sources in order to generate the “fast-slow” de-integrate phases. The main voltage reference (VREF1) is applied between the REF1+ and REF- pins. The secondary reference (VREF2) is applied between the REF2+ and REF- pins. The reference voltage inputs are fully differential and the reference voltage can be generated anywhere within the power supply voltage of the converter. How- ever, to minimize rollover error, especially at high con- version rates, keep the reference Common mode voltage (i.e., REF-) near or at the analog common potential. All voltage reference inputs are high-imped- ance. Average reference input current is typically only 30 pA. 5.3 Analog Common (ANALOG COMMON) Analog common is used as the IN- return during the zero integrator and de-integrate phases of each con- version. If IN- is at a different potential than analog common, a Common mode voltage exists in the sys- tem. This signal is rejected by the 80dB CMRR of the converter. However, in most applications, IN- will be set at a fixed, known voltage (power supply common, for instance). In this case, analog common should be tied to the same point so that the Common mode voltage is eliminated.

© 2006 Microchip Technology Inc. 6.0 DIGITAL SECTION The TC850 digital section consists of two sets of con- version counters, control and sequencing logic, clock oscillator and divider, data latches and an 8-bit, 3-state interface bus. A simplified schematic of the bus interface logic is shown in Figure 6-1 6.1 Clock Oscillator The TC850 includes a crystal oscillator on-chip. All that is required is to connect a crystal across OSC1 and OSC2 pins and to add two inexpensive capacitors (Figure 1-1). The oscillator output is ÷ 4 prior to clock- ing the A/D internal counters. For example, a 100 kHz crystal produces a system clock frequency of 25 kHz. Since each conversion requires 1280 clock periods, in this case the conversion rate will be 25,000/1280, or 19.5 conversions per second. In most applications, however, an external clock is divided down from the microprocessor clock. In this case, the OSC1 pin is used as the external oscillator input and OSC2 is left unconnected. The external clock driver should swing from digital ground to VDD. The ÷ 4 function is active for both external clock and crystal oscillator operations. FIGURE 6-1: Bus Interface Simplified Schematic 6.2 Digital Operating Modes Two modes of operation are available with the TC850, continuous conversions and on-demand. The Operat- ing mode is controlled by the CONT/DEMAND input. The bus interface method is different for Continuous and Demand modes of operation. 6.2.1 DEMAND MODE OPERATION When CONT/DEMAND is low, the TC850 performs one conversion each time the chip is selected and the WR input is pulsed low. Data is valid on the falling edge of the BUSY output and can be accessed using the interface truth table (Table 6-1). 6.2.2 CONTINUOUS MODE OPERATION When CONT/DEMAND is high, the TC850 continu- ously performs conversions. Data will be valid on the falling edge of the BUSY output and remains valid for 443-1/2 clock cycles. The low/high (L/H) byte-select and overrange/polarity (OVR/POL) inputs are disabled during Continuous mode operation. Data must be read in three consecutive bytes, as shown in Table 6-1. RD L/H 3-State Buffer Output Enable End of Conversion CONT/ DEMAND Start Conversion To A/D Control Logic Octal 2-Input Mux Select Low-Byte Up/Down Counter High-Byte Up/Down Counter Polarity Overrange TC850 Select 2-Input Mux DBO–DB7 CE CS WR POL/OVR Note: In Continuous mode, the conversion result must be read within 443-1/2 clock cycles of the BUSY output falling edge. After this time (i.e.,1/2 clock cycle before BUSY goes high) the internal counters are reset and the data is lost.

© 2006 Microchip Technology Inc. DS21479C-page 13 TC850 TABLE 6-1: BUS INTERFACE TRUTH TABLE CE • CS Pins 1 and 2 RD Pin 4 CONT/DEMAND Pin 5 L/H Pin 7 OVR/POL Pin 6 DB7 Pin 8 DB6–DB0 Pin 9-Pin 15 (Note 1) “1” = Input Positive Data Bits 14 - 8 “1” = Input Overrange (Note 2) Data Bits 14 - 8 X Data Bit 7 Data Bits 6 - 0 X X Note 3 X X X High-Impedance State X X X X High-Impedance State Note Pin numbers refer to 40-pin PDIP. Extended overrange operation: Although rated at 15 bits (±32,767 counts) of resolution, the TC850 provides an addi- tional 191 counts above full scale. For example, with a full-scale input of 3.2768V, the maximum analog input voltage which will be properly converted is 3.2958V. The extended resolution is signified by the overrange bit being high and the low-order byte contents being between 0 and 190. For example, with a full-scale voltage of 3.2768V: VIN Overrange Bit Low Byte Data Bits 14–8 3.2767V Low 25510 12710 3.2768V High 00010 010 3.2769V High 00110 010 3.2867V High 09910 010 Continuous mode data transfer: a. In Continuous mode, data MUST be read in three sequential bytes after the BUSY output goes low: (1) The first byte read will be the high-order byte, with DB7 = polarity. (2) The second byte read will contain the low-order byte. (3) The third byte read will again be the high-order byte, but with DB7 = overrange. All three data bytes must be read within 443-1/2 clock cycles after the falling edge of BUSY. The c input must go high after each byte is read, so that the internal byte counter will be incremented. However, the CS and CEinputs can remain enabled through the entire data transfer sequence.

© 2006 Microchip Technology Inc. 6.3 Pin Description (Digital) 6.3.1 CHIP SELECT AND CHIP ENABLE (CS AND CE) The CS and CE inputs permit easy interfacing to a vari- ety of digital bus systems. CE is active LOW while CS is active HIGH. These inputs are logically ANDed internally and are used to enable the RD and WR inputs. 6.3.2 WRITE ENABLE INPUT (WR) The write input is used to initiate a conversion when the TC850 is in Demand mode. CS and CE must be active for the WR input to be recognized. The status of the data bus is meaningless during the WR pulse, because no data is actually written into the TC850. 6.3.3 READ ENABLE INPUT (RD) The read input, combined with CS and CE, enable the 3-state data bus outputs. Also, in Continuous mode, the rising edge of the RD input activates an internal byte counter to sequentially read the three data bytes. 6.3.4 LOW/HIGH BYTE SELECT (L/H) The L/H input determines whether the low (Least Significant) Byte or high (Most Significant) Byte of data is placed on the 3-state data bus. This input is mean- ingful only when the TC850 is in the Demand mode. In the Continuous mode, data must be read in three predetermined bytes, so the L/H input is ignored. 6.3.5 OVERRANGE/POLARITY BIT SELECT (OVR/POL) The TC850 provides 15 bits of resolution, plus polarity and overrange bits. Thus, 17 bits of information must be transferred on an 8-bit data bus. To accomplish this, the overrange and polarity bits are multiplexed onto data bit DB7 of the Most Significant Byte. When OVR/POL is HIGH, DB7 of the high byte contains the overrange sta- tus (HIGH = analog input overrange, LOW = input within full scale). When OVR/POL is LOW, DB7 is HIGH for positive analog input polarity and LOW for negative polarity. The OVR/POL input is meaningful only when CS, CE and RD are active, and L/H is LOW (i.e., the Most Significant Byte is selected). OVR/POL is ignored when the TC850 is in Continuous mode. 6.3.6 CONTINUOUS/DEMAND MODE INPUT (CONT/DEMAND) This input controls the TC850 Operating mode. When CONT/DEMAND is HIGH, the TC850 performs conver- sions continuously. In Continuous mode, data must be read in the prescribed sequence shown in Table 6-1. Also, all three data bytes must be read within 443-1/2 internal clock cycles after the BUSY output goes low. After 443-1/2 clock cycles data will be lost. When CONT/DEMAND is LOW, the TC850 begins a conversion each time CS and CE are active and WR is being pulsed LOW. The conversion is complete and data can be read after the falling edge of the BUSY out- put. In Demand mode, data can be read in any sequence and remains valid until WR is again pulsed LOW. 6.3.7 BUSY OUTPUT (BUSY) The BUSY output is used to convey an end-of-conver- sion to external logic. BUSY goes HIGH at the begin- ning of the de-integrate phase and goes LOW at the end of the conversion cycle. Data is valid on the falling edge of BUSY. The output-high period is fixed at 836 clock periods, regardless of the analog input value. BUSY is active during Continuous and Demand mode operation. This output can also be used to generate an end-of- conversion interrupt in μP-based systems. Noninterrupt-driven systems can poll BUSY to determine when data is valid.

© 2006 Microchip Technology Inc. DS21479C-page 15 TC850 7.0 ANALOG SECTION TYPICAL

APPLICATIONS

7.1 Component Selection 7.1.1 REFERENCE VOLTAGE The typical value for reference voltage VREF1 is 1.6384V. This value yields a full scale voltage of 3.2768V and resolution of 100 μV per step. The VREF2 value is derived by dividing VREF1 by 64. Thus, typical VREF2 value is 1.6384V/64, or 25.6 mV. The VREF2 value should be adjusted within ±1% to maintain 15-bit accuracy for the total conversion process; EQUATION 7-1: The reference voltage is not limited to exactly 1.6384V, however, because the TC850 performs a ratiometric conversion. Therefore, the conversion result will be: EQUATION 7-2: The full scale voltage can range from 3.2V to 3.5V. Full scale voltages of less than 3.2V will result in increased noise in the Least Significant bits, while a full scale above 3.5V will exceed the input common-mode range. 7.1.2 INTEGRATION RESISTOR The TC850 buffer supplies 25 μA of integrator charging current with minimal linearity error. RINT is easily calculated: EQUATION 7-3: For a full scale voltage of 3.2768V, values of RINT between 120 kΩ and 150 kΩ are acceptable. 7.1.3 INTEGRATION CAPACITOR The integration capacitor should be selected to produce an integrator swing of ≈ 4V at full scale. The capacitor value is easily calculated: EQUATION 7-4: The integration capacitor should be selected for low dielectric absorption to prevent rollover errors. A polypropylene, polyester or polycarbonate dielectric capacitor is recommended. 7.1.4 REFERENCE CAPACITORS The reference capacitors require a low-leakage dielec- tric, such as polypropylene, polyester or polycarbon- ate. A value of 1 μF is recommended for operation over the temperature range. If high-temperature operation is not required, the CREF values can be reduced. 7.1.5 AUTO-ZERO CAPACITORS Five capacitors are required to auto-zero the input buffer, integrator amplifier and comparator. Recom- mended capacitors are 0.1 μF film dielectric (such as polyester or polypropylene). Ceramic capacitors are not recommended. VREF = VREF1 ± 1% Digital Counts = • 16384 VIN VREF1 RINT = VFULLSCALE 25 μA C = VFS RINT 4 • 256 4V FCLOCK where: FCLOCK is the crystal or external oscillator frequency and VFS is the maximum input voltage.

© 2006 Microchip Technology Inc. FIGURE 8-4: Conversion Timing, Demand Mode FIGURE 8-5: Bus Output Timing, Demand Mode WR Pulses are Ignored

836 Clock Cycles

1100 Clock Cycles

CS . CE Next Convert Command will be Recognized Previous Conversion Data Valid Data Meaningless New Conversion Data Valid Next Conversion can Begin

319 Clock

125 Clock

. . . . WR DB0-DB6 DB7 OVR/POL L/H TCE TDHC TDHR TRE CS . CE HI-Z Data Bits 8 to 14 High-Impedance High-Impedance Don't Care Don't Care Data Bits 0 tp 6 HI-Z "1"= Input Overrange "1"= Positive Polarity Data Bit 7 tOP TLH RD NOTE: CONT/DEMAND = LOW *RD (as well as CS and CE) can go HIGH after each byte is read (i.e., in a mP bus interface) or remain LOW during the entire DATA-READ sequence (i.e., mP I/O port interface).

© 2006 Microchip Technology Inc. DS21479C-page 19 TC850 FIGURE 8-6: Conversion Timing, Continuous Mode FIGURE 8-7: Bus Output Timing, Continuous Mode DB0-DB7 Busy Internal Clock Data Meaningless Data Valid Data Meaningless 1/2 Clock Cycle

1280 Internal Clock Cycles

NOTES: CS = HIGH; CE = LOW Data Bits 0-7 Data Bits 8-14 Overrange High-Impedance State HI-Z TRE TWRE TWRD Data Bits 8-14 Polarity

© 2006 Microchip Technology Inc. 9.0 PACKAGING INFORMATION 9.1 Package Marking Information Package marking data not available at this time 9.2 Taping Form 9.3 Package Dimensions Component Taping Orientation for 44-Pin PLCC Devices NOTE: Drawing does not represent total number of pins. Pin 1 User Direction of Feed Standard Reel Component Orientation for 713 Suffix Device W P Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 44-Pin PLCC 32 mm 24 mm 500 13 in Carrier Tape, Number of Components Per Reel and Reel Size .015 (0.38) .008 (0.20) .620 (15.75) .590 (15.00) .700 (17.78) .620 (15.75) .540 (13.72) .510 (12.95) 2.070 (52.58) 2.030 (51.56) .210 (5.33) .170 (4.32) .020 (0.51) .016 (0.41) .110 (2.79) .090 (2.29) .065 (1.65) .045 (1.14) .200 (5.08) .125 (3.18) .098 (2.49) Max. .030 (0.76) Min. .060 (1.52) .020 (0.51) .150 (3.81) Min. 40-Pin CERDIP (Wide) Pin 1 3° Min. Dimensions: inches (mm)

© 2006 Microchip Technology Inc. DS21479C-page 21 TC850 9.3 Package Dimensions (Continued) 2.065 (52.45) 2.027 (51.49) .200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .022 (0.56) .015 (0.38) .110 (2.79) .090 (2.29) .555 (14.10) .530 (13.46) .610 (15.49) .590 (14.99) .015 (0.38) .008 (0.20) .700 (17.78) .610 (15.50) .040 (1.02) .020 (0.51) 40-Pin PDIP (Wide) Pin 1 3° Min. Dimensions: inches (mm) .695 (17.65) .685 (17.40) .656 (16.66) .650 (16.51) .656 (16.66) .650 (16.51) .021 (0.53) .013 (0.33) .032 (0.81) .026 (0.66) .630 (16.00) .591 (15.00) .120 (3.05) .090 (2.29) .180 (4.57) .165 (4.19) .695 (17.65) .685 (17.40) .050 (1.27) Typ. .020 (0.51) Min. Pin 1 44-Pin PLCC Dimensions: inches (mm)

© 2006 Microchip Technology Inc. NOTES:

© 2006 Microchip Technology Inc. DS21479C-page 23 TC850 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software
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• Distributor or Representative
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• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com

© 2006 Microchip Technology Inc. READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response From: Name Company Address City / State / ZIP / Country Application (optional): Would you like a reply? Y N Device: Literature Number: Questions: DS21479C TC850 What are the best features of this document? How does this document meet your hardware and software development needs? Do you find the organization of this document easy to follow? If not, why? What additions to the document do you think would enhance the structure and subject? What deletions from the document could be made without affecting the overall usefulness? Is there any incorrect or misleading information (what and where)? How would you improve this document?

© 2006 Microchip Technology Inc. DS21479C-page 25 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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