TC820CPL

TC820 MICROCHIP | Alldatasheet

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Technical content

Features

• Multiple Analog Measurement System - Digit A/D Converter - Frequency Counter - Logic Probe  Low Noise A/D Converter: - Differential Inputs: (1pA Bias Current) - On-Chip 50ppm/°C Voltage Reference  Frequency Counter: - 4MHz Maximum Input Frequency - Auto-Ranging Over Four Decade Range  Logic Probe: - Two LCD Annunciators - Buzzer Driver  3-3/4 Digit Display with Over Range Indicator  LCD Display Driver with Built-in Contrast Control  Data Hold Input for Comparison Measurements  Low Battery Detect with LCD Annunciator  Under Range and Over Range Outputs  On-Chip Buzzer Driver with Control Input  40-Pin Plastic DIP, 44-Pin Plastic Flat Pack, or 44-Pin PLCC Packages Device Selection Table General Description The TC820 is a 3-3/4 digit, multi-measurement system especially suited for use in portable instruments. It inte- grates a dual slope A/D converter, auto-ranging fre- quency counter and logic probe into a single 44-pin surface mount, or 40-pin through hole package. The TC820 operates from a single 9V input voltage (bat- tery) and features a built-in battery low flag. Function and decimal point selection are accomplished with sim- ple logic inputs designed for direct connection to an external microcontroller or rotary switch. Part Number Resolution Package Operating Temp. Range TC820CPL 3-3/4 Digits 40-Pin PDIP 0 °Ct o+ 7 0°C TC820CKW 3-3/4 Digits 44-PinPQFP 0 °Ct o+ 7 0°C TC820CLW 3-3/4 Digits 44-Pin PLCC 0 °Ct o+ 7 0°C 3-3/4 Digit A/D Converter with Frequency Counter and Logic Probe

DS21476B-page 2  2002 Microchip Technology Inc. Package Type TC820CPL OSC1 OSC2 OSC3 CREF+ COM VSS PKHOLD FREQ/VOLTS BUZIN BUZOUT DP1/HIDP0/LO

1 CAZ

7 CAZ

42 OSC1

41 EOC/HOLD

40 VINT

12 TC820CLW

L–E4 UR PKHOLD AGD2 OFE2 VDISP BC2P1 PKFE1 BP2 OSC1 VSS OR COM CREF+ BC4P3 OSC3 OSC2 EOC/HOLD ANNUNC FREQ/VOLTS BUZIN BUZOUT DP1/HI DP0/LO RANGE/FREQ LOGIC BP1 BP3 BC1BT AGD1 VBUFF VIN+ VIN- VREF- VREF+ CREF- HFE3 AGD4 VDD

 2002 Microchip Technology Inc. DS21476B-page 3 TC820 Typical Applications Peak Hold Comparator 3-3/4 Digit A/D Converter Low Battery Detect Decimal Point Drivers Buzzer Driver Function SelectLogic Probe Auto-Ranging Frequency Counter Clock Oscillator Triple LCD Drivers Low Drift Voltage Differential Reference Logic High Logic Low Over Range PKHold Low Batt Annunciator Drive Decimal Point Select Buzzer Control Function Select Digital Ground To LCD and Buzzer Peak Hold Logic Probe Input Frequency Input Full Scale Select Under Range Over Range Analog GND Volts Frequency Logic Triplex LCD TC820 Analog Input EOC Range Frequency Input Triples Drivers Display Latch Comparator A > B A/D Counter (3999 Counts) Logic Low Logic DP0/LO DP1/HI Range/ Frequency Frequency/ Volts Buzzer Driver BUZIN Logic Low OSC3OSC2OSC1 Frequency Counter Input A/D Counter Select Range SEL B A Low Batt Low Batt Detect A/D Control DEINT Under Range Over Range Range EOC DGND UR OR EOC/ HOLD PEAK HOLD ANNUNC SEG0    BP3VDISP To LCD VINTCAZ Common VDD VSS VREF+ VREF- TC820 VIN+ VIN- CREF+C REF-V BUFF

DS21476B-page 4  2002 Microchip Technology Inc.

1.0 ELECTRICAL

Absolute Maximum Ratings* Analog Input Voltage: Package Power Dissipation (TA –7 0 ° C )(Note 2): Operating Temperature Range: *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. TC820 ELECTRICAL SPECIFICATIONS Electrical Characteristics: VS =9 V ,TA = 25°C, unless otherwise specified. Symbol Parameter Min Typ Max Units Test Conditions Zero Input Reading -000 ±000 +000 Digital Reading VIN =0 V Full Scale = 400mV RE Rollover Error -1 ±0.2 +1 Counts V IN = ±390mV Full Scale = 400mV NL Nonlinearity (Maximum Deviation From Best Straight Line Fit) -1 ±0.2 +1 Count Full Scale = 400mV Ratiometric Reading 1999 1999/2000 2000 — V IN =V REF,T C 8 2 0 CMRR Common Mode Rejection Ratio — 50 — µV/V V CM =± 1 V ,VIN =0 V Full Scale = 400mV (VFS =2 0 0 m V ) VCMR Common Mode Voltage Range V SS +1 . 5 — V DD – 1 Input High, Input Low eN Noise (P-P Value Not Exceeded 95% of Time) —1 5 — µVV IN =0 V Full Scale = 400mV IIN Input Leakage Current — — — — V IN =0 V —1 1 0 p A T A =2 5 ° C —2 0 — p A 0 ° C ≤ TA ≤ +70°C —1 0 0 —p A - 4 0 ° C ≤ TA ≤ +85°C VCOM Analog Common Voltage 3.15 3.3 3.45 V 25k Ω between Common and VDD (VSS -V COM) VCTC Common Voltage T emperature Coefficient —— — — 2 5 k Ω Between Common and VDD —3 5 5 0 p p m / ° C 0 ° C ≤ TA ≤ +70°C Note 1: Input voltages may exceed the supply voltages provided that input current is limited to ±100µA. Current above this value may result in invalid display readings, but will not destroy the device if limited to ±1mA. 2: Dissipation ratings assume device is mounted with all leads soldered to printed circuit board.

 2002 Microchip Technology Inc. DS21476B-page 5 TC820 TCZS Zero Reading Drift — — — — V IN =0 V TCFS Scale Factor T emperature Coefficient —— — — V IN =3 9 9 m V —1 5 p p m / ° C 0 ° C ≤ TA ≤ +70°C — 5 — ppm/°C -40°C ≤ TA ≤ +85°C Ext Ref = 0ppm/°C IS Supply Current — 1 1.5 mA V IN =0 V Peak-to-Peak Backplane Drive Voltage 4.25 4.7 5.3 V V S =9 V VDISP =D G N D Buzzer Frequency — 5 — kHz F OSC =4 0 k H z Counter TIme-Base Period — 1 — Second F OSC =4 0 k H z Low Battery Flag Voltage 6.7 7 7.3 V V DD to VSS VIL Input Low Voltage — — DGND + 1.5 V VIH Input High Voltage V DD –1 . 5 — — V VOL Output Low Voltage, UR, OR Outputs VDD –1 . 5 — D G N D+0 . 4 V I L =5 0µA Control Pin Pull-down Current — 5 — µAV IN =V DD TC820 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: VS =9 V ,TA = 25°C, unless otherwise specified. Symbol Parameter Min Typ Max Units Test Conditions Note 1: Input voltages may exceed the supply voltages provided that input current is limited to ±100µA. Current above this value may result in invalid display readings, but will not destroy the device if limited to ±1mA. 2: Dissipation ratings assume device is mounted with all leads soldered to printed circuit board.

DS21476B-page 6  2002 Microchip Technology Inc.

2.0 PIN DESCRIPTIONS

T h ed e s c r i p t i o n so ft h ep i n sa r el i s t e di nT a b l e2 - 1 . TABLE 2-1: PIN FUNCTION TABLE Pin Number (40-PDIP) Pin Number (44-PQFP) Symbol Description 1 40 L-E4 LCD segment driver for L ("logic LOW"), polarity, and "e" segment of most significant digit (MSD). 2 41 AGD4 LCD segment drive for "a," "g," and "d" segments of MSD. 3 42 BC4P3 LCD segment drive for "b" and "c" segments of MSD and decimal point 3. 4 43 HFE3 LCD segment drive for H ("logic HIGH"), and "f" and "e" segments of third LSD. 5 44 AGD3 LCD segment drive for "a," "g," and "d" segments of third LSD. 6 1 BC3P2 LCD segment drive for "b" and "c" segments of third LSD and decimal point 2. 7 2 OFE2 LCD segment drive for "over range," and "f" and "e" segments of second LSD. 8 3 AGD2 LCD segment drive for "a," "g," and "d" segments of second LSD. 9 4 BC2P1 LCD segment drive for "b " and "c" segments of second LSD and decimal point 1. 10 5 PKFE1 LCD segment drive for "hold peak reading," and "f" and "e" segments of LSD. 11 6 AGD1 LCD segment drive for "a," "g," and "d" segments of LSD. 12 7 BC1BT LCD segment drive for "b" and "c" segments of LSD and "low battery." 13 8 BP3 LCD backplane #3. 14 9 BP2 LCD backplane #2. 15 10 BP1 LCD backplane #1. —1 1 V DISP Sets peak LCD drive signal: VPEAK =( VDD)–V DISP.V DISP m a ya l s ob eu s e dt o compensate for temperature variation of LCD crystal threshold voltage. 16 12 DGND Internal logic digital ground, the logic "0" level. Nominally 4.7V below V DD. 17 13 ANNUNC Square-wave output at the backplane frequency, synchronized to BP1. ANNUNC can be used to control display annunciators. Connecting an LCD segment to ANNUNC turns it on; connecting it to its backplane turns it off. 18 14 LOGIC Logic mode control input. When connected to V DD, the converter is in Logic mode. The LCD displays "OL" and the decimal point inputs control the HIGH and LOW annunciators. When the "low" annunciator is on, the buzzer will also be on. When unconnected or con- nected to DGND, the TC820 is in the Voltage/Frequency Measurement mode. This pin has a 5µA internal pull-down to DGND 19 15 RANGE/ FREQ Dual purpose input. In Range mode, when connected to V DD, the integration time will be 200 counts instead of 2000 counts 20 16 DP0/LO Dual purpose input. Decimal point select input for voltage measurements. In logic mode, connecting this pin to VDD will turn on the "low" LCD segment. There is an internal 5 µA pull-down to DGND in Volts mode only. Decimal point logic: DP1 DPQ Decimal Point Selected

00 N o n e

01 D P 1

10 D P 2

11 D P 3

21 17 DP1/HI Dual purpose input. Decimal point select input for voltage measurements. In Logic mode, connecting this pin to V DD will turn on the "high" LCD segment. There is an internal 5 µA pull-down to DGND in Volts mode only. 22 18 BUZOUT Buzzer output. Audio frequency, 5kHz, output which drives a piezoelectric buzzer. 23 19 BUZIN Buzzer control input. Connecting BUZIN to V DD turns the buzzer on. BUZIN is logically OR’ed (internally) with the "logic level low" input. There is an internal 5µAp u l l - d o w nt o DGND. 24 20 FREQ/ VOLTS Voltage or frequency measurement select input. When unconnected, or connected VOLTS to DGND, the A/D converter function is active. When connected to V DD,t h e frequency counter function is active. This pin has an internal 5 µA pull-down to DGND.

 2002 Microchip Technology Inc. DS21476B-page 7 TC820 25 21 PKHOLD Peak hold input. When connected to V DD, the converter will only update the display if a new conversion value is greater than the preceding value. Thus, the peak reading will be stored and held indefinitely. When unconnected, or connected to DGND, the converter will operate normally. This pin has an internal 5µA pull-down to DGND. — 22 UR Under range output. This output will be HIGH when the digital reading is 380 counts or less. — 23 OR Over range output. This output will be HIGH when the analog signal input is greater than full scale. The LCD will display "OL" when the input is over ranged. 26 24 V SS Negative supply connection. Connect to negative terminal of 9V battery. 27 25 COM Analog circuit ground reference point. Nominally 3.3V below V DD. 28 26 C REF+ Positive connection for reference capacitor. 29 27 C REF- Negative connection for reference capacitor. 30 28 V REF+ High differential reference input connection. 31 29 V REF- Low differential reference input connection. 32 30 V IN- Low analog input signal connection. 33 31 V IN+ High analog input signal connection. 34 32 V BUFF Buffer output. Connect to integration resistor. 35 33 C AZ Auto-zero capacitor connection. 36 34 V INT Integrator output. Connect to integration capacitor. —3 5 E O C / HOLD Bi-directional pin. Pulses low (i.e., from V DD to DGND) at the end of each conversion. If connected to VDD, conversions will continue, but the display is not updated. 37 36 OSC1 Crystal oscillator (input) connection. 38 37 OSC2 Crystal oscillator (output) connection. 39 38 OSC3 RC oscillator connection. 40 39 V DD LCD segment drive for "a," "g," and "d" segments of MSD. TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin Number (40-PDIP) Pin Number (44-PQFP) Symbol Description

DS21476B-page 8  2002 Microchip Technology Inc.

3.0 DETAILED DESCRIPTION

The TC820 is a 3-3/4 digit measurement system com- bining an integrating analog-to-digital converter, fre- quency counter, and logic level tester in a single package. The TC820 supersedes the TC7106 in new designs by improving performance and reducing sys- tem cost. The TC820 adds features that are difficult, expensive, or impossible to provide with older A/D con- verters (see Table 3-1). The high level of integration permits TC820 based instruments to deliver higher per- formance and more features, while actually reducing parts count. Fabricated in low power CMOS, the TC820 directly drives a 3-3/4 digit (3999 maximum) LCD. With a maximum range of 3999 counts, the TC820 pro- vides 10 times greater resolution in the 200mV to 400mV range than traditional 3-1/2 digit meters. An auto-zero cycle ensures a zero reading with a 0V input. CMOS processing reduces analog input bias current to only 1pA. Rollover error (the difference in readings for equal magnitude but opposite polarity input signals) is less than ±1 count. Differential reference inputs permit ratiometric measurements for ohms or bridge trans- ducer applications. The TC820's frequency counter option simplifies design of an instrument well-suited to both analog and digital troubleshooting: voltage, current, and resistance measurements, plus precise frequency measurements to 4MHz (higher frequencies can be measured with an external prescaler), and a simple logic probe. The fre- quency counter will automatically adjust its range to match the input frequency, over a four-decade range. Two logic level measurement inputs permit a TC820 based meter to function as a logic probe. When com- bined with external level shifters, the TC820 will display logic levels on the LCD and also turn on a piezoelectric buzzer when the measured logic level is low. Other TC820 features simplify instrument design and reduce parts count. On-chip decimal point drivers are included, as is a low battery detection annunciator. A piezoelectric buzzer can be controlled with an external switch or by the logic probe inputs. Two oscillator options are provided: a crystal can be used if high accu- racy frequency measurements are desired, or a simple RC option can be used for low-end instruments. A "peak reading hold" input allows the TC820 to retain the highest A/D or frequency reading. This feature is useful in measuring motor starting current, maximum temperature, and similar applications. A family of instruments can be created with the TC820. No additional design effort is required to create instru- ments with 3-3/4 digit resolution. The TC820 operates from a single 9V battery, with typ- ical power of 10mW. Packages include a 40-pin plastic DIP , 44-pin plastic flat package (PQFP), and 44-pin PLCC. TABLE 3-1: COMPETITIVE EVALUATION

3.1 General Theory of Operation

3.1.1 DUAL SLOPE CONVERSION

The TC820 analog-to-digital converter operates on the principle of dual slope integration. An understanding of the dual slope conversion technique will aid the user in following the detailed TC820 theory of operation follow- ing this section. A conventional dual slope converter measurement cycle has two distinct phases: 1. Input Signal Integration 2. Reference Voltage Integration (De-integration) Referring to Figure 3-1, the unknown input signal to be converted is integrated from zero for a fixed time period INT), measured by counting clock pulses. A constant reference voltage of the opposite polarity is then inte- grated until the integrator output voltage returns to zero. The reference integration (de-integration) time DEINT) is then directly proportional to the unknown input voltage (VIN). Features Comparison TC820 7106 3-3/4 Digit Resolution Yes No Auto-Ranging Frequency Counter Yes No Logic Probe Yes No Decimal Point Drive Yes No Peak Reading Hold (Frequency or Voltage) Yes No Display Hold Yes No Simple 10:1 Range Change Yes No Buzzer Drive Yes No Low Battery Detection with Annunciator Yes No Over Range Detection with Annunciator Yes No Low Drift Reference Yes No Under Range/Over Range Logic Output Yes No Input Overload Display "OL" "1" LCD Annunciator Driver Yes No LCD Drive Type Triplexed Direct LCD Pin Connections 15 24 LCD Elements 36 23

 2002 Microchip Technology Inc. DS21476B-page 9 TC820 In a simple dual slope converter, a complete conver- sion requires the integrator output to "ramp-up" from zero and "ramp-down" back to zero. A simple mathe- matical equation relates the input signal, reference volt- age, and integration time. EQUATION 3-1: For a constant VINT: EQUATION 3-2: FIGURE 3-1: BASIC DUAL SLOPE CONVERTER Accuracy in a dual slope converter is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. An inher- ent benefit of the dual slope technique is noise immu- nity. Noise spikes are integrated or averaged to zero during the integration periods, making integrating ADCs immune to the large conversion errors that plague successive approximation converters in high noise environments. Interfering signals, with frequency components at multiples of the averaging (integrating) period, will be attenuated (Figure 3-2). Integrating ADCs commonly operate with the signal integration period set to a multiple of the 50/60Hz power line period. FIGURE 3-2: NORMAL MODE REJECTION OF DUAL SLOPE CONVERTER

3.2 Analog Section

In addition to the basic integrate and de-integrate dual slope phases discussed above, the TC820 design incorporates a "zero integrator output" phase and an "auto-zero" phase. These additional phases ensure that the integrator starts at 0V (even after a severe over range conversion), and that all offset voltage errors (buffer amplifier, integrator and comparator) are removed from the conversion. A true digital zero read- ing is assured without any external adjustments. A complete conversion consists of four distinct phases: 1. Zero Integrator Output 2. Auto-Zero 3. Signal Integrate 4. Reference De-integrate

3.2.1 ZERO INTEGRATOR OUTPUT

This phase guarantees that the integrator output is at 0V before the system zero phase is entered, ensuring that the true system offset voltages will be compen- sated for even after an over range conversion. The duration of this phase is 500 counts plus the unused de-integrate counts.

3.2.2 AUTO-ZERO PHASE

During the auto-zero phase, the differential input signal is disconnected from the measurement circuit by open- ing internal analog switches, and the internal nodes are s h o r t e dt oA n a l o gC o m m o n( 0 V REF)t oe s t a b l i s haz e r o input condition. Additional analog switches close a feedback loop around the integrator and comparator to permit comparator offset voltage error compensation. A voltage established on C AZ then compensates for inter- nal device offset voltages during the measurement cycle. The auto-zero phase residual is typically 10µVt o 15µV. The auto-zero duration is 1500 counts. R INTCINT tINT

0 VIN(t)dt =VREFtDEINT

RINTCINT∫ Where: V REF = Reference Voltage tINT = Integration Time tDEINT = De-integration Time VIN =V REF tDEINT tINT REF Voltage Analog Input Signal Display Switch Driver Control Logioc Integrator Output Clock Counter Polarity Control Phase Control VIN = VREF VIN = 1.2VREF Variable Reference Integrate Time Fixed Signal Integrate Time Integrator C ComparatorR 0.1/T 1/T 10/ T Input Frequency Normal Mode Rejection (dB) T = Measurement Period

DS21476B-page 10  2002 Microchip Technology Inc.

3.2.3 SIGNAL INTEGRATION PHASE

Upon completion of the auto-zero phase, the auto-zero loop is opened and the internal differential inputs con- nect to V IN+ and V IN-. The differential input signal is then integrated for a fixed time period, which is 2000 counts (4000 clock periods). The externally set clock frequency is divided by two before clocking the internal counters. The integration time period is: EQUATION 3-3: The differential input voltage must be within the device's Common mode range when the converter and measured system share the same power supply com- mon (ground). If the converter and measured system do not share the same power supply common, as in battery powered applications, V IN-s h o u l db et i e dt o analog common. Polarity is determined at the end of signal integration phase. The sign bit is a "true polarity" indication, in that signals less than 1LSB are correctly determined. This allows precision null detection that is limited only by device noise and auto-zero residual offsets.

3.2.4 REFERENCE INTEGRATE

(DE-INTEGRATE) PHASE The reference capacitor, which was charged during the auto-zero phase, is connected to the input of the inte- grating amplifier. The internal sign logic ensures the polarity of the reference voltage is always connected in the phase opposite to that of the input voltage. This causes the integrator to ramp back to zero at a constant rate, determined by the reference potential. The amount of time required (t DEINT) for the integrating amplifier to reach zero is directly proportional to the amplitude of the voltage that was put on the integrating capacitor (V INT) during the integration phase. EQUATION 3-4: The digital reading displayed by the TC820 is: The oscillator frequency is divided by 2 prior to clock- ing the internal decade counters. The four-phase mea- surement cycle takes a total of 8000 (4000) counts or 16,000 clock pulses. The 8000 count phase is indepen- dent of input signal magnitude or polarity. Each phase of the measurement cycle has the follow- ing length: TABLE 3-2: MEASUREMENT CYCLE PHASE LENGTH Note 1: This time period is fixed. The integration period for theTC820 is: tINT (TC820) = 4000/FOSC = 2000 counts. Where FOSC is the clock oscillator frequency. 2: Times shown are the RANGE/FREQ at logic low (normal operation). When RANGE/FREQ is logic high, signal integrate times are 200 counts. See Section 3.2.7, “10:1 Range Change”.

3.2.5 INPUT OVER RANGE

When the analog input is greater than full scale, the LCD will display "OL" and the "OVER RANGE" LCD annunciator will be on.

3.2.6 PEAK READING HOLD

The TC820 provides the capability of holding the high- est (or peak) reading. Connecting the PK HOLD input to V DD enables the peak hold feature. At the end of each conversion, the contents of the TC820 counter are compared to the contents of the display register. If the new reading is higher than the reading being dis- played, the higher reading is transferred to the display register. A "higher" reading is defined as the reading with the higher absolute value. The peak reading is held in the display register, so the reading will not "droop" or slowly decay with time. The held reading will be retained until a higher reading occurs, the PK HOLD input is disconnected from V DD, or power is removed. The peak signal to be measured must be present dur- ing the TC820 signal integrate period. The TC820 does not perform transient peak detection of the analog input signal. However, in many cases, such as measuring temperature or electric motor starting current, the TC820 "acquisition time" will not be a limitation. If true peak detection is required, a simple circuit will suffice. See the applications section for details. The peak reading function is also available when the TC820 is in the Frequency Counter mode. The counter auto-ranging feature is disabled when peak reading hold is selected. t INT = 4000 FOSC tDEINT = RINTCINTVINT VREF VIN+VIN- Digital Count = 2000 VREF Conversion Phase Counts 1) Auto-Zero 1500 2) Signal Integrate (Notes 1, 2) 2000 3) Reference Integrate 1 to 4001 4) Integrator Output Zero 499 to 4499

 2002 Microchip Technology Inc. DS21476B-page 11 TC820 3.2.7 10:1 RANGE CHANGE The analog input full scale range can be changed with the RANGE/FREQ input. Normally, RANGE/FREQ is held low by an internal pull-down. Connecting this pin to V S+ will increase the full scale voltage by a factor of 10. No external component changes are required. The RANGE/FREQ input operates by changing the integrate period. When RANGE/FREQ is connected to VDD, the signal integration phase of the conversion is reduced by a factor of 10 (i.e., from 2000 counts to 200 counts). For the TC820, the 10:1 range change will result in ±4V full scale. This full scale range will exceed the Common mode range of the input buffer when operating from a 9V battery. If range changing is required for the TC820, a higher supply voltage can be provided, or the input voltage can be divided by 2 externally.

3.3 Frequency Counter

In addition to serving as an analog-to-digital converter, the TC820 internal counter can also function as a fre- quency counter (Figure 3-3). In the Counter mode, pulses at the RANGE/FREQ input will be counted and displayed. The frequency counter derives its time-base from the clock oscillator. The counter time-base is: EQUATION 3-5: Thus, the counter will operate with a 1-second time- base when a 40kHz oscillator is used. The frequency counter accuracy is determined by the oscillator accu- racy. For accurate frequency measurements, a crystal oscillator is recommended. The frequency counter will automatically select the proper range. Auto-range operation extends over four decades, from 3.999kHz to 3.999MHz. Decimal points are set automatically in the Frequency mode (Figure 3-4). The logic switching levels of the RANGE/FREQ input are CMOS levels. For best counter operation, an exter- nal buffer is recommended. See the applications sec- tion for details.

3.4 Logic Probe

The TC820 can also function as a simple logic probe (Figure 3-5). This mode is selected when the LOGIC input is high. Two dual purpose pins, which normally control the decimal points, are used as logic inputs. Connecting either input to a logic high level will turn on the corresponding LCD annunciator. When the "low" annunciator is on, the buzzer will be on. As with the fre- quency counter input, external level shifters/buffers are recommended for the logic probe inputs. FIGURE 3-3: TC820 COUNTER OPERATION tCOUNT = FOSC 40,000 Data Latch, Peak Hold Register, LCD Decoder/Drivers Over Range Detect Under Range Control Auto-Range Control Programmable Divider Clock Oscillator To Decimal Point Drivers Frequency InputRANGE/ FREQ ÷20,000 From Integrator of A/D Converter Comparator LCD 3-3/4 Digit Counter Enable Count Overflow A/D Converter Frequency Counter A/D Converter/Frequency Counter Select TC820 FREQ/ VOLTS

 2002 Microchip Technology Inc. DS21476B-page 13 TC820 When the logic probe function is selected while FREQ/ VOLTS is low (A/D mode), the ADC will remain in the Auto-Zero mode. The LCD will read "OL" and all decimal points will be off (Figure 3-6). FIGURE 3-6: If the logic probe is active while FREQ/VOLTS is high (Counter mode), the frequency counter will continue to operate. The display will read "OL" but the decimal points will be visible. If the logic probe input is also con- nected to the RANGE/FREQ input, bringing the LOGIC input low will immediately display the frequency at the logic probe input.

3.5 Analog Pin Functional Description

3.5.1 DIFFERENTIAL SIGNAL INPUTS

(VIN+), (VIN-) The TC820 is designed with true differential inputs, and accepts input signals within the Input Stage Common mode voltage (V CM) range. The typical range is VDD –1 Vt oV SS + 1.5V. Common mode voltages are removed from the system when the TC820 operates from a battery or floating power source (isolated from measured system) and V SS is connected to analog c o m m o n( s e eF i g u r e3 - 7 ) . In systems where Common mode voltages exist, the 86dB Common mode rejection ratio minimizes error. Common mode voltages do, however, affect the inte- grator output level. A worst case condition exists if a large, positive V CM exists in conjunction with a full scale, negative differential signal. The negative signal drives the integrator output positive along with V CM (Figure 3-8). For such applications, the integrator out- put swing can be reduced below the recommended 2V full scale swing. The integrator output will swing within 0.3V of V DD,o rV DD without increased linearity error.

3.5.2 REFERENCE (V DD,V SS)

The TC820 reference, like the analog signal input, has true differential inputs. In addition, the reference volt- age can be generated anywhere within the power sup- ply voltage of the converter. The differential reference inputs permit ratiometric measurements and simplify interfacing with sensors, such as load cells and temper- ature sensors. To prevent rollover type errors from being induced by large Common mode voltages, C REF should be large compared to stray node capacitance. A 0.1µF capacitor is typical. The TC820 offers a significantly improved analog com- mon temperature coefficient, providing a very stable voltage suitable for use as a voltage reference. The temperature coefficient of analog common is typically 35ppm/°C.

3.5.3 ANALOG COMMON

The analog common pin is set at a voltage potential approximately 3.3V below V DD. This potential is between 3.15V and 3.45V below VDD. Analog common is tied internally to an N-channel FET capable of sink- ing 3mA. This FET will hold the common line at 3.3V below V DD should an external load attempt to pull the c o m m o nl i n et o w a r dVDD. Analog common source cur- rent is limited to 12µA, and is, therefore, easily pulled to a more negative voltage (i.e., below V DD –3 . 3 V ) . The TC820 connects the internal V IN+ and VIN- inputs to analog common during the auto-zero cycle. During the reference integrate phase, V IN- is connected to analog common. If V IN- is not externally connected to analog common, a Common mode voltage exists. This is rejected by the converter's 86dB Common mode rejection ratio. In battery powered applications, analog common and V IN- are usually connected, removing Common mode voltage concerns. In systems where V IN- is connected to the power supply ground or to a given voltage, analog common should be connected to V IN-. The analog common pin serves to set the analog sec- tion reference or common point. The TC820 is specifi- cally designed to operate from a battery, or in any “measurement" system where input signals are not ref- erenced (float), with respect to the TC820 power source. The analog common potential of V DD –3 . 3 V gives a 7V end of battery life voltage. The analog com- mon potential has a voltage coefficient of 0.001%. With a sufficiently high total supply voltage DD –V SS > 7V), analog common is a very stable potential with excellent temperature stability (typically 35ppm/°C). This potential can be used to generate the TC820 reference voltage. An external voltage refer- ence will be unnecessary in most cases, because of the 35ppm/°C temperature coefficient. See the applica- tions section for details. High Low * "High" Annuciator will be on when DP1/HI = Logic High ** "Low" Annunciator and Buzzer will be on when DP0/LO = Logic High

 2002 Microchip Technology Inc. DS21476B-page 15 TC820

4.0 FUNCTION CONTROL INPUTS

4.1 Functional Description

The TC820 Operating modes are selected with the function control inputs. See the control input truth, Table 4-1. The high logic threshold is ≥ V DD –1 . 5 Va n d the low logic level is ≤ DGND +1.5V. TABLE 4-1: TC820 CONTROL INPUT TRUTH TABLE Note 1: Logic "0" = DGND 2: Logic "1" = VDD-

4.1.1 FREQ/VOLTS

This input determines whether the TC820 is in the Ana- log-to-Digital Conversion mode, or in the Frequency Counter mode. When FREQ/VOLTS is connected to VDD, the TC820 will measure frequency at the RANGE/ FREQ input. When unconnected, or connected to DGND, the TC820 will operate as an analog-to-digital converter. This input has an internal 5 µA pull-down to DGND.

4.1.2 LOGIC

The LOGIC input is used to activate the logic probe function. When connected to V DD, the TC820 will enter the Logic Probe mode. The LCD will show "OL" and all decimal points will be off. The decimal point inputs directly control "high" and "low" display annunciators. When LOGIC is unconnected, or connected to DGND, the TC820 will perform analog-to-digital or frequency measurements, as selected by the FREQ/VOLTS input. The LOGIC input has an internal 5 µA pull-down to DGND.

4.1.3 RANGE/FREQ

The function of this dual purpose pin is determined by the FREQ/VOLTS input. When FREQ/VOLTS is con- n e c t e dt oVDD, RANGE/FREQ is the input for the fre- quency counter function. Pulses at this input are counted with a time-base equal to F OSC/40,000. Since this input has CMOS input levels (V DD –1 . 5 Va n d DGND +1.5V), an external buffer is recommended. When the TC820 analog-to-digital converter function is selected, connecting RANGE/FREQ to V DD will divide the integration time by 10. Therefore, the RANGE/ FREQ input can be used to perform a 10:1 range change without changing external components.

4.1.4 DP0/LO, DP1/HI

The function of these dual purpose pins is determined by the LOGIC input. When the TC820 is in the Analog- to-Digital Converter mode, these inputs control the LCD decimal points. See the decimal point truth, Table 4-2. These inputs have internal 5 µA pull-downs to DGND when the Voltage/Frequency Measurement mode is active. Connecting the LOGIC input to V DD places the TC820 in the Logic Probe mode. In this mode, the DP0/LO and DP1/HI inputs control the LCD "low" and "high" annun- ciators directly. When DP1/HI is connected to V DD,t h e "high" annunciator will turn on. When DP0/LO is con- n e c t e dt oV DD, the "low" annunciator and the buzzer will turn on. The internal pull-downs on these pins are disabled when the logic probe function is selected. These inputs have CMOS logic switching thresholds. For optimum performance as a logic probe, external level shifters are recommended. See the applications section for details.

4.1.5 BUZIN

This input controls the TC820 on-chip buzzer driver. Connecting BUZIN to V DD will turn the buzzer on. There is an external pull-down to DGND. BUZIN can be used with external circuitry to provide additional func- tions, such as a fast, audible continuity indication.

4.2 Additional Features

The TC820 is available in 40-pin and 44-pin packages. Several additional features are available in the 44-pin package. Logic Input TC820 FunctionFREQ/ VOLTS RANGE/ FREQ LOGIC X X 1 Logic Probe 0 0 0 A/D Converter, VFULL SCALE =2xV REF 0 1 0 A/D Converter, VFULL SCALE =2 0xV REF

1 Frequency

0 Frequency Counter

TABLE 4-2: TC820 DECIMAL POINT TRUTH TABLE DP1 DP0 LCD 0 0 3999 0 1 399.9 10 3 9 . 9 9 11 3 . 9 9 9

DS21476B-page 16  2002 Microchip Technology Inc.

4.2.1 EOC /HOLD

EOC/HOLD is a dual purpose, bi-directional pin. As an output, this pin goes low for 10 clock cycles at the end of each conversion. This pulse latches the conversion data into the display driver section of the TC820. EOC /HOLD can be used to hold (or "FREEZE") the dis- play. Connecting this pin to V DD inhibits the display update process. Conversions will continue, but the dis- play will not change. EOC /HOLD will hold the display reading for either analog-to-digital, or frequency measurements. The input/output structure of the EOC /HOLD pin is shown in Figure 4-1. The output drive current is only a few microAmps, so EOC /HOLD can easily be over- driven by an open collector logic gate, as well as a FET, bipolar transistor, or mechanical switch. When used as an output, EOC /HOLD will have a slow rise and fall time due to the limited output current drive. A CMOS Schmitt trigger buffer is recommended. FIGURE 4-1: EOC /HOLD PIN

4.2.2 OVER RANGE (OR),

UNDER RANGE (UR) The OR output will be high when the analog input sig- nal is greater than full scale (3999 counts). The UR out- put will be high when the display reading is 380 counts or less. The OR and UR outputs can be used to provide an auto-ranging meter function. By logically ANDing these outputs with the inverted EOC /HOLD output, a single pulse will be generated each time an under ranged or over ranged conversion occurs (Figure 4-2). FIGURE 4-2: GENERATING UNDER RANGE AND OVER RANGE PULSES 4.2.3 V DISP The VDISP input sets the peak-to-peak LCD drive volt- age. In the 40-pin package, V DISP is connected inter- nally to DGND, providing a typical LCD drive voltage of 5VP-P. The 44-pin package includes a separate V DISP input for applications requiring a variable or tempera- ture compensated LCD drive voltage. See the applica- tions information for suggested circuits. EOC/HOLD Display Update EOC TC820 ≈ 500kΩ EOC/HOLD TC820 UR OR *74HC132

 2002 Microchip Technology Inc. DS21476B-page 17 TC820

5.0 TYPICAL APPLICATIONS

5.1 Power Supplies

The TC820 is designed to operate from a single power supply such as a 9V battery (Figure 5-1). The converter will operate over a range of 7V to 15V. For battery oper- ation, analog common (COM) provides a Common mode bias voltage (see analog common discussion in the theory of operation section). However, measure- ments cannot be referenced to battery ground. T o do so will exceed the Negative Common mode voltage limit. FIGURE 5-1: POWERING THE TC820 FROM A SINGLE 9V BATTERY A battery with voltage between 3.5V and 7V can be used to power the TC820, when used with a voltage doubler, as shown in Figure 5-2. The voltage doubler uses the TC7660 and two external capacitors. With this configuration, measurements can be referenced either to analog common or to battery ground. FIGURE 5-2: POWERING THE TC820 FROM A LOW VOLTAGE BATTERY

5.2 Digital Ground (DGND)

Digital ground is generated from an internal zener diode (Figure 5-3). The voltage between V DD and DGND is the internal supply voltage for the digital sec- tion of the TC820. DGND will sink a minimum of 3mA. DGND establishes the low logic level reference for the TC820 mode select inputs, and for the frequency and logic probe inputs. The DGND pin can be used as the negative supply for external logic gates, such as the logic probe buffers. T o ensure correct counter opera- tion at high frequency, connect a 1 µF capacitor from DGND to V DD. DGND also provides the drive voltage for the LCD. The TC820 40-pin package internally connects the LCD V DISP pin to DGND, and provides an LCD drive voltage of about 5V P-P. In the 44-pin package, connecting the VDISP pin to DGND will provide a 5V LCD drive voltage. FIGURE 5-3: DGND AND COM OUTPUTS

5.3 Digital Input Logic Levels

Logic levels for the TC820 digital inputs are referenced to V DD and DGND. The high level threshold is VDD – 1.5V, and the low logic level is DGND + 1.5V. In most cases, digital inputs will be connected directly to VDD with a mechanical switch. CMOS gates can also be used to control the logic inputs, as shown in the logic probe inputs section.

5.4 Clock Oscillator

The TC820 oscillator can be controlled with either a crystal, or with an inexpensive resistor capacitor com- bination. The crystal circuit, shown in Figure 5-4, is rec- ommended when high accuracy is required in the Frequency Counter mode. The 40kHz crystal is a stan- dard frequency for ultrasonic alarms, and will provide a 1-second time-base for the counter or 2.5 analog-to- digital conversions per second. Consult the crystal manufacturer for detailed applications information. TC820 VIN VREF- VDD VREF+ COM VIN+ VIN- VSS VDD VSS VREF+ VREF- TC820 3.5V to 6V TC7660 VIN+ VIN- VIN 10µF3 10µF COM 12µA P TC820 Logic Section 3.2V N N VDD VSS COM DGND

DS21476B-page 18  2002 Microchip Technology Inc. FIGURE 5-4: SUGGESTED CRYSTAL OSCILLATOR CIRCUIT Where low cost is important, the RC circuit of Figure 5-5 can be used. The frequency of this circuit will be approximately: EQUATION 5-1: FIGURE 5-5: RC OSCILLATOR CIRCUIT Typical values are R = 10k Ω and C = 68pF . The resis- tor value should be ≥ 100kΩ. For accurate frequency measurement, an RC oscillator frequency of 40kHz is required.

5.5 System Timing

All system timing is derived from the clock oscillator. The clock oscillator is divided by 2 prior to clocking the A/D counters. The clock is also divided by 8 to drive the buzzer, by 240 to generate the LCD backplane fre- quency, and by 40,000 for the frequency counter time- base. A simplified diagram of the system clock is shown in Figure 5-6. FIGURE 5-6: SYSTEM CLOCK GENERATION

5.6 Component Value Selection

5.6.1 AUTO-ZERO CAPACITOR - C AZ

The value of the auto-zero capacitor (C AZ)h a ss o m e influence on system noise. A 0.47 µF capacitor is rec- ommended; a low dielectric absorption capacitor (Mylar) is required.

5.6.2 REFERENCE VOLTAGE

The reference voltage capacitor used to ramp the inte- grator output voltage back to zero during the reference integrate cycle is stored on C REF.A0 . 1µF capacitor is typical. A good quality, low leakage capacitor (such as Mylar) should be used. TC820 40kHz 38 39 5pF 10pF 22MΩ 470kΩ TOSC = 0.3 RC 5pF 37 38 39 110kΩ 10pF 75pF TC820 A/D Counter TC820 ÷ 40,000Counter Time-Base ÷ 240 LCD Backplane Driver ÷ 8Buzzer ÷ 2 OSC1 OSC2 OSC3 XTAL Oscillator Components RC Oscillator Components

 2002 Microchip Technology Inc. DS21476B-page 19 TC820

5.6.3 INTEGRATING CAPACITOR - C INT

CINT should be selected to maximize integrator output voltage swing without causing output saturation. Analog common will normally supply the differential voltage ref- erence. For this case, a ±2V integrator output swing is optimum when the analog input is near full scale. For 2.5 readings/second (F OSC = 40kHz) and V FS = 400mV, a 0.22µF value is suggested. If a different oscillator fre- quency is used, C INT must be changed in inverse pro- portion to maintain the nominal ±2V integrator swing. An exact expression for C INT is: EQUATION 5-2: CINT must have low dielectric absorption to minimize rollover error. A polypropylene capacitor is recommended.

5.6.4 INTEGRATING RESISTOR - R INT

The input buffer amplifier and integrator are designed with class A output stages. The integrator and buffer can supply 40µA drive currents with negligible linearity errors. R INT is chosen to remain in the output stage lin- ear drive region, but not so large that printed circuit board leakage currents induce errors. For a 400mV full scale, R INT should be about 100kΩ.

5.7 Reference Voltage Selection

A full scale reading (4000 counts for TC820) requires the input signal be twice the reference voltage. See Reference Voltage Selection, Table 5-1 below. Note 1: TC820 in A/D Converter mode, RANGE/FREQ = logic low. 2: Not recommended. 3: VFS > 2V may exceed the Input Common mode range. See Section 3.2.7, "10:1 Range Change". 4: Full scale voltage values are not limited to the val- ues shown. For example, TC820 V FS can be any value from 400mV to 2V. In some applications, a scale factor other than unity may exist between a transducer output voltage and the required digital reading. Assume, for example, that a pressure transducer output is 800mV for 4000 lb/in Rather than dividing the input voltage by two, the refer- ence voltage should be set to 400mV. This permits the transducer input to be used directly. The internal voltage reference potential available at ana- log common will normally be used to supply the con- verter's reference voltage. This potential is stable whenever the supply potential is greater than approxi- mately 7V. The low battery detection circuit and analog common operate from the same internal reference. This ensures that the low battery annunciator will turn on at the time the internal reference begins to lose regulation. The TC820 can also operate with an external refer- ence. Figure 5-7 shows internal and external reference applications. FIGURE 5-7: REFERENCE VOLTAGE CONNECTIONS

5.8 Ratiometric Resistance

The TC820 true differential input and differential refer- ence make ratiometric readings possible. In ratiometric operation, an unknown resistance is measured with respect to a known standard resistance. No accurately defined reference voltage is needed. The unknown resistance is put in series with a known standard and a current is passed through the pair (Figure 5-8). The voltage developed across the unknown is applied to the input and voltages across the known resistor applied to the reference input. If the unknown equals the standard, the input voltage will equal the refer- ence voltage and the display will read 2000. The displayed reading can be determined from the following expression: EQUATION 5-3: The display will over range for values of R UNKNOWN ≥ 2xR STANDARD. TABLE 5-1: REFERENCE VOLTAGE SELECTION Full Scale Input Voltage (VFS)( N o t e1 ) VREF Resolution 200mV (Note 2) — 400mV 200mV 10 µV 1V 500mV 250 µV 2V (Notes 3, 4) 1V 500 µV CINT =

4000 VFS

Where: F OSC = Clock Frequency VFS = Full Scale Input Voltage RINT = Integrating Resistor VINT = Desired Full Scale Integrator Output Swing TC820 TC820 22kΩ VDD VDDVSS VREF+ VREF- Analog Common SET VREF = 1/2 VFULL SCALE (a) Internal Reference (b) External Reference VREF+ VREF- Analog Common 2kΩ VREF VIN VOUT VSS MCP1525 1µF Displayed Reading = RUNKNOWN RSTANDARD

DS21476B-page 20  2002 Microchip Technology Inc. FIGURE 5-8: LOW PARTS COUNT RATIOMETRIC RESISTANCE MEASUREMENT

5.9 Buffering the FREQ Input

When the FREQ/VOLTS input is high and the LOGIC input is low, the TC820 will count pulses at the RANGE/ FREQ input. The time-base will be F OSC/40,000, or 1 second with a 40kHz clock. The signal to be mea- sured should swing from V DD to DGND. The RANGE/ FREQ input has CMOS input levels without hysteresis. For best results, especially with low frequency sine- wave inputs, an external buffer with hysteresis should be added. A typical circuit is shown in Figure 5-9. FIGURE 5-9: FREQUENCY COUNTER EXTERNAL BUFFER

5.10 Logic Probe Inputs

The DP0/LO and DP1/HI inputs provide the logic probe inputs when the LOGIC input is high. Driving either DP0/LO or DP1/HI to a logic high will turn on the appro- priate LCD annunciator. When DP0/LO is high, the buzzer will be on. To provide a "single input" logic probe function, external buffers should be used. A simple circuit is shown in Figure 5-10. This circuit will turn the appropriate annun- ciator on for high and low level inputs. FIGURE 5-10: SIMPLE EXTERNAL LOGIC PROBE BUFFER If carefully controlled logic thresholds are required, a window comparator can be used. Figure 5-11 shows a typical circuit. This circuit will turn on the high or low annunciators when the logic thresholds are exceeded, but the resistors connected from DP0/LO and DP1/HI to DGND will turn both annunciators off when the logic probe is unconnected. The TC820 logic inputs are not latched internally, so pulses of short duration will usually be difficult or impos- sible to see. T o display short pulses properly, the input pulse should be "stretched." The circuit of Figure 5-11 shows capacitors added across the input pull-down resistors to stretch the input pulse and permit viewing short duration input pulses. FIGURE 5-11: WINDOW COMPARATOR LOGIC PROBE TC820 RSTANDARD RUNKNOWN Analog Common VDD VREF+ VREF- VIN+ VIN- LCD TC820 DGND Frequency Input GND DGND 74HC14 RANGE/FREQ FREQ/VOLTS VDD1µF +9V VDD TC820 Logic Probe Input +9V *74HC14 LOGIC DP1/HI DP0/LO DGND VDD TC820 DP1/HI LOGIC DP0/LO DGND 1N4148 1N4148 +9V VL 1MΩ 1MΩ Logic Probe Input Note: Select R1, R2, R3 for desired logic thresholds. VH

 2002 Microchip Technology Inc. DS21476B-page 21 TC820

5.11 External Peak Detection

The TC820 will hold the highest A/D conversion or fre- quency reading indefinitely when the PKHOLD input is connected to V DD. However, the analog peak input must be present during the A/D converter's signal inte- grate period. For slowly changing signals, such as tem- perature, the peak reading will be properly converted and held. If rapidly changing analog signals must be held, an external peak detector should be added. An inexpensive circuit can be made from an op amp and a few discrete components, as shown in Figure 5-12. The droop rate of the external peak detector should be adjusted so that the held voltage will not decay below the desired accuracy level during the converter's 400msec conversion time. FIGURE 5-12: EXTERNAL PEAK DETECTOR

5.12 Liquid Crystal Display (LCD)

The TC820 drives a triplex (multiplexed 3:1) LCD with three backplanes. The LCD can include decimal points, polarity sign, and annunciators for over range, peak hold, high and low logic levels, and low battery. Table 5-2 shows the assignment of the display seg- ments to the backplanes and segment drive lines. The backplane drive frequency is obtained by dividing the oscillator frequency by 240. Backplane waveforms are shown in Figure 5-13. These appear on outputs BP1, BP2, and BP3. They remain the same, regardless of the segments being driven. FIGURE 5-13: BACKPLANE WAVEFORMS Other display output lines have waveforms that vary depending on the displays values. Figure 5-13 shows a set of waveforms for the a, g, d outputs of one digit for several combinations of "on" segments. FIGURE 5-14: TYPICAL DISPLAY OUTPUT WAVEFORMS TABLE 5-2: LCD BACKPLANE AND SEGMENT ASSIGNMENTS *Connect both pins 2 and 16 of LCD to TC820 BP3 of output. VDD TC820 VSS VIN+ PKHOLD 0.01µF Offset Null 1N4148 +9V 10kΩ VIN TL061 BP1 BP2 BP3 40-Pin (PDIP) 44-Pin (PQFP) LCD Display Pin Number BP1 BP2 BP3 14 0 3 L O W 24 1 4 A 4 " — " 3 42 5 B4 G4 E4 4 43 6 HIGH C4 D4 54 4 7 A 3 F 3 D P 3 61 8 B 3 G 3 E 3 7 2 9 OVER C3 D3 83 1 0 A 2 F 2 D P 2 9 4 11 B2 G2 E2 10 5 12 PEAK C2 D2 11 6 13 A1 F1 DP1 12 7 14 B1 G1 E1 13 8 2,16* — C1 D1 14 9 1 BP1 — BATT 15 10 15 LOW BP2 BP3 VDD VH VL VDISP VDD VH VL VDISP VDD VH VL VDISP VDD VH VL VDISP Segment Line All OFF a Segment ON d, g OFF a, g ON d OFF All ON

DS21476B-page 22  2002 Microchip Technology Inc.

5.13 LCD Source

Although most users will design their own custom LCD, a standard display for the TC820 (Figure 5-15), Part No. ST-1355-M1, is available from the following sources: Crystaloid (USA) Crystaloid Electronics P. O . B o x 6 28

5282 Hudson Drive

Hudson, OH 44238 Phone: 216-655-2429 Crystaloid (Europe) Rep. France 102, rue des Nouvelles F92150 Suresnes France FIGURE 5-15: TYPICAL TC820 LCD

5.14 Annunciator Output

The annunciator output is a square wave running at the backplane frequency (for example, 167Hz when F OSC = 40kHz). The peak-to-peak amplitude is equal to (VDD –V DISP). Connecting an annunciator of the LCD to the annunciator output turns it on; connecting it to its backplane turns it off.

5.15 LCD Drive Voltage (V DISP)

The peak-to-peak LCD drive voltage is equal to (V DD – VDISP). In the 40-pin dual in-line package (DIP), V DISP is internally connected to DGND, providing a typical LCD drive voltage of 5V P-P. For applications with a wide temperature range, some LCDs require that the drive levels vary with temperature to maintain good viewing angle and display contrast. In this case, the TC820 44-pin package provides a pin con- nection for V DISP. Figure 5-16 shows TC820 circuits that can be adjusted to give a temperature compensation of about 10mV/°C between V DD and V DISP. The diode between GND and VDISP should have a low turn on volt- age because VDISP cannot exceed 0.3V below GND.

5.16 Crystal Source

Two sources of the 40kHz crystal are: Statek Corp. 512 N. Main St. Orange, CA 92668 Phone: 714-639-7810 Fax: 714-997-1256 Part #: CX-1V-40.0 SPK Electronics 2F-1, No. 312, Sec, 4, Jen Ai Rd. Taipei, Taiwan R.O.C. Phone: (02) 754-2677 Fax: 886-2-708-4124 Part #: QRT-38-40.0kHz FIGURE 5-16: TEMPERATURE COMPENSATING CIRCUITS HIGH LOW OVER PEAK BATT PIN 1 VDISP TC820 DGND 200kΩ 39kΩ 5kΩ 75kΩ 1N4148 VDISP TC820 DGND 39kΩ 20kΩ 2N2222 18kΩ Note: Pin numbers shown are for 44-pin flat package. TL071 1 N5817 1N5817

 2002 Microchip Technology Inc. DS21476B-page 23 TC820

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

Package marking data not available at this time.

6.2 Taping Forms

Component Taping Orientation for 44-Pin PLCC Devices User Direction of Feed Standard Reel Component Orientation for TR Suffix Device Note: Drawing does not represent total number of pins. W P Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 44-Pin PLCC 32 mm 24 mm 500 13 in Carrier Tape, Number of Components Per Reel and Reel Size Component Taping Orientation for 44-Pin PQFP Devices User Direction of Feed PIN 1 Standard Reel Component Orientation for TR Suffix Device W P Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 44-Pin PQFP 24 mm 16 mm 500 13 in Carrier Tape, Number of Components Per Reel and Reel Size Note: Drawing does not represent total number of pins.

DS21476B-page 24  2002 Microchip Technology Inc.

6.3 Package Dimensions

2.065 (52.45) 2.027 (51.49) .200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .022 (0.56) .015 (0.38) .110 (2.79) .090 (2.29) .555 (14.10) .530 (13.46) .610 (15.49) .590 (14.99) .015 (0.38) .008 (0.20) .700 (17.78) .610 (15.50) .040 (1.02) .020 (0.51) 40-Pin PDIP (Wide) PIN 1 3° MIN. Dimensions: inches (mm) .695 (17.65) .685 (17.40) .656 (16.66) .650 (16.51) .656 (16.66) .650 (16.51) .021 (0.53) .013 (0.33) .032 (0.81) .026 (0.66) .630 (16.00) .591 (15.00) .120 (3.05) .090 (2.29) .180 (4.57) .165 (4.19) .695 (17.65) .685 (17.40) .050 (1.27) TYP. .020 (0.51) MIN. PIN 1 44-Pin PLCC Dimensions: inches (mm)

 2002 Microchip Technology Inc. DS21476B-page 25 TC820

6.3 Package Dimensions (Continued)

Dimensions: inches (mm) .557 (14.15) .537 (13.65) .398 (10.10) .390 (9.90) .031 (0.80) TYP. .018 (0.45) .390 (9.90) .010 (0.25) TYP. .096 (2.45) MAX. .557 (14.15) .537 (13.65) .083 (2.10) .075 (1.90) .041 (1.03) .026 (0.65) 7° MAX. .009 (0.23) .005 (0.13) 44-Pin PQFP PIN 1

DS21476B-page 26  2002 Microchip Technology Inc. SALES AND SUPPORT Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom- mended workarounds. T o determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

 2002 Microchip Technology Inc. DS21476B-page 27 TC820 Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip T echnology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical com- ponents in life support systems is not authorized except with express written approval by Microchip. No licenses are con- veyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, K EELOQ,m i c r o I D ,M P L A B ,P I C ,P I C m i c r o ,P I C M A S T E R , PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Tech- nology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro ® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.

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No. 11, O’Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 Japan Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd.

200 Middle Road

#07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUROPE Denmark Microchip Technology Nordic ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 France Microchip Technology SARL Parc d’Activite du Moulin de Massy

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91300 Massy, France

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20041 Agrate Brianza

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