TC7650_13 MICROCHIP | Alldatasheet
Document overview
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Technical content
Features
- Low Input Offset Voltage: 0.7µV Typ
- Low Input Offset Voltage Drift: 0.05V/°C Max
- Low Input Bias Current: 10pA Max
- High Impedance Differential CMOS Inputs: 10 12
- High Open Loop Voltage Gain: 120dB Min.
- Low Input Noise Voltage: 2.0Vp-p
- High Slew Rate: 2.5V/ sec.
- Low Power Operation: 20mW
- Output Clamp Speeds Recovery Time
- Compensated Internally for Stable Unity Gain Operation
- Direct Replacement for ICL7650
- Available in 8-Pin Plastic DIP and 14-Pin Plastic DIP Packages
Applications
- Instrumentation
- Medical Instrumentation
- Embedded Control
- Temperature Sensor Amplifier
- Strain Gage Amplifier Device Selection Table Package Type Part Number Package Temperature Range Max VOS TC7650CPA 8-Pin PDIP 0°C to +70°C 5 V TC7650CPD 14-Pin PDIP 0°C to +70°C 5 V C B NC 8-Pin DIP VSS VSS INT/EXT EXT CLK IN INT CLK OUT OUTPUT OUTPUT CLAMP CA CRETN VDDTC7650CPD CA OUTPUT VDD TC7650CPA INPUT INPUT CB OUTPUT CLAMP INPUT– INPUT+ NC 14-Pin DIP NC = NO INTERNAL CONNECTION TC7650 Chopper Stabilized Operational Amplifier
DS21463C-page 2 2001-2012 Microchip Technology Inc. General Description The TC7650 CMOS chopper stabilized operational amplifier practically removes offset voltage error terms from system error calculations. The 5V maximum VOS specification, for example, represents a 15 times improvement over the industry standard OP07E. The 50nV/°C offset drift specification is over 25 times lower than the OP07E. The increased performance elimi- nates V OS trim procedures, periodic potentiometer adjustment and the reliability problems caused by dam- aged trimmers. The TC7650 performance advantages are achieved without the additional manufacturing complexity and cost incurred with laser or "zener zap" V OS trim tech- niques. The TC7650 nulling scheme corrects both DC V OS errors and VOS drift errors with temperature. A nulling amplifier alternately corrects its own VOS errors and the main amplifier V OS error. Offset nulling voltages are stored on two user supplied external capacitors. The capacitors connect to the internal amplifier V OS null points. The main amplifier input signal is never switched. Switching spikes are not present at the TC7650 output. The 14-pin dual-in-line package (DIP) has an external oscillator input to drive the nulling circuitry for optimum noise performance. Both the 8 and 14-pin DIPs have an output voltage clamp circuit to minimize overload recovery time. Functional Block Diagram TC7650 Null NULL Inputs Output Clamp Output BB A CA CB For 8-Pin DIP , connect to Vss Null Amplifier Main Amplifier Output Clamp Circuit Intermod Compensation Oscillator AB INT/EXT EXT CLK IN CLK OUT 14-Pin DIP Only BA *CRETN
2001-2012 Microchip Technology Inc. DS21463C-page 3 TC7650
1.0 ELECTRICAL
ABSOLUTE MAXIMUM RATINGS* Package Power Dissipation (TA 70°C) Operating Temperature Range *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indi- cated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods my affect device reliability. TC7652 ELECTRICAL SPECIFICATIONS Electrical Characteristics: VDD = +5V, VSS = -5V, CA = CB = 0.1F, TA = +25°C, unless otherwise indicated. Symbol Parameter Min. Typ Max Units Test Conditions Input VOS Input Offset Voltage — ±0.7 ±1.0 TA = +25°C Over Operating Temp Range VOS/T Input Offset Voltage Average Temperature Coefficient —0 . 0 1 0 . 0 5 V/°C Operating Temperature Range Offset Voltage vs. Time — 100 — nV/ month IBIAS Input Bias Current — 1.5 100 150 400 pA pA pA TA = +25°C 0°C TA +70°C -25°C TA +85°C IOS Input Offset Current — 0.5 — pA eNP-P Input Noise Voltage — 2 — VP-P RS = 100, 0 to 10Hz IN Input Noise Current — 0.01 —p A / Hz f = 10Hz RIN Input Resistance — 10 12 CMVR Common Mode Voltage Range -5 -5.2 to +2 +1.6 V CMRR Common Mode Rejection Ratio 120 130 — dB CMVR = -5V to +1.5V Output A Large Signal Voltage Gain 120 130 — dB R L = 10k VOUT Output Voltage Swing (Note 2)± 4 . 7 ±4.85 ±4.95 V V RL = 10k RL = 100k Clamp ON Current 25 70 200 AR L = 100k (Note 1) Clamp OFF Current — 1 — pA -4V < V OUT < +4V (Note 1) Dynamic B W Unity Gain Bandwidth — 2.0 — MHz Unity Gain (+1) SR Slew Rate — 2.5 — V/ sec C L = 50pF, RL = 10k tR Rise Time — 0.2 — sec Overshoot — 20 — % fCH Internal Chopping Frequency 120 200 375 Hz Pins 12–14 Open (DIP) Supply V DD, VSS Operating Supply Range 4.5 — 16 V IS Supply Current — 2 3.5 mA No Load PSRR Power Supply Rejection Ratio 120 130 dB V S = ±3V to ±8V Note 1: See "Output Clamp" discussion. 2: Output clamp not connected. See typical characteristics curves for output swing versus clamp current characteristics. 3: Limiting input current to 100A is recommended to avoid latch-up problems.
DS21463C-page 4 2001-2012 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE
3.0 DETAILED DESCRIPTION
3.1 Theory of Operation
Figure 3-1 shows the major elements of the TC7650. There are two amplifiers (the main amplifier and the nulling amplifier), and both have offset null capability. The main amplifier is connected full-time from the input to the output. The nulling amplifier, under the control of the chopping frequency oscillator and clock circuit, alternately nulls itself and the main amplifier. Two exter- nal capacitors provide the required storage of the null- ing potentials and the necessary nulling loop time constants. The nulling arrangement operates over the full common mode and power supply ranges, and is also independent of the output level, thus giving excep- tionally high CMRR, PSRR and A VOL. Careful balancing of the input switches minimizes chopper frequency charge injection at the input termi- nals, and the feed forward type injection into the com- pensation capacitor that can cause output spikes in this type of circuit. The circuit's offset voltage compensation is easily shown. With the nulling inputs shorted, a voltage almost identical to the nulling amplifier offset voltage is stored on C A. The effective offset voltage at the null amplifier input is: EQUATION 3-1: After the nulling amplifier is zeroed, the main amplifier is zeroed; the A switches open and B switches close. The output voltage equation is: EQUATION 3-2: EQUATION 3-3: As desired, the device offset voltages are reduced by the high open loop gain of the nulling amplifier.
3.2 Output Stage/Loading
The output circuit is a high impedance stage (approxi- mately 18k). With loads less than this, the chopper amplifier behaves in some ways like a trans-conduc- tance amplifier whose open-loop gain is proportional to load resistance. For example, the open loop gain will be 17dB lower with a 1k load than with a 10k load. If the amplifier is used strictly for DC, the lower gain is of little consequence, since the DC gain is typically greater than 120dB, even with a 1k load. In wideband applications, the best frequency response will be achieved with a load resistor of 10k or higher. This results in a smooth 6dB/octave response from 0.1Hz to 2MHz, with phase shifts of less than 10° in the transi- Pin Number Symbol Description 8-pin DIP 14-pin DIP 1,8 2,1 C A, CB Nulling capacitor pins 2 4 -INPUT Inverting Input 3 5 +INPUT Non-inverting Input
47 V SS Negative Power Supply
59 O U T P U T
61 0 O U T P U T O u t p u t 71 1 V DD Positive Power Supply — 3,6 NC No internal connection —8C RETN Capacitor current return pin — 12 INT CLK OUT Internal Clock Output — 13 EXT CLK IN External Clock Input — 14 INT/EXT Select Internal or External Clock VOSE VOUT = AMVOSM + (V+ - V-) + AN(V+ - V-) + AN VOSE VOUT AMAN V+ V-– VOSM VOSN+ AN
2001-2012 Microchip Technology Inc. DS21463C-page 5 TC7650 tion region, where the main amplifier takes over from the null amplifier. The clock frequency sets the transi- tion region.
3.3 Intermodulation
Previous chopper stabilized amplifiers have suffered from intermodulation effects between the chopper fre- quency and input signals. These arise because the finite AC gain of the amplifier results in a small AC sig- nal at the input. This is seen by the zeroing circuit as an error signal, which is chopped and fed back, thus inject- ing sum and difference frequencies, and causing dis- turbances to the gain and phase versus frequency characteristics near the chopping frequency. These effects are substantially reduced in the TC7650 by feeding the nulling circuit with a dynamic current corre- sponding to the compensation capacitor current in such a way as to cancel that portion of the input signal due to a finite AC gain. The intermodulation and gain/phase disturbances are held to very low values, and can gen- erally be ignored. FIGURE 3-1: TC7650 CONTAINS A NULLING AND MAIN AMPLIFIER. OFFSET CORRECTION VOLTAGES ARE STORED ON TWO EXTERNAL CAPACITORS FIGURE 3-2: NULLING CAPACITOR CONNECTION
3.4 Nulling Capacitor Connection
The offset voltage correction capacitors are connected to C A and C B. The common capacitor connection is made to V SS (Pin 4) on the 8-pin packages and to capacitor return (CRETN, Pin 8) on the 14-pin packages. The common connection should be made through a separate PC trace or wire to avoid voltage drops. The capacitors outside foil, if possible, should be connected to C RETN or VSS.
3.5 Clock Operation
The internal oscillator is set for a 200Hz nominal chop- ping frequency on both the 8- and 14-pin DIPs. With the 14-pin DIP TC7650, the 200 Hz internal chopping fre- quency is available at the internal clock output (Pin 12). A 400Hz nominal signal will be present at the external clock input pin (Pin 13) with INT/EXT high or open. This is the internal clock signal before a divide-by-two oper- ation. The 14-pin DIP device can be driven by an external clock. The INT/EXT input (Pin 14) has an internal pull- up and may be left open for internal clock operation. If an external clock is used, INT/EXT must be tied to VSS (Pin 7) to disable the internal clock. The external clock signal is applied to the external clock input (Pin 13). The external clock amplitude should swing between V DD and ground for power supplies up to ±6V and between V+ and V+ -6V for higher supply voltages. At low frequencies the external clock duty cycle is not critical, since an internal divide-by-two gives the desired 50% switching duty cycle. The offset storage correction capacitors are charged only when the exter- nal clock input is high. A 50% to 80% external clock Null Main Amplifier Null Amplifier Gain = AM B A B A + CB CA TC7650 Null Gain = AN , Offset = VOSN VOUTAnalog Input VDD VSS 2 7 CA CB VDD TC7650 4 11 CA CB VSS 14-PIN PACKAGE 8-PIN PACKAGE TC7650 - -
DS21463C-page 6 2001-2012 Microchip Technology Inc. positive duty cycle is desired for frequencies above 500Hz to ensure transients settle before the internal switches open. The external clock input can also be used as a strobe input. If a strobe signal is connected at the external clock input so that it is LOW during the time an overload signal is applied, neither capacitor will be charged. The leakage currents at the capacitors pins are very low. At 25°C a typical TC7650 will drift less than 10V/sec.
3.6 Output Clamp
Chopper-stabilized systems can show long recovery times from overloads. If the output is driven to either supply rail, output saturation occurs. The inputs are no longer held at a "virtual ground." The V OS null circuit treats the differential signal as an offset and tries to cor- rect it by charging the external capacitors. The nulling circuit also saturates. Once the input signal returns to normal, the response time is lengthened by the long recovery time of the nulling amplifier and external capacitors. Through an external clamp connection, the TC7650 eliminates the overload recovery problem by reducing the feedback network gain before the output voltage reaches either supply rail. FIGURE 3-3: INTERNAL CLAMP CIRCUIT FIGURE 3-4: NON-INVERTING AMPLIFIER WITH OPTIONAL CLAMP FIGURE 3-5: INVERTING AMPLIFIER WITH OPTIONAL CLAMP The output clamp circuit is shown in Figure 3-3, with typical inverting and non-inverting circuit connections shown in Figures 3-4 and 3-5. Output voltage versus clamp circuit current characteristics are shown in the typical operating curves. For the clamp to be fully effec- tive, the impedance across the clamp output should be greater than 100k.
3.7 Latch-Up Avoidance
Junction-isolated CMOS circuits inherently include a parasitic 4-layer (p-n-p-n) structure which has charac- teristics similar to an SCR. Under certain circum- stances this junction may be triggered into a low- impedance state, resulting in excessive supply current. To avoid this condition, no voltage greater than 0.3V beyond the supply rails should be applied to any pin. In general, the amplifier supplies must be established either at the same time or before any input signals are applied. If this is not possible, the drive circuits must limit input current flow to under 0.1mA to avoid latch- up.
3.8 Thermoelectric Potentials
Precision DC measurements are ultimately limited by thermoelectric potentials developed in thermocouple junctions of dissimilar metals, alloys, silicon, etc. Unless all junctions are at the same temperature, ther- moelectric voltages, typically around 0.1 V/°C, but up to tens of V/°C for some materials, will be generated. In order to realize the benefits extremely-low offset volt- ages provide, it is essential to take special precautions to avoid temperature gradients. All components should be enclosed to eliminate air movement, especially those caused by power dissipating elements in the sys- tem. Low thermoelectric co-efficient connections should be used where possible and power supply volt- ages and power dissipation should be kept to a mini- mum. High impedance loads are preferable, and separation from surrounding heat dissipating elements is advised. Internal Positive Clamp Bias ≈ V+ - VT ≈ V+ - 0.7 P-Channel Output Clamp Pin N-Channel TC7650 C R C Output Input For Full Clamp Effect R1R3 + (R1/R2) ‡ 100 kΩ 0.1µFConnect To VSS On 8-Pin DIP. R Clamp TC7650 Clamp C R C Output 0.1 Fµ0.1 Fµ Input For Full Clamp Effect Connect To VR On 8-Pin DIP. * – (R1 R2) ‡ 100 kΩ
2001-2012 Microchip Technology Inc. DS21463C-page 7 TC7650
3.9 Pin Compatibility
On the 8-pin mini-DIP TC7650, the external null stor- age capacitors are connected to pins 1 and 8. On most other operational amplifiers these are left open or are used for offset potentiometer or compensation capaci- tor connections. For OP05 and OP07 operational amplifiers, the replacement of the offset null potentiometer between pins 1 and 8 by two capacitors from the pins to V SS will convert the OP05/07 pin configurations for TC7650 operation. For LM108 devices, the compensation capacitor is replaced by the external nulling capacitors. The LM101/748/709 pinouts are modified similarly by removing any circuit connections to Pin 5. On the TC7650, Pin 5 is the output clamp connection. Other operational amplifiers may use this pin as an off- set or compensation point. The minor modifications needed to retrofit a TC7650 into existing sockets operating at reduced power sup- ply voltages make prototyping and circuit verification straightforward.
3.10 Input Guarding
High impedance, low leakage CMOS inputs allow the TC7650 to make measurements of high-impedance sources. Stray leakage paths can increase input cur- rents and decrease input resistance unless inputs are guarded. A guard is a conductive PC trace surrounding the input terminals. The ring connects to a low imped- ance point at the same potential as the inputs. Stray leakages are absorbed by the low impedance ring. The equal potential between ring and inputs prevents input leakage currents. Typical guard connections are shown in Figure 3-6. The 14-pin DIP configuration has been specifically designed to ease input guarding. The pins adjacent to the inputs are unused. In applications requiring low leakage currents, boards should be cleaned thoroughly and blown dry after sol- dering. Protective coatings will prevent future board contamination.
3.11 Component Selection
The two required capacitors, CA and CB, have optimum values, depending on the clock or chopping frequency. For the preset internal clock, the correct value is 0.1F. To maintain the same relationship between the chop- ping frequency and the nulling time constant, the capacitor values should be scaled in proportion to the external clock, if used. High quality film type capacitors (such as Mylar) are preferred; ceramic or other lower grade capacitors may be suitable in some applications. For fast settling on initial turn-on, low dielectric absorp- tion capacitors (such as polypropylene) should be used. With ceramic capacitors, several seconds may be required to settle to 1V. FIGURE 3-6: INPUT GUARD CONNECTION Input + Output Inverting Amplifier Input + Output Follower Input + Output Noninverting Amplifier R3* R3* Should Be Low Impedence For Optimum Guarding NOTE: R3 = R1 R2 R1 + R2 R3*
DS21463C-page 8 2001-2012 Microchip Technology Inc.
4.0 TYPICAL CHARACTERISTICS
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. OUTPUT VOLTAGE (V) Positive Clamp Current vs. Output Voltage CLAMP CURRENT 1 mA 0.1 mA 0.01 mA 1 Am 0.1 A 0.01 A m 1 nA 1 pA 0.01 nA 0.1 nA m OUTPUT VOLTAGE (V) Negative Clamp Current vs. Output Voltage CLAMP CURRENT 3.0 2.6 2.2 1.8 1.0 1.4 5 6 7 8 9 1 01 11 21 31 41 5 SUPPLY VOLTAGE (V) Supply Current vs. Supply Voltage SUPPLY CURRENT (mA) Gain/Phase vs. Frequency –10 –20 –30 –40 –50 –60 1k 10k 100k 1M 10M GAIN (dB) 225 180 135 -45 -90 -135 -180 FREQUENCY (H )z PHASE (deg) 1 mA 0.1 mA 0.01 mA 1 Am 0.1 A 0.01 A m 1 nA 1 pA 0.01 nA 0.1 nA m CLOSED-LOOP GAIN = 20 PHASE GAIN TA = +25˚C VS = ±5V TA = +25˚C VS = ±5V TA = +25˚C
2001-2012 Microchip Technology Inc. DS21463C-page 9 TC7650
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
Package marking information not available at this time.
5.2 Package Dimensions
3˚MIN. PIN 1 .260 (6.60) .240 (6.10) .045 (1.14) .030 (0.76) .070 (1.78) .040 (1.02) .400 (10.16) .348 (8.84) .200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) .110 (2.79) .090 (2.29) .022 (0.56) .015 (0.38) .040 (1.02) .008 (0.20) .310 (7.87) .290 (7.37) .400 (10.16) .310 (7.87) 8-Pin Plastic DIP Dimensions: inches (mm) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging .260 (6.60) .240 (6.10) .770 (19.56) .745 (18.92) .310 (7.87) .290 (7.37) .040 (1.02) .020 (0.51) .070 (1.78) .045 (1.14) .022 (0.56) .015 (0.38) .110 (2.79) .090 (2.29) .200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) PIN 1 14-Pin PDIP (Narrow) .015 (0.38) .008 (0.20) 3˚MIN. .400 (10.16) .310 (7.87) Dimensions: inches (mm) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
DS21463C-page 10 2001-2012 Microchip Technology Inc.
6.0 REVISION HISTORY
Revision C (December 2012) Added a note to each package outline drawing.
2001-2012 Microchip Technology Inc. DS21463C-page 11 TC7650 SALES AND SUPPORT Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
DS21463C-page 12 2001-2012 Microchip Technology Inc. NOTES:
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