TC7109 MICROCHIP | Alldatasheet

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© 2006 Microchip Technology Inc. DS21456C-page 1 TC7109/A Features:

  • Zero Integrator Cycle for Fast Recovery from Input Overloads
  • Eliminates Cross-Talk in Multiplexed Systems
  • 12-Bit Plus Sign Integrating A/D Converter with Over Range Indication
  • Sign Magnitude Coding Format
  • True Differential Signal Input and Differential Reference Input
  • Low Noise: 15μVP-P Typ.
  • Input Current: 1pA Typ.
  • No Zero Adjustment needed
  • TTL Compatible, Byte Organized Tri-State Outputs
  • UART Handshake Mode for simple Serial Data Transmissions Device Selection Table *The “A” version has a higher IOUT on the digital lines. General Description: The TC7109A is a 12-bit plus sign, CMOS low power Analog-to-Digital Converter (ADC). Only eight passive components and a crystal are required to form a complete dual slope integrating ADC. The improved VOH source current and other TC7109A features make it an attractive per-channel alternative to analog multiplexing for many data acquisition applica- tions. These features include typical input bias current of 1pA, drift of less than 1μV/°C, input noise typically 15μVP-P, and auto-zero. True differential input and ref- erence allow measurement of bridge type transducers, such as load cells, strain gauges and temperature transducers. The TC7109A provides a versatile digital interface. In the Direct mode, Chip Select and HIGH/LOW byte enable control parallel bus interface. In the Handshake mode, the TC7109A will operate with industry standard UARTs in controlling serial data transmission – ideal for remote data logging. Control and monitoring of conver- sion timing is provided by the RUN/HOLD input and Status output. For applications requiring more resolution, see the TC500, 15-bit plus sign ADC data sheet. The TC7109A has improved over range recovery performance and higher output drive capability than the original TC7109. All new (or existing) designs should specify the TC7109A wherever possible. Part Number (TC7109X)* Package Temperature Range TC7109CKW 44-Pin PQFP 0°C to +70°C TC7109CLW 44-Pin PLCC 0°C to +70°C TC7109CPL 40-Pin PDIP 0°C to +70°C TC7109IJL 40-Pin CERDIP -25°C to +85°C 12-Bit μA-Compatible Analog-to-Digital Converters

© 2006 Microchip Technology Inc. Package Type NC = No internal connection TC7109A TC7109 STATUS POL OR TEST LBEN HBEN CE/LOAD REF OUT IN HI IN LO COMMON SEND RUN/HOLD BUFF OSC OUT OSC SEL OSC IN MODE GND OSC OUT BUFF AZ INT REF IN+ REF CAP+ REF CAP- REF IN- B12 B11 B10 INT IN HI 12 13 14 15 17 18 BUFF OSC OUT AZ NC BUFF 44 43 42 41 39 38 GND 37 36 35 34 19 20 21 22 REF OUT SEND NC TC7109ACKW TC7109CKW 44-Pin PQFP 44-Pin PLCC 40-Pin PDIP/CERDIP RUN/HOLD COMMON IN LO REF IN+ REF CAP+ REF CAP- REF IN- STATUS POL OR B11 B10 NC OSC SEL OSC OUT OSC IN MODE NC CE/LOAD HBEN LBEN TEST B12 INT IN HI 18 19 20 21 23 24 BUFF OSC OUT AZ NC BUFF GND 43 42 41 40 25 26 27 28 REF OUT SEND NC TC7109ACLW TC7109CLW RUN/HOLD COMMON IN LO REF IN+ REF CAP+ REF CAP- REF IN- STATUS POL OR B11 B10 NC OSC SEL OSC OUT OSC IN MODE NC CE/LOAD HBEN LBEN TEST B12

© 2006 Microchip Technology Inc. DS21456C-page 3 TC7109/A Typical Application Input High AZ BUFF CAZ INT Buffer Integrator AZ ZI AZ ZI DE (+) AZ INT AZ Comparator Comp Out CREF AZ DE (±) ZI Common Input Low INT REF IN+ DE (–) DE (–) DE (+) RINT CINT REF CAP- REF CAP+ ZI 6.2V 10mA REF OUT 9 10 11 12 13 14 To Analog Section Comp Out AZ INT DE (±) ZI Conversion Control Logic Oscillator and Clock Circuitry Handshake Logic 15 16 LBEN HBEN CE/LOAD GND

14 Latches

16 Three-State Outputs

© 2006 Microchip Technology Inc. 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings* Analog Input Voltage (Low to High) (Note 1).... V+ to V- Reference Input Voltage: Digital Input Voltage: Power Dissipation, TA < 70°C (Note 3) Operating Temperature Range *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. TC7109/TC7109A ELECTRICAL SPECIFICATIONS Electrical Characteristics: All parameters with V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, unless otherwise indicated. Symbol Parameter Min Typ Max Unit Test Conditions Analog Overload Recovery Time (TC7109A) Measurement Cycle Zero Input Reading -00008 ±00008 +00008 Octal Reading VIN = 0V; Full Scale = 409.6mV Ratio Metric Reading 37778 37778 40008 40008 Octal Reading VIN = VREF VREF = 204.8mV NL Non-Linearity (Max Deviation from Best Straight Line Fit) ±0.2 Count Full Scale = 409.6mV to 2.048V Over Full Operating Temperature Range Rollover Error (Difference in Reading for Equal Positive and Inputs near (Full Scale) ±0.02 Count Full Scale = 409.6mV to 2.048V Over Full Operating Temperature Range CMRR Input Common Mode Rejection Ratio μV/V VCM ±1V, VIN = 0V Full Scale = 409.6mV VCMR Common Mode Voltage Range V- +1.5 V+ -1.5 V Input High, Input Low and Common Pins eN Noise (P-P Value Not Exceeded 95% of Time) μV VIN = 0V, Full Scale = 409.6mV IIN Leakage Current at Input pA VIN, All Packages: +25°C 100 pA C Device: 0°C ≤ TA ≤ +70°C 100 250 pA I Device: -25°C ≤ TA ≤ +85°C TCZS Zero Reading Drift 0.2 μV/°C VIN = 0V Note Input voltages may exceed supply voltages if input current is limited to ±100μA. Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device latch-up. Therefore, it is recommended that inputs from sources other than the same power supply should not be applied to the TC7109A before its power supply is established. In multiple supply systems, the supply to the device should be activated first. This limit refers to that of the package and will not occur during normal operation.

© 2006 Microchip Technology Inc. DS21456C-page 5 TC7109/A TCFS Scale Factor Temperature Coefficient μV/°C VIN = 408.9mV = >77708 Reading, Ext Ref = 0ppm/°C Supply Current (V+ to GND) 700 1500 μA VIN = 0V, Crystal Oscillator 3.58MHz Test Circuit IS Supply Current (V+ to V-) 700 1500 μA Pins 2-21, 25, 26, 27, 29 Open VREF Reference Out Voltage -2.4 -2.8 -3.2 V Referenced to V+, 25kΩ Between V+ and Ref Out TCREF Ref Out Temperature Coefficient ppm/°C 25kΩ Between V+ and Ref Out 0°C ≤ TA ≤ +70°C Digital VOH Output High Voltage IOUT = 700μA 3.5 4.3 V TC7109: IOUT = 100μA Pins 3 -16, 18, 19, 20 TC7109A: IOUT = 700μA VOL Output Low Voltage 0.2 0.4 μA IOUT = 1.6mA Output Leakage Current ±0.01 μA Pins 3 -16 High-Impedance Control I/O Pull-up Current μF Pins 18, 19, 20 VOUT = V+ – 3V Mode Input at GND Control I/O Loading pF HBEN, Pin 19; LBEN, Pin 18 VIH Input High Voltage 2.5 V Pins 18 -21, 26, 27 Referenced to GND VIL Input Low Voltage V Pins 18-21, 26, 27 Referenced to GND Input Pull-up Current μA μA Pins 26, 27; VOUT = V+ – 3V Pins 17, 24; VOUT = V+ – 3V Input Pull-down Current μA Pins 21, VOUT = GND = +3V Oscillator Output Current, High mA VOUT – 2.5V Oscillator Output Current, Low 1.5 mA VOUT – 2.5V Buffered Oscillator Output Current High mA VOUT – 2.5V Buffered Oscillator Output Current Low mA VOUT – 2.5V tW Mode Input Pulse Width nsec HANDLING PRECAUTIONS: These devices are CMOS and must be handled correctly to prevent damage. Package and store only in conductive foam, antistatic tubes, or other conducting material. Use proper antistatic handling pro- cedures. Do not connect in circuits under “power-on” conditions, as high transients may cause permanent damage. TC7109/TC7109A ELECTRICAL SPECIFICATIONS (Continued) Electrical Characteristics: All parameters with V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, unless otherwise indicated. Symbol Parameter Min Typ Max Unit Test Conditions Note Input voltages may exceed supply voltages if input current is limited to ±100μA. Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device latch-up. Therefore, it is recommended that inputs from sources other than the same power supply should not be applied to the TC7109A before its power supply is established. In multiple supply systems, the supply to the device should be activated first. This limit refers to that of the package and will not occur during normal operation.

© 2006 Microchip Technology Inc. 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number (40-Pin PDIP) Symbol

Description

Digital ground, 0V, ground return for all digital logic. STATUS Output HIGH during integrate and de-integrate until data is latched. Output LOW when analog section is in auto-zero or zero integrator configuration. POL Polarity – High for positive input. OR Over Range – High if over ranged (Three-State Data bit). B12 Bit 12 (Most Significant bit) (Three-State Data bit). B11 Bit 11 (Three-State Data bit). B10 Bit 10 (Three-State Data bit). Bit 9 (Three-State Data bit). Bit 8 (Three-State Data bit). Bit 7 (Three-State Data bit). Bit 6 (Three-State Data bit). Bit 5 (Three-State Data bit). Bit 4 (Three-State Data bit). Bit 3 (Three-State Data bit). Bit 2 (Three-State Data bit). Bit 1 (Least Significant bit) (Three-State Data bit). TEST Input High – Normal operation. Input LOW – Forces all bit outputs HIGH. Note: This input is used for test purposes only. LBEN Low Byte Enable – with MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin LOW activates low order byte outputs, B1–B8. With MODE (Pin 21) HIGH, this pin serves as low byte flag output used in Handshake mode. (See Figure 3-7, Figure , and Figure 3-9.) HBEN High Byte Enable – with MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin LOW activates high order byte outputs, B9–B12, POL, OR. With MODE (Pin 21) HIGH, this pin serves as high byte flag output used in Handshake mode. See Figures 3-7, 3-8, and 3-9. CE/LOAD Chip Enable/Load – with MODE (Pin 21) LOW, CE/LOAD serves as a master output enable. When HIGH, B1–B12, POL, OR outputs are disabled. When MODE (Pin 21) is HIGH, a load strobe is used in handshake mode. (See Figure 3-7, Figure , and Figure 3-9.) MODE Input LOW – Direct Output mode where CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18) act as inputs directly controlling byte outputs. Input Pulsed HIGH - Causes immediate entry into Handshake mode and output of data as in Figure 3-9. Input HIGH – enables CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18) as outputs, Handshake mode will be entered and data output as in Figure 3-7 and Figure 3-9 at conversions completion. OSC IN Oscillator Input. OSC OUT Oscillator Output. OSC SEL Oscillator Select – Input HIGH configures OSC IN, OSC OUT, BUFF OSC OUT as RC oscillator – clock will be same phase and duty cycle as BUFF OSC OUT. Input LOW configures OSC IN, OSC OUT for crystal oscillator - clock frequency will be 1/58 of frequency at BUFF OSC OUT. BUFF OSC OUT Buffered Oscillator Output. RUN/HOLD Input HIGH – Conversions continuously performed every 8192 clock pulses. Input LOW – Conversion in progress completed; converter will stop in auto-zero seven counts before integrate. SEND Input - Used in Handshake mode to indicate ability of an external device to accept data. Connect to V+ if not used. Analog Negative Supply – Nominally -5V with respect to GND (Pin 1). REF OUT Reference Voltage Output – Nominally 2.8V down from V+ (Pin 40).

© 2006 Microchip Technology Inc. DS21456C-page 7 TC7109/A Note: All Digital levels are positive true. BUFF Buffer Amplifier Output. AZ Auto-Zero Node – Inside foil of CAZ. INT Integrator Output – Outside foil of CINT. COMMON Analog Common – System is auto-zeroed to COMMON. IN LO Differential Input Low Side. IN HI Differential Input High Side. REF IN+ Differential Reference Input Positive. REF CAP+ Reference Capacitor Positive. REF CAP- Reference Capacitor Negative. REF IN- Differential Reference Input Negative. Positive Supply Voltage – Nominally +5V with respect to GND (Pin 1). TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin Number (40-Pin PDIP) Symbol

© 2006 Microchip Technology Inc. 3.0 DETAILED DESCRIPTION (All Pin Designations Refer to 40-Pin DIP.) 3.1 Analog Section The Typical Application diagram on page 3 shows a block diagram of the analog section of the TC7109A. The circuit will perform conversions at a rate deter- mined by the clock frequency (8192 clock periods per cycle), when the RUN/HOLD input is left open or connected to V+. Each measurement cycle is divided into four phases, as shown in Figure 3-1. They are: (1) Auto-Zero (AZ), (2) Signal Integrate (INT), (3) Reference De-integrate (DE), and (4) Zero Integrator (ZI). 3.1.1 AUTO-ZERO PHASE The buffer and the integrator inputs are disconnected from input high and input low and connected to analog common. The reference capacitor is charged to the ref- erence voltage. A feedback loop is closed around the system to charge the auto-zero capacitor, CAZ, to com- pensate for offset voltage in the buffer amplifier, inte- grator, and comparator. Since the comparator is included in the loop, the AZ accuracy is limited only by the noise of the system. The offset referred to the input is less than 10μV. 3.1.2 SIGNAL INTEGRATE PHASE The buffer and integrator inputs are removed from com- mon and connected to input high and input low. The auto-zero loop is opened. The auto-zero capacitor is placed in series in the loop to provide an equal and opposite compensating offset voltage. The differential voltage between input high and input low is integrated for a fixed time of 2048 clock periods. At the end of this phase, the polarity of the integrated signal is determined. If the input signal has no return to the converter’s power supply, input low can be tied to analog common to establish the correct Common mode voltage. 3.1.3 DE-INTEGRATE PHASE Input high is connected across the previously charged reference capacitor and input low is internally connected to analog common. Circuitry within the chip ensures the capacitor will be connected with the correct polarity to cause the integrator output to return to the zero crossing (established by auto-zero), with a fixed slope. The time, represented by the number of clock periods counted for the output to return to zero, is proportional to the input signal. 3.1.4 ZERO INTEGRATOR PHASE The ZI phase only occurs when an input over range condition exists. The function of the ZI phase is to eliminate residual charge on the integrator capacitor after an over range measurement. Unless removed, the residual charge will be transferred to the auto-zero capacitor and cause an error in the succeeding conversion. The ZI phase virtually eliminates hysteresis, or “cross- talk” in multiplexed systems. An over range input on one channel will not cause an error on the next channel measured. This feature is especially useful in thermo- couple measurements, where unused (or broken thermocouple) inputs are pulled to the positive supply rail. During ZI, the reference capacitor is charged to the ref- erence voltage. The signal inputs are disconnected from the buffer and integrator. The comparator output is connected to the buffer input, causing the integrator output to be driven rapidly to 0V (Figure 3-1). The ZI phase only occurs following an over range and lasts for a maximum of 1024 clock periods. 3.1.5 DIFFERENTIAL INPUT The TC7109A has been optimized for operation with analog common near digital ground. With +5V and -5V power supplies, a full ±4V full scale integrator swing maximizes the analog section’s performance. A typical CMRR of 86dB is achieved for input differen- tial voltages anywhere within the typical Common mode range of 1V below the positive supply, to 1.5V above the negative supply. However, for optimum per- formance, the IN HI and IN LO inputs should not come within 2V of either supply rail. Since the integrator also swings with the Common mode voltage, care must be exercised to ensure the integrator output does not sat- urate. A worst-case condition is near a full scale nega- tive differential input voltage with a large positive Common mode voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive Common mode volt- age. In such cases, the integrator swing can be reduced to less than the recommended ±4V full scale value, with some loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity.

© 2006 Microchip Technology Inc. FIGURE 3-1: Conversion Timing (RUN/HOLD) Pin High FIGURE 3-2: Digital Section Internal Clock Integrator Output for Normal Input Integrator Saturates Internal Latch Integrator Output for Over Range Input No Zero Crossing ZI AZ Zero Integrator Phase forces Integrator Output to 0V Zero Crossing Occurs Zero Crossing Detected INT Phase II Status Output AZ Phase I DE Phase III AZ Fixed 2048 Counts 2048 Counts Min. 4096 Counts Max Number of Counts to Zero Crossing Proportional to VIN After Zero Crossing, Analog section will be in Auto-Zero Configuration TEST POL OR B B B B B B B B B B STATUS RUN/ HOLD OSC IN OSC OUT OSC SEL BUFF OSC OUT MODE To Analog Section COMP OUT AZ INT DE (±) ZI Conversion Control Logic Oscillator and Clock Circuitry High Order Byte Outputs Low Order Byte Outputs Handshake Logic B B SEND LBEN HBEN CE/LOAD GND

14 Three-State Outputs

© 2006 Microchip Technology Inc. DS21456C-page 11 TC7109/A FIGURE 3-3: TC7109A RUN/HOLD Operation 3.2.4 DIRECT MODE The data outputs (bits 1 through 8, low order bytes; bits 9 through 12, polarity and over range high order bytes) are accessible under control of the byte and chip enable terminals as inputs, with the MODE pin at a LOW level. These three inputs are all active LOW. Internal pull-up resistors are provided for an inactive HIGH level when left open. When chip enable is LOW, a byte enable input LOW will allow the outputs of the byte to become active. A variety of parallel data accessing techniques may be used, as shown in the “Interfacing” section. (See Figure 3-4 and Table 3-1.) The access of data should be synchronized with the conversion cycle by monitoring the Status output. This prevents accessing data while it is being updated and eliminates the acquisition of erroneous data. FIGURE 3-4: TC7109A Direct Mode Output Timing TABLE 3-1: TC7109A DIRECT MODE TIMING REQUIREMENTS 3.2.5 HANDSHAKE MODE An alternative means of interfacing the TC7109A to digital systems is provided when the Handshake Out- put mode of the TC7109A becomes active in controlling the flow of data, instead of passively responding to chip and byte enable inputs. This mode allows a direct inter- face between the TC7109A and industry standard UARTs with no external logic required. The TC7109A provides all the control and flag signals necessary to sequence the two bytes of data into the UART and ini- tiate their transmission in serial form when triggered into the Handshake mode. The cost of designing remote data acquisition stations is reduced using serial data transmission to minimize the number of lines to the central controlling processor. Integrator Output Internal Clock Determinated at Zero Crossing Detection Auto-Zero Phase I Min 1790 Counts Max 2041 Counts Static in Hold State INT Phase II RUN/HOLD input is ignored until end of auto-zero phase. *Note: Internal Latch Status Output RUN/HOLD Input

7 Counts

= High-Impedance CE/LOAD As Input tCEA tBEA HBEN As Input tDAB tDAB LBEN As Input High Byte Data Low Byte Data Data Valid tDAC tDHC Data Valid Data Valid Symbol

© 2006 Microchip Technology Inc. DS21456C-page 13 TC7109/A FIGURE 3-5: TC7109A RC Oscillator With OSCILLATOR SELECT input LOW, two on-chip capacitors and a feedback device are added to the oscillator. In this configuration, the oscillator will oper- ate with most crystals in the 1MHz to 5MHz range, with no external components (Figure ). The OSCILLATOR SELECT input LOW inserts a fixed 458 divider circuit between the BUFFERED OSCILLATOR OUTPUT and the internal clock. A 3.58MHz TV crystal gives a division ratio, providing an integration time given by: EQUATION 3-1: FIGURE 3-6: Crystal Oscillator The error is less than 1% from two 60Hz periods, or 33.33msec, which will give better than 40dB, 60Hz rejection. The converter will operate reliably at conver- sion rates up to 30 per second, corresponding to a clock frequency of 245.8kHz. When the oscillator is to be over driven, the OSCILLA- TOR OUTPUT should be left open, and the over driving signal should be applied at the OSCILLATOR INPUT. The internal clock will be of the same duty cycle, fre- quency and phase as the input signal. When the OSCILLATOR SELECT is at GND, the clock will be 1/58 of the input frequency. FIGURE 3-7: TC7109A Handshake with Send Input Held Positive OSC OUT Buffered OSC OUT OSC SEL V+ or Open OSC IN R C FOSC = 0.45/RC t = (2048 clock periods) = 33.18 msec

3.58 MHz

= Three-State High-Impendance Integrator Output Data Invalid Data Valid Internal Clock Internal Latch Status Output Mode Input Internal Mode Send Input CE/LOAD HBEN High Byte Data LBEN Low Byte Data = Don't Care = Three-State will Pull-up UART Norm Terminates UART Mode Zero Crossing Detected Zero Crossing Occurs Send Sensed Send Sensed Mode Low, not in Handshake Mode Disables Outputs CE/LOAD, HBEN, LBEN Mode High Activates CE/LOAD, HBEN, LBEN

© 2006 Microchip Technology Inc. DS21456C-page 15 TC7109/A 3.4 Test Input The counter and its outputs may be tested easily. When the TEST input is connected to GND, the internal clock is disabled and the counter outputs are all forced into the HIGH state. When the input returns to the 1/2 (V+ – GND) voltage or to V+ and one clock is input, the counter outputs will all be clocked to the LOW state. The counter output latches are enabled when the TEST input is taken to a level halfway between V+ and GND, allowing the counter contents to be examined any time. 3.5 Component Value Selection The integrator output swing for full scale should be as large as possible. For example, with ±5V supplies and COMMON connected to GND, the nominal integrator output swing at full scale is ±4V. Since the integrator output can go to 0.3V from either supply without signif- icantly effecting linearity, a 4V integrator output swing allows 0.7V for variations in output swing, due to com- ponent value and oscillator tolerances. With ±5V sup- plies and a Common mode voltage range of ±1V required, the component values should be selected to provide ±3V integrator output swing. Noise and roll- over errors will be slightly worse than in the ±4V case. For large Common mode voltage ranges, the integrator output swing must be reduced further. This will increase both noise and rollover errors. To improve performance, ±6V supplies may be used. 3.5.1 INTEGRATING CAPACITOR The integrating capacitor, CINT, should be selected to give the maximum integrator output voltage swing that will not saturate the integrator to within 0.3V from either supply. A ±3.5V to ±4V integrator output swing is nom- inal for the TC7109A, with ±5V supplies and analog common connected to GND. For 7-1/2 conversions per second (61.72kHz internal clock frequency), nominal values CINT and CAZ are 0.15μF and 0.33μF, respec- tively. These values should be changed if different clock frequencies are used to maintain the integrator output voltage swing. The value of CINT is given by: EQUATION 3-2: The integrating capacitor must have low dielectric absorption to prevent rollover errors. Polypropylene capacitors give undetectable errors, at reasonable cost, up to +85°C. 3.5.2 INTEGRATING RESISTOR The integrator and buffer amplifiers have a class A out- put stage with 100μA of quiescent current. They supply 20μA of drive current with negligible non-linearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2.048V full scale, a 100kΩ resistor is recommended and for 409.6mV full scale, a 20k resistor is recommended. RINT may be selected for other values of full scale by: EQUATION 3-3: 3.5.3 AUTO-ZERO CAPACITOR As the auto-zero capacitor is made large, the system noise is reduced. Since the TC7109A incorporates a zero integrator cycle, the size of the auto-zero capaci- tor does not affect overload recovery. The optimal value of the auto-zero capacitor is between 2 and 4 times CINT. A typical value for CAZ is 0.33μF. The inner foil of CAZ should be connected to Pin 31 and the outer foil to the RC summing junction. The inner foil of CINT should be connected to the RC summing junction and the outer foil to Pin 32, for best rejection of stray pickups. 3.5.4 REFERENCE CAPACITOR A 1μF capacitor is recommended for most circuits. However, where a large Common mode voltage exists, a larger value is required to prevent rollover error (e.g., the reference low is not analog common), and a 409.6mV scale is used. The rollover error will be held to 0.5 count with a 10μF capacitor. 3.5.5 REFERENCE VOLTAGE To generate full scale output of 4096 counts, the analog input required is VIN = 2VREF. For 409.6mV full scale, use a reference of 204.8mV. In many applications, where the ADC is connected to a transducer, a scale factor will exist between the input voltage and the digital reading. For instance, in a measuring system, the designer might like to have a full scale reading when the voltage for the transducer is 700mV. Instead of dividing the input down to 409.6mV, the designer should use the input voltage directly and select VREF = 350mV. Suitable values for integrating resistor and capacitor would be 34kΩ and 0.15μF. This makes the system slightly quieter and also avoids a divider network on the input. Another advantage of this system occurs when temperature and weight measurements, with an offset or tare, are desired for non-zero input. The offset may be introduced by connecting the voltage output of the transducer between common and analog high, and the offset voltage between common and ana- log low, observing polarities carefully. In processor based systems using the TC7109A, it may be more desirable to use software and perform this type of scaling or tare subtraction digitally. (2048 Clock Period) (20 μA) Integrator Output Voltage Swings CINT = Full Scale Voltage 20 μA RINT =

© 2006 Microchip Technology Inc. 3.5.6 REFERENCE SOURCES A major factor in the absolute accuracy of the ADC is the stability of the reference voltage. The 12-bit resolu- tion of the TC7109A is one part in 4096, or 244 ppm. Thus, for the on-board reference temperature coeffi- cient of 70ppm/°C, a temperature difference of 3°C will introduce a one-bit absolute error. Where the ambient temperature is not controlled, or where high accuracy absolute measurements are being made, it is recommended that an external high quality reference be used. A reference output (Pin 29) is provided, which may be used with a resistive divider to generate a suitable ref- erence voltage (20mA may be sunk without significant variation in output voltage). A pull-up bias device is pro- vided, which sources about 10μA. The output voltage is nominally 2.8V below V+. When using the on-board reference, REF OUT (Pin 29) should be connected to REF IN- (pin 39), and REF IN+ should be connected to the wiper of a precision potentiometer between REF OUT and V+. The test circuit shows the circuit for a 204.8mV reference, generated by a 2kΩ precision potentiometer in series with a 24kΩ fixed resistor.

© 2006 Microchip Technology Inc. 4.2 Handshake Mode The Handshake mode provides an interface to a wide variety of external devices. The byte enables may be used as byte identification flags, or as load enables, and external latches may be clocked by the rising edge of CE/LOAD. A handshake interface to Intel® micropro- cessors using an 8255 PPI is shown in Figure . The handshake operation with the 8255 is controlled by inverting its Input Buffer Full (IBF) flag to drive the SEND input to the TC7109A, and using the CE/LOAD to drive the 8255 strobe. The internal control register of the PPI should be set in MODE 1 for the port used. If the 8255 IBF flag is LOW and the TC7109A is in Hand- shake mode, the next word will be strobed into the port. The strobe will cause IBF to go HIGH (SEND goes LOW), which will keep the enabled byte outputs active. The PPI will generate an interrupt which, when executed, will result in the data being read. The IBF will be reset LOW when the byte is read, causing the TC7109A to sequence into the next byte. The MODE input to the TC7109A is connected to the control line on the PPI. The data from every conversion will be sequenced in two bytes in the system, if this output is left HIGH, or tied HIGH separately. (The data access must take less time than a conversion.) The output sequence can be obtained on demand if this output is made to go from LOW to HIGH and the interrupt may be used to reset the MODE bit. Conversions may be obtained on command under soft- ware control by driving the RUN/HOLD input to the TC7109A by a bit of the 8255. Another peripheral device may be serviced by the unused port of the 8255. The Handshake mode is particularly useful for directly interfacing to industry standard UARTs (such as Intersil HD-6402), providing a means of serially transmitting converted data with minimum component count. A typical UART connection is shown in Figure . In this circuit, any word received by the UART causes the UART DR (Data Ready) output to go HIGH. The MODE input to the TC7109A goes HIGH, triggering the TC7109A into Handshake mode. The high order byte is output to the UART and when the UART has trans- ferred the data to the Transmitter register, TBRE (SEND) goes HIGH again, LBEN will go HIGH, driving the UART DRR (Data Ready Reset), which will signal the end of the transfer of data from the TC7109A to the UART. An extension of the typical connection to several TC7109A’s with one UART is shown in Figure 4-7. In this circuit, the word received by the UART (available at the RBR outputs when DR is HIGH) is used to select which converter will handshake with the UART. Up to eight TC7109A’s may interface with one UART, with no external components. Up to 256 converters may be accessed on one serial line with additional components. FIGURE 4-6: TC7109 Typical UART Interface GND BUFF OSC OUT STATUS HBEN B1 - B8 TEST LBEN MODE CE/LOAD SEND V+ 40 TC7109A CLK RESET 5–12 V GND RRD RBR1–8 PE FE OE SFD RR1 TRO TRC RRC EPE CLS1 CLS2 SBS PI CRL *TBR1–8 TRE DRR DR TBRL TBRE MR HD-640R CMOS UART +5V GND +5V GND Serial Input Serial Output GND GND +5V +5V GND +5V -5V +5V or Open GND 3.58MHz Crystal Analog GND External Reference – Input CAZ 0.33μF CINT 0.15μF 0.01μF 1MΩ 1μF 3–8 9–16 B9 - B12, POL, OR 26–33 For lowest power consumption, TBR1-TBR8 inputs should have 100kΩ pull-up resistors to +5V. Send any word to UART to transmit latest result. RINT 20kΩ 100kΩ 0.2VREF 1VREF CD4060B REF IN- REF CAP- REF CAP+ REF IN+ IN HI IN LO COM INT AZ REF OUT BUFF RUN/HOLD OSC SEL OSC OUT OSC IN *Note:

© 2006 Microchip Technology Inc. DS21456C-page 21 TC7109/A FIGURE 4-7: Handshake Interface for Multiplexed Converters FIGURE 4-8: Connection Diagram TC7109A B9 - B12 POL, OR B1 - B8 LBEN HBEN Analog In RUN/HOLD SEND MODE CE/ LOAD +5V TC7109A B9 - B12 POL, OR B1 - B8 LBEN HBEN 8-Bit Data Bus Analog In RUN/HOLD SEND MODE CE/ LOAD +5V TC7109A B9 - B12 POL, OR B1 - B8 LBEN HBEN Analog In RUN/HOLD SEND MODE CE/ LOAD +5V TBRL DRR GND TBRE RBR1 - RBR8 SFD TBR1 - TBR8 Serial Output Serial Input

6402 CMOS UART

μPD8748H/49H CMOS Microcomputer +5V Other I/O +5V GND -5V GND 3.58MHz Crystal Analog GND External Reference – Input CAZ 0.33μF RINT 20k 10 k Ω Ω

0.2 VREF

1 VREF

B9 - B12, POL, OR B1 - B8 CE/LOAD 21-24, 35-38 12-19 31-34 CINT 0.15μF 0.01μF 1MΩ 1μF GND +5V +5V +5V +5V GND 3-8 9-16 REF IN- REF CAP- REF CAP+ REF IN+ IN HI HI LO COM INT AZ BUFF REF OUT OSC SEL OSC OUT OSC IN SEND BUFF OSC OUT MODE

© 2006 Microchip Technology Inc. 5.0 INTEGRATING CONVERTER

FEATURES

The output of integrating ADCs represents the integral, or average, of an input voltage over a fixed period of time. Compared with techniques in which the input is sampled and held, the integrating converter averages the effects of noise. A second important characteristic is that time is used to quantize the answer, resulting in extremely small non-linearity errors and no missing output codes. The integrating converter also has very good rejection of frequencies whose periods are an integral multiple of the measurement period. This feature can be used to advantage in reducing line frequency noise (Figure ). FIGURE 5-1: Normal Mode Rejection of Dual Slope Converter as a Function of Frequency 0.1/t 1/t 10/t Input Frequency Normal Mode Rejection Plan t = Measurement Period

© 2006 Microchip Technology Inc. DS21456C-page 23 TC7109/A 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Package marking data not available at this time. 6.2 Taping Form Component Taping Orientation for 44-Pin PQFP Devices User Direction of Feed Pin 1 Standard Reel Component Orientation for 713 Suffix Device W P Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 44-Pin PQFP 24 mm 16 mm 500 13 in Carrier Tape, Number of Components Per Reel and Reel Size Note: Drawing does not represent total number of pins. Pin 1 Component Taping Orientation for 44-Pin PLCC Devices User Direction of Feed Standard Reel Component Orientation for 713 Suffix Device Note: Drawing does not represent total number of pins. W P Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 44-Pin PLCC 32 mm 24 mm 500 13 in Carrier Tape, Number of Components Per Reel and Reel Size

© 2006 Microchip Technology Inc. 6.3 Package Dimensions Dimensions: inches (mm) 2.065 (52.45) 2.027 (51.49) .200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .022 (0.56) .015 (0.38) .110 (2.79) .090 (2.29) .555 (14.10) .530 (13.46) .610 (15.49) .590 (14.99) .015 (0.38) .008 (0.20) .700 (17.78) .610 (15.50) .040 (1.02) .020 (0.51) 40-Pin PDIP (Wide) Pin1 3° Min. Dimensions: inches (mm) .015 (0.38) .008 (0.20) .620 (15.75) .590 (15.00) .700 (17.78) .620 (15.75) .540 (13.72) .510 (12.95) 2.070 (52.58) 2.030 (51.56) .210 (5.33) .170 (4.32) .020 (0.51) .016 (0.41) .110 (2.79) .090 (2.29) .065 (1.65) .045 (1.14) .200 (5.08) .125 (3.18) .098 (2.49) Max. .030 (0.76) Min. .060 (1.52) .020 (0.51) .150 (3.81) MIN. 40-Pin CERDIP (Wide) Pin 1 3° Min.

© 2006 Microchip Technology Inc. DS21456C-page 25 TC7109/A 6.3 Package Dimensions (Continued) Dimensions: inches (mm) .557 (14.15) .537 (13.65) .398 (10.10) .390 (9.90) .031 (0.80) TYP. .018 (0.45) .012 (0.30) .398 (10.10) .390 (9.90) .010 (0.25) Typ. .096 (2.45) Max. .557 (14.15) .537 (13.65) .083 (2.10) .075 (1.90) .041 (1.03) .026 (0.65) 7° Max. .009 (0.23) .005 (0.13) 44-Pin PQFP Pin 1 Dimensions: inches (mm) Standard Reel Component Orientation for 713 Suffix Device Note: Drawing does not represent total number of pins. W P Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 44-Pin PLCC 32 mm 24 mm 500 13 in Carrier Tape, Number of Components Per Reel and Reel Size

© 2006 Microchip Technology Inc. NOTES:

© 2006 Microchip Technology Inc. DS21456C-page 27 TC7109/A THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:

  • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software
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  • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels:
  • Distributor or Representative
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  • Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com

© 2006 Microchip Technology Inc. READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response From: Name Company Address City / State / ZIP / Country Application (optional): Would you like a reply? Y N Device: Literature Number: Questions: DS21456C TC7109/A What are the best features of this document? How does this document meet your hardware and software development needs? Do you find the organization of this document easy to follow? If not, why? What additions to the document do you think would enhance the structure and subject? What deletions from the document could be made without affecting the overall usefulness? Is there any incorrect or misleading information (what and where)? How would you improve this document?

© 2006 Microchip Technology Inc. DS21456C-page 29 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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