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Technical content

Features

  • Integrated Gate-to-Source Resistor
  • Integrated Gate-to-Source Zener Diode
  • Low Threshold
  • Low On-Resistance
  • Low Input Capacitance
  • Fast Switching Speeds
  • Free from Secondary Breakdown
  • Low Input and Output Leakage
  • Independent, Electrically Isolated N- and P-Channels
  • 8-Lead Very Thin Plastic Dual Flat, No Lead, 6x5m mV D F N P a c k a g e

Applications

  • High-Voltage Pulser
  • A m p l i f i e r s
  • B u f f e r s
  • Piezoelectric Transducer Drivers
  • General-Purpose Line Drivers
  • Logic-Level Interfaces Package Types

Description

The TC6321 consists of high-voltage, low-threshold N-channel and P-channel MOSFETs in an 8-Lead VDFN package. Both MOSFETs have integrated gate-to-source resistors and gate-to-source Zener diode clamps, which are desired for high-voltage pulser applications. The TC6321 is a complimentary, high-speed, high-voltage, gate-clamped N- and P-channel MOSFET pair, which utilizes an advanced vertical DMOS structure and the well-proven silicon-gate manufacturing process. This combination produces a device with the power-handling capabilities of bipolar transistors and with the high-input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally- induced secondary breakdown. Vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance and fast switching speeds are desired. TC6321 6x5 V D F N * * Includes Dual Exposed Thermal Pads (EP); see Table 3-1. DN DN DP DP SN GN SP GP 3 N- and P-Channel Enhancement-Mode MOSFET Pair

DS20005724A-page 2  2017 Microchip Technology Inc. Typical Application Circuit Functional Block Diagram +100V TC6321 -100V VDD VH VSS VL OE INA INB 10 nF 10 nF MD12XX, MD17XX, MD18XX N-Channel P-Channel DN DN DP DP SN GN GP SP

 2017 Microchip Technology Inc. DS20005724A-page 3 TC6321

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. N-CHANNEL DC AND AC ELECTRICAL CHARACTERISTICS Unless otherwise noted, TA =T J = +25°C. Parameters Sym. Min. Typ. Max. Units Conditions DC Parameters (Note 1) Drain-to-Source Breakdown Voltage BVDSS 200 — — V VGS = 0V, ID = 2.0 mA Gate Threshold Voltage V GS(th) 1.0 — 2.0 V V GS =V DS, ID = 1.0 mA Change in VGS(th) with Temperature ∆VGS(th) — — –4.5 mV/ºC VGS =V DS, ID = 1.0 mA (Note 2) Gate-to-Source Shunt Resistor R GS 10 — 50 k Ω IGS = 100 μA Gate-to-Source Zener Voltage VZ GS 13.2 — 25 V I GS = 2 mA Zero Gate Voltage Drain Current IDSS — — 10.0 μAV DS = 200V VGS = 0V —— 1 . 0m A V DS = 200V, VGS = 0V TJ = +125°C (Note 2) On-State Drain Current I D(ON) 1.0 — — A V GS =4 . 5 V , VDS = 25V 2.0 — — V GS = 10V, VDS = 25V Static Drain-to-Source On-State Resistance RDS(ON) —— 8 . 0 Ω VGS = 4.5V, ID =1 5 0m A —— 7 . 0 V GS = 10V, ID = 1.0A Change in RDS(ON) with Temperature ∆RDS(ON) —— 1 . 0 % / º C VGS = 4.5V, ID =1 5 0m A (Note 2) AC Parameters (Note 2) Forward Transconductance G FS 400 — — mmho V GS = 25V, ID= 500 mA Input Capacitance C ISS —— 1 1 0 pF VGS = 0V VDS = 25V f = 1.0 MHz Common Source Output Capacitance COSS ——6 0 Reverse Transfer Capacitance C RSS ——2 3 Turn-On Delay Time t d(ON) ——1 0 ns VGS = 10V VDS = 25V ID = 1.0A RGEN = 25Ω Rise Time t r ——1 5 Turn-Off Delay Time t d(OFF) ——2 0 Fall Time t f ——1 5 Note 1: Unless otherwise stated, all DC parameters are 100% tested at +25°C. Pulse test: 300 µs pulse, 2% duty cycle. 2: Specification is obtained by characterization and is not 100% tested.

DS20005724A-page 4  2017 Microchip Technology Inc. Diode Parameters Diode Forward Voltage Drop V SD —— 1 . 8 V VGS= 0V, ISD= 500 mA (Note 1) Reverse Recovery Time t rr —1 0 0— n s VGS = 0V, ISD = 500 mA diF/dt = 25 A/µ (Note 2) P-CHANNEL DC AND AC ELECTRICAL CHARACTERISTICS Unless otherwise noted, TA = TJ = +25°C. Parameter Sym. Min. Typ. Max. Unit Condition DC Parameters (Note 1) Drain-to-Source Breakdown Voltage BVDSS –200 — — V V GS= 0V, ID= –2.0 mA Gate Threshold Voltage V GS(th) –1.0 — –2.4 V V GS =V DS, ID = –1.0 mA Change in VGS(th) with Temperature ∆VGS(th) —— 4 . 5 m V / º C VGS =V DS, ID = –1.0 mA (Note 2) Gate-to-Source Shunt Resistor R GS 10 — 50 k Ω IGS = 100 μA Gate-to-Source Zener Voltage VZ GS 13.2 — 25 V I GS = –2 mA Zero Gate Voltage Drain Current IDSS — — –10.0 μAV DS = 200V, VGS = 0V — — –1.0 mA VDS = 200V, VGS = 0V TJ = +125°C, (Note 2) On-State Drain Current I D(ON) –1.0 — — A VGS = –4.5V, VDS = –25V –2.0 — — V GS = –10V, VDS = –25V Static Drain-to-Source On-State Resistance RDS(ON) ——1 0 VGS = –4.5V, ID = –150 mA Change in RDS(ON) with Temperature ∆RDS(ON) —— 1 . 0 % / ° C VGS = –25V, ID = –200 mA (Note 2) AC Parameters (Note 2) Forward Transconductance G FS 400 — — mmho V GS = –25V, ID = –500 mA Input Capacitance C ISS —— 2 0 0 pF VGS = 0V VDS = –25V f = 1.0 MHz Common Source Output Capacitance COSS ——5 5 Reverse Transfer Capacitance C RSS ——3 0 Turn-On Delay Time t d(ON) ——1 0 ns VGS = –10V VDS = –25V ID = –1.0A RGEN = 25Ω Rise Time t r ——1 5 Turn-Off Delay Time t d(OFF) ——2 0 Fall Time t f ——1 5 Note 1: Unless otherwise stated, all DC parameters are 100% tested at +25°C. Pulse test: 300 µs pulse, 2% duty cycle. 2: Specification is obtained by characterization and is not 100% tested. N-CHANNEL DC AND AC ELECTRICAL CHARACTERISTICS (CONTINUED) Unless otherwise noted, TA =T J = +25°C. Parameters Sym. Min. Typ. Max. Units Conditions Note 1: Unless otherwise stated, all DC parameters are 100% tested at +25°C. Pulse test: 300 µs pulse, 2% duty cycle. 2: Specification is obtained by characterization and is not 100% tested.

 2017 Microchip Technology Inc. DS20005724A-page 5 TC6321 Diode Parameters Diode Forward Voltage Drop V SD — — –1.8 V VGS= 0V, ISD= –500 mA (Note 1) Reverse Recovery Time t rr —1 0 0— n s VGS = 0V, ISD = –500 mA diF/dt = -25 A/µs (Note 2) TEMPERATURE SPECIFICATIONS Parameters Sym. Min. Typ. Max. Units Conditions Temperature Ranges Operating Temperature T J –40 — +150 °C Storage Temperature T A –55 — +175 °C Thermal Package Resistances Thermal Resistance, 6x5 mm VDFN-8LD JC — 1.43 — °C/W P-CHANNEL DC AND AC ELECTRICAL CHARACTERISTICS (CONTINUED) Unless otherwise noted, TA = TJ = +25°C. Parameter Sym. Min. Typ. Max. Unit Condition Note 1: Unless otherwise stated, all DC parameters are 100% tested at +25°C. Pulse test: 300 µs pulse, 2% duty cycle. 2: Specification is obtained by characterization and is not 100% tested.

DS20005724A-page 6  2017 Microchip Technology Inc. NOTES:

 2017 Microchip Technology Inc. DS20005724A-page 7 TC6321

2.0 TYPICAL PERFORMANCE CURVES

Note: Unless otherwise indicated, TA = TJ = 25°C. FIGURE 2-1: N-Channel ID vs. VDS (Output Characteristics). FIGURE 2-2: N-Channel On-Resistance vs. Temperature. FIGURE 2-3: N-Channel ID vs. VGS. FIGURE 2-4: P-Channel ID vs. VDS (Output Characteristics). FIGURE 2-5: P-Channel On-Resistance vs. Temperature. FIGURE 2-6: P-Channel ID vs. VGS. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 0 50 100 150 200 ID (A) VDS (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -55 -25 0 25 50 75 100 125 150 175 RDS(ON) (normalized) Temperature (°C) VGS = 4.5V, ID = 150 mA VGS = 10V, ID = 1A 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0123456789 1 0 ID (A) VGS (V) Temp. = 25 C VDS = +25V -3.50 -3.00 -2.50 -2.00 -1.50 -1.00 -0.50 0.00 -200-150-100-500 ID (A) VDS (V) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -55 -25 0 25 50 75 100 125 150 175 RDS(ON) (normalized) Temperature (°C) VGS = -4.5V, ID = -150 mA VGS = -10V, ID = -1A -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 ID (A) VGS (V) Temp. = 25ƒ& VDS = -25V

DS20005724A-page 10  2017 Microchip Technology Inc. NOTES:

 2017 Microchip Technology Inc. DS20005724A-page 11 TC6321

3.0 PIN DESCRIPTION

The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE TC6321 6x5 VDFN Name Description

1 SN Source N-Channel

2 GN Gate N-Channel

3 GP Gate P-Channel

4 SP Source P-Channel

5, 6 DP Drain P-Channel 7,8 DN Drain N-Channel

9 EP Dual Exposed Thermal Pads

DS20005724A-page 12  2017 Microchip Technology Inc. NOTES:

 2017 Microchip Technology Inc. DS20005724A-page 13 TC6321

4.0 FUNCTIONAL DESCRIPTION

4.1 N-Channel Switching Waveforms

Figure 4-1 shows the N-channel switching waveforms and test circuit. FIGURE 4-1: N-Channel Switching Waveforms and Test Circuit.

4.2 P-Channel Switching Waveforms

Figure 4-2 shows the P-channel switching waveforms and test circuit. FIGURE 4-2: P-Channel Switching Waveforms and Test Circuit. t(ON) td(ON) tr 10% 90% 10% 90% 90% 10% t(OFF) tftd(OFF) 0 V 10 V Input Output VDD 0 V VDD Output Input RGEN RL VSOURCE TC6321 t(ON) td(ON) tr 10% 90% 10% 90% 90% 10% t(OFF) tftd(OFF) -10 V 0 V Input Output 0 V VSS VSS OutputInput RGEN RL VSOURCE TC6321

DS20005724A-page 14  2017 Microchip Technology Inc. NOTES:

 2017 Microchip Technology Inc. DS20005724A-page 15 TC6321

5.0 APPLICATION INFORMATION

The TC6321 N- and P-MOSFET pair is designed for a wide range of switching and amplifying applications where high-voltage, high-current drive and fast switching speeds are required, especially for medical ultrasound applications. A typical application pairs the TC6321 with any of MD12xx, MD17xx, or MD18xx ultrasound family MOSFET Drivers in order to form a high-speed and high-voltage (+/–100V 2.5A) pulser circuit. Figure 5-1 illustrates the application circuit digram for a two level pulser. FIGURE 5-1: TC6321 - Application Circuit Diagram. +100V TC6321 -100V VDD VH VSS VL OE INA INB 10 nF 10 nF MD12XX, MD17XX, MD18XX

DS20005724A-page 16  2017 Microchip Technology Inc. NOTES:

 2017 Microchip Technology Inc. DS20005724A-page 17 TC6321

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

8-Lead VDFN (6 x 5 mm) Example Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC ® designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. TC6321 V/9U 1640 256

DS20005724A-page 18  2017 Microchip Technology Inc. BA 0.10 C 0.10 C (DATUM B) (DATUM A) C SEATING PLANE NOTE 1 TOP VIEW SIDE VIEW BOTTOM VIEW NOTE 1 N

0.10 C A B

0.10 C 0.08 C Microchip Technology Drawing C04-413A Sheet 1 of 2 For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: 8-Lead Very Thin Plastic Dual Flat, No Lead (9U) - 6x5 mm Body [VDFN] With Dual Exposed Pads D E A 2X D2 2X E2 4X (K1) 4X (K2) 8X b 0.05 C 8X L e N e (K3) (K4) D E

 2017 Microchip Technology Inc. DS20005724A-page 19 TC6321 Microchip Technology Drawing C04-413A Sheet 2 of 2 Number of Terminals Overall Height Terminal Width Overall Width Terminal Length Exposed Pad Width (X2) Terminal Thickness Pitch Standoff Units Dimension Limits A b e L E N

1.27 BSC

0.20 REF

3.15 0.55 0.35 0.80 0.00 0.40 0.60 3.25 0.85 0.02

5.00 BSC

3.35 0.65 0.45 0.90 0.05 MAX K4 0.60 REF REF: Reference Dimension, usually without tolerance, for information purposes only. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Notes: Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M Exposed Pad to Exposed Pad For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Note: Overall Length Exposed Pad Length (X2) D D2 2.25

6.00 BSC

2.35 2.45 8-Lead Very Thin Plastic Dual Flat, No Lead (9U) - 6x5 mm Body [VDFN] With Dual Exposed Pads Molded Package Edge to Exposed Pad K3 0.35 REF Terminal to Exposed Pad (X4) K2 0.20 REF Terminal to Exposed Pad (X4) K1 0.35 REF

DS20005724A-page 20  2017 Microchip Technology Inc.

 2017 Microchip Technology Inc. DS20005724A-page 21 TC6321 APPENDIX A: REVISION HISTORY Revision A (March 2017)

  • Original Release of this Document.

DS20005724A-page 22  2017 Microchip Technology Inc. NOTES:

 2017 Microchip Technology Inc. DS20005724A-page 23 TC6321 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . PART NO. Device Temperature XX Package Device: TC6321T: N- and P-Channel Enhancement-Mode MOSFET Pair, Tape and Reel Temperature: V = -55°C to +175°C (Various temperature levels) (1 ) Package Type: 9U = Very Thin Plastic Dual Flat, No Lead, VDFN, 8-Lead, 6x5 mm Body, with Dual Exposed Pads Examples: a) TC6321T-E/MQ: Tape and Reel, Various temperature levels, 8-LD VDFN package Note 1: Shipment of these devices may require an end-use/end-user certificate per SPI-43508.

DS20005724A-page 24  2017 Microchip Technology Inc. NOTES:

 2017 Microchip Technology Inc. DS20005724A-page 25 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2017, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-1396-7 Note the following details of the code protection feature on Microchip devices:

  • Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
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  • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
  • Microchip is willing to work with the customer who is concerned about the integrity of their code.
  • Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are co mmitted to continuously improvin g the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT S YSTEM CERTIFIED BY DNV == ISO/TS 16949 ==

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