TC59S6408BFT-80

TC59S6416 TOSHIBA | Alldatasheet

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Technical content

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 1,048,576-WORDS x 4BANKS x 16-BITS SYNCHRONOUS DYNAMIC RAM 2,097,152-WORDS x 4BANKS x 8-BITS SYNCHRONOUS DYNAMIC RAM 4,194,304-WORDS x 4BANKS x 4-BITS SYNCHRONOUS DYNAMIC RAM

DESCRIPTION

TC59S6416BFT/BFTL is a CMOS synchronous dynamic random access memory organized as 1,048,576-wordsxX4 banksX16 bits and TC59S6408BFT/BFTL is organized as 2,097,152 wordsx4 banksX8 bits and the TC59S6404BFT/BFTL is organized as 4,194,304 wordsX4 banksX4 bits. Fully synchronous operations are referenced to the positive edges of clock input and can transfer data up to 125M words per second. These devices are controlled by commands setting. Each bank are kept active so that DRAM core sense amplifiers can be used as a cache. The refresh functions, either Auto Refresh or Self Refresh are easy to use. By having a programmable Mode Register, the system can choose the most suitable modes which will maximize its performance. These devices are ideal for main memory in applications such as work-stations.

FEATURES

“ [=o [<0 | iteas Active to Precharge Command Period(Min.) | _48ns__| __-60ns_—| tac Access Time from CuK(Max) | ns | ns | fac __RetiActive to Ref/Active Command Period (Min.)| _68ns__ | ans __| Icc1_ Operation Current (Max.) (Single bank) @ Single power supply of 3.3V+0.3V © Up to 125MHz clock frequency @ Synchronous operations : All signals referenced to the positive edges of clock © Architecture : Pipeline © Organization TC59S6416BFT/BFTL : 1,048,576 wordsX4 banks x 16bits TC59S6408BFT/BFTL : 2,097,152 words x4 banks x 8bits TC59S6404BFT/BFTL : 4,194,304 words x4 banks x 4bits © Programmable Mode register © Auto Refresh and Self Refresh © Burst Length : 1, 2, 4, 8, Full page @ TAS Latency : 2,3 © Single Write Mode © Burst Stop Function © Byte Data Controlled by L- DQM, U- DQM (TC59$6416) © 4K Refresh cycles /64ms @ Interface : LVTTL @ Package TC59S6416BFT/BFTL : TSOPI54-P-400-0.80B TC59S6408BFT/BFTL : TSOPI54-P-400-0.80B TC59S6404BFT/BFTL : TSOPI54-P-400-0.80B 961001€8A1 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. @ The products described in this document are subject to foreign exchange and foreign trade control laws. @ The information contained herein is Bresented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1998-01-12 1/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 PIN NAMES PIN ASSIGNMENT (TOP VIEW) BSO, BS1 Bank Select TC59S6408BFT/BFTL jTeseseaoaarr/errL 5 (TC59S6404) Vec Vee Vec G1 54 [0 Vss Vss Vss DQ0~DQ7 DQO —— QO nc G2 s3f) Nc Q7_—siaqs (rcs9s6408) Data Input/Output VeeQ VeeQ = Veeq G3 52 VssQ VssQ_ —VssQ pQ1 NC nc 4 sinc) = =NC DQi4 DQo~DQ15 pq@z.pqi.—s ogo fs 50H) Qs Qe ai (TC59S6416) VssQ VssQ VssQ =i 49 : VecQ VecQ_ VecQ cs Chip Select DQa DQ2 nc Os 470 ne DQ5.-DQi1 Row Address Strobe VeQ VeQ VeeQ 9 6 V5Q VesQ Vss0 AS Column Address Strobe pqs. gsi 11 aa vq2 aaa [we [write Enable VssQ VssQ. VssQ E12 43 VecQ VecQ VecQ Dam DQ7 NC ne 13 a2f nc =nc v8 Vec Vee Veo 14 41 Vss Vss Vss (rcsese4oe/ , . LDQM NC nc 15 4of2nc Nc nc 6404) Output disable/ Write Mask WE WE we O16 391 pam DQM UDQM UDQM/LDQM CS csSi7 38) cik CLK CLK (15986416) RAS RAS RAS C}18 = 37. CKE.—s KE CKE - cs cs cs i9 36fnc nc nc [cke __—_—_[ Clock enable BS1 BS1 ps1 21 340 ag Ag Ag Atoap AtoaP AtoaP E22 33 ABABA [vec | Power (+ 3.30) AO AO ao 23 320 a7 a7 al at at 2a a1 fl ab AGB A2 A2 a2Q25 30f as) a5 AS a 8 eae eA vn ve ve (for 1/0 buffer) Vee Vec Vec 27 28 vss ss. Vs VssQ Ground (for 1/0 buffer) 1998-01-12 2/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 BLOCK DIAGRAM CLK —*! cLock BUFFER CKE | a CONTROL _ commano|_ SIGNAL RAS —>| Ct TT |GENERATOR CAS | beconer Wwe >| FA &

8 CELL ARRAY 8 CELL ARRAY

i} BANK #0 a BANK #1 A10 3 5 i & MODE [sense amenrien | [sense AMenien | AO ADDRESS LP $ LY BUFFER ag iS All Bs1 DATA CONTROL K | [_) DQ K—) S eeu NT BUFFER boa REFRESH COLUMN iii Os t——q | { DQM | : e a Pry io a a S CELL ARRAY is} CELL ARRAY a BANK #2 a BANK #3 NOTE : The TC59S6404BFT/BFTL configuration is 4096x1024x4 of cell array with the DQ pins numbered DQO-3. The TC59S6408BFT/BFTL configuration is 4096x512x8 of cell array with the DQ pins numbered DQO-7. The TC59S6416BFT/BFTL configuration is 4096x256x16 of cell array with the DQ pins numbered DQO-15. 1998-01-12 3/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 ABSOLUTE MAXIMUM RATINGS [Vr Vaur | st, Ontut vonage | -aavevoa |v | 1 _] Vee: vec | Power Supoy vorage | -03-a8 [|v [Tom | Operating Temperature | o-m |e | 1 _| [re | Storage Temperate | senso «| Se dP [Tousen | Soldering Temperatwreton | 60 «|e «dT Sd [ro «| rower Dispaton «tt Pw Td [tour shore cireuit ourput current [so Tema RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 to 70°C) [sao [rere | ow | ve [om | wm [re | [va [__ fever sippy votowe 30 | 33 fe |v [2 [Veco [Power Spy voto or vowed | 30 | 33 | 36 |v | 2 _| [vn [pein vores 20 | if eos |v | 2 [ [att vorase es ff os | ve Note: Viy(max) =Vcc/VccQ +1.2V for pulse width = 5ns Vit(min) = Vss5/VssQ-1.2V for pulse width = 5ns CAPACITANCE (Vcc =3.3V , f= 1MHz , Ta=25°C) a « [ = | | Se [ern oupur apuctine——SSSSSCSCSC~sC es NOTE: These parameters are periodicaly sampled and not 100% tested. 1998-01-12 4/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 RECOMMENDED DC OPERATING CONDITIONS (Vcc = 3.3V £ 0.3V, Ta =0~70°C) it Lvmeo—-82 | = 10 Tins | notes cers eran OPERATING CURRENT tex =min , tac= min Active Precharge command cycling |' bank operation Neer 70 3 without Burst operation eee em fe| fet [=| tec=min , C=Vin Vin l= Vin (min)! Vit (max) = Bees i deiny TT CKE=Vj, (Power Down mode) | Icczp 3 acer ee fel pte) CLK=Vi. , CS=Vin a seas Vine = Vin(min) /Viu(max) = Boks innective state CKE=VIL (Power Down mode) | Icczps mA Seqmomr fos fe | fet f*] teg= min CS=Vi4 (min) = Bank : active state (4 banks) CKE= Vi. (Power Down mode) | Iccap BURST OPERATING CURRENT tag=min leca Read/Write command cycling AUTO REFRESH CURRENT tex=min , tec=min lees 3 Auto Refresh command cycling SELF REFRESH CURRENT Pr FT) CKE=0.2V Tel Toto ec INPUT LEAKAGE CURRENT \\ 5 (OVS Vin=Vcc, all other pins not under test = 0V) rc) as OUTPUT LEAKAGE CURRENT i} -5 5 (Output disable, OVS VourS Vecq) poof os [os [al | LVTTL OUTPUT “H” LEVEL VOLTAGE Vv 24 v (lour= -2mA) oH ° LVTTL OUTPUT “L” LEVEL VOLTAGE Vv Vv (loyr=2mA) ot 1998-01-12 5/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 AC CHARACTERISTICS AND OPERATING CONDITIONS (Vcc = 3.3V t 0.3V, Ta=0 to 70°C) (Notes : 5, 6, 7) Fac [RetncivetoRetncive commend reios | | | | | [a fs [asnceene meer fo femol em] w fuco[AcivetoReedMive Command Dey ine | 20 | |» | | [| cco [Renee to Rear) command eed | + | [1 || owe | 9 | fur [recargetoAcive conmard ered | 20 | |» || [a fino [acivea)ioncivat) conmand rwiod fa | [|| [es] epee eS eee etetettet | [ar=3 | 8 | tooo | 10 | 1000 | fn [ekwihioerwanSSC—Ci | |] fig [ekiowiewiwatn Ss 3 | Ps || OP| eevee eee | CR fue [Oviout Ona sh pedir tine ~———S*p a Pe Ps | |) CP fiz [output bate iow mpetanee Tine «fo | fe | | [| fsa [Power Bown Mode ty Time ——SC* oe Pe fe | wo] | fs _[Faniton Tine of GK ie dra tes | [es |] [| fo; [Dat-inserwptie SSS 2 | fs |] fox [bat-inkow tine Si + | | ]CC jus [adres set-uptine ———SSSC~s 2 | ps |] fi [adires wotine ——SSSSCSCi # | |] fs [ext set-up tine SSCs 2 | os | |CC feos [ext toting SSCs PCO fas [command se-aptine Sie | pes |] fan [conmandreldtine +t + [+ || [| fur [Rete tine ——SSSSCSC—~sSCi we Pm fuse [Move Regt Sa Getine Se | tm | PT %* CL is CAS Latency. 1998-01-12 6/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 NOTES : 1. Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device. 2. All voltages are referenced to Vss. 3. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tcK and trc. Input signals are changed one time during tcx. 4, These parameters depend on the output loading. Specified values are obtained with the output open. 5. Power -up sequence is described in Note 11. 6. AC TEST CONDITIONS 3.3V o-1.4V 1.2ka 500 Output Output o—4)Z= 509) te 8700 vo A.C. TEST LOAD (A) A.C. TEST LOAD (B) 7, Transition times are measured between Vjq and Vj,. Transition (rise and fall) of input signals have a fixed slope. 8. tz defines the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels. 1998-01-12 7/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 9. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows : the number of clock cycles = specified value of timing/clock period (count fractions as a whole number ) 10. tcH is the pulse width of CLK measured from the positive edge to the negative edge referenced to Vin (min.). tcp is the pulse width of CLK measured from the negative edge to the positive edge referenced to Vy (max.). 11. Power-up Sequence Power-up must be performed in the following sequence. 1) Power must be applied to Voc and VccQ (simultaneously) while all input signals are held in the “NOP” state. The CLK signals must be started at the same time. 2) After power-up a pause of at least 200 yseconds is required. It is required that DQM and CKE signals then be held “high” (Vcc levels) to ensure that the DQ output is impedance. 3) All banks must be precharged. 4) The Mode Register Set command must be asserted to initialize the Mode Register. 5) A minimum of eight Auto Refresh dummy cycles is required to stabilize the internal circuitly of the device. The Mode Register Set command can be invoked either before or after the Auto Refresh dummy cycles. 12. A.C Latency Characteristics DQM to output in High-Z (Read DQM Latency) DQM to input data delay (Write DQM Latency) [ o | | Write command to input data (Write Data Latency) | [cS to Commadn input (Staten) perenne [a=3 | 3 | cae Precharge to Last Valid data out Burst Stop Command to DQ Hi-Z Lead time Pa=3 | 3 | Burst Stop Command to Last Valid data out Ja=3 | 2 | Read with Autoprecharge Command to Active/Ref Command oxcte Write with Autoprecharge Command to Active/Ref Command ns 1998-01-12 8/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 9998-01-12 10/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 Control Timing of Input Data (TC59S6408 /6404BFT (Word Mask) 7 y cw) EF tos) tox tos} tox ‘tou van WY van WMT vauo YY - VALID Y (Clock Mask) tos} tox tos | ton tos| tou pavwooa 7K seam Rom KLM KR KY Control Timing of Output Data (TC59S6408/6404BFT (Output Enable) . iis Y y aM =p + tac tac taz tac tac ton tou tou tz tou (Clock Mask) cxe i Lt tac tac tac tac ton tou tou tou 1998-01-12 11/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 Control Timing of Input Data (TC59S6416BFT (Word Mask) oom ante Af VAL Y Le Yo 7, a 7 a; GO Mul, SO GE GF, posooars7 stan KA _sn KA 26 KL» KZ) (Clock Mask) voor0ar 7K ocam KA _ociam KA" KR" KZ] an, Re GO Ml oe G eZ, 9998-01-12 12/57

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 Control Timing of Output Data (TC59S6416BFT (Output Enable) . iis Loqm Lj ti so Hy A = == tou tz tou tac tac tac tuz tac tou tou tou tou tiz Y Y Y GO: NY (Clock Mask) oe a Lj tac ton DQ0 to D7 Uy n> VW \\y van W7 tac 1998-01-12 13/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 | nm ; po o af 2 J 2 | - po i of 4 fT 4 | oa fo fof og L oo 1 | Reserved

Figure 1. Interleaved Bank Read (Burst Length=4 , CAS Latency=3: 0 to A9, 7S WZ LLL SSS MN BML MLN SSX ALIN.

Figure 2. Interleaved Bank Read (Burst Length=4, CAS Latency=3, Auto Precharge)

• AP is internal precharge start timing.

Figure 3. Interleaved Bank Read (Burst Length=8, CAS Latency=3)

Figure 4. Interleaved Bank Read (Burst Length=8, CAS Latency=3, Auto Precharge)

• AP is the internal precharge start timing.

Figure 5. Interleaved Bank Write (Burst Length=8)

Figure 6. Interleaved Bank Write (Burst Length=8, Auto Precharge)

• AP is the internal precharge start timing.

Figure 7. Page Mode Read (Burst Length=4, CAS Latency=3:

• AP is the internal precharge start timing.

Figure 8. Page Mode Read/Write (Burst Length=8, CAS Latency=3.

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 Figure9. Auto Precharge Read (Burst Length=4, CAS Latency=3) (CLK = 100MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 ato : CCAM MAMMMUMMMM AMA AO to 89, 777M RAW A WLLL WL XL Bank #0 ave ade tL. ace ata t Bank #1 on: Idle Bank #3 *AP is the internal precharge start timing. NOTE): See Figure 15 7998-01-12 23/51

Figure 10. Auto Precharge Write (Burst Length =4)

10 ZZ W_ ULL MLN

• AP is the internal precharge start timing.

Figure 11. Auto Refresh cycle

Figure 12. Self Refresh Cycle

Figure 13. Power Down Mode

0109 LM SS) CLL LLL ES LL LLL LL LL ON LE CE

NOTE): The Power Down mode is invoked by asserting CKE “low”. All Input/Output buffers (except the CKE buffer) are turned off in Power Down mode. When CKE goes high, the No-operation command input must be at next CLK rising edge.

Figure 14. Burst Read and Single Write (Burst Length=4, CAS Latency=3

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 PIN FUNCTIONS CLOCK INPUT: CLK The CLK input is used as the reference for S-DRAM operations. All operations are synchronized to the positive edges of CLK. CLOCK ENABLE; CKE The CKE input is used to suspend the internal CLK. When the CKE signal is asserted “low”, the internal CLK is suspended and output data is held intact while CKE is asserted “low”. When all banks are in the idle state, the CKE input controls the entry to the Power Down and Self Refresh modes. BANK SELECT: BSO, BS1 The TC59S6416BFT/BFTL, TC59S6408BFT/BFTL and the TC59S6404BFT/BFTL are organized as four- bank memory cell arrays. The BSO, BS1 inputs are latched at the time of assertion of the operation commands and selects the bank to be used for the operation. Ds pes] 4 [0 [0 | eaneno | [ota | Loa tT Bankes | ADDRESS INPUTS: A0~A11 The AO to A11 inputs are address to access the memory cell array, as following table. [ Row Address Column Address TC59S64048FT/BFTL The row address bits are latched at the Bank Activate command and column address bits are latched on the Read or Write command. Also, the AO to All inputs are used to set the data in the Mode register in a Mode Register Set cycle. 1998-01-12 29/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 CHIP SELECT: CS The CS input controls the latching of the commands on the positive edges of CLK when CS is asserted “low”. No commands are latched as long as CS is held “high”. ROW ADDRESS STROBE: RAS The RAS input defines the operation commands in conjunction with the CAS and WE inputs, and is latched at the positive edges of CLK. When RAS and CS are asserted “low” and CAS is asserted “high”, either the Bank Activate command or the Precharge command is selected by the WE signal. When WE is asserted “high”, the Bank Activate command is selected and the bank designated by BSO, BS1 are turned on so that it is in the active state. When WE is asserted “low”, the Precharge command is selected and the bank designated by BSO, BS1 are switched to the idle state after Precharge operation. COLUMN ADDRESS STROBE: CAS The CAS input defines the operation commands in conjunction with the RAS and WE inputs, and is latched at the positive edges of CLK. When RAS is held “high” and CS is asserted “low”, column access is started by asserting CAS “low”. Then, the Read or Write command is selected by asserting WE “low” or “high”. WRITE ENABLE: WE The WE input defines the operation commands in conjunction with the RAS and CAS inputs, and is latched at the positive edges of CLK. The WE input is used to select the Bank Activate or Precharge command and Read or Write command. DATA INPUT/OUTPUT MASK: DQM or L- DQM and U-DQM The DQM input enables output in a Read cycle and functions as the input data mask in a Write cycle. When DQM is asserted “high” at the positive edges of CLK, output data is disabled after two clock cycles during a Read cycle, and input data is masked at the same clock cycle during a Write cycle. In the case of the TC59S6416BFT/BFTL, the LDQM and UDQM inputs function as byte data control. The LDQM input can control DQ0-7 in a Read or Write cycle and the UDQM can control DQ8-15 in a Read or Write cycle. DATA INPUT/ OUTPUT: DQ0- 15 The DQO-15 input and output data are synchronized with the positive edges of CLK. In the case of TC59S6408BFT/BFTL and TC59S6404BFT/BFTL, these pins are DQ0-7 and DQ0-3 respectively. 1998-01-12 30/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. Table 1 Truth Table (Note (1) and (2)) [commana [owner ni oct] ot ow] on | wo Prvanal]_@ [we [OS | we leanne | we” [wt =x]x[v[v][v]c[ilale | frees te | wt x [x |v fe? v[e[w [|e | Mode fegiterset | we [|x| |v[v]v [i}elr[. | o-opeaion | Ay [w[x|x|x[x]» [i}w]w]e | feuststop | aa [|x |x| x[*] [ef] wl | foeve dest =| Aw [tx [x|x)x[» ]w[x|x |x| ile Pu [x |x |x | Self Refresh Exit L x x Power Down Mode Enrty | Idle/Active' L x pefu tu] x | Glock suspend Mode txit [| Active [| t | w | x | x [x [ x [x |x [x [x | Power Down Mode Exit Any L | x | Note (1) V=Valid x =Don’t Care L=Low level H=High level (2) CKEn signal is input level when commands are issued. CKE,.; signal is input level one clock cycle before the commands are issued. (3) These are state designated by the BSO, BS1 signals. (4) Device state is Full Page Burst operation. (5) LDQM, UDQM (TC59S6416BFT/BFTL) (6) Power Down Mode can not entry in the burst cycle. When this command assert in the burst cycle, device state is clock suspend mode. 1998-01-12 31/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 1. Command Function 1-1 Bank Activate command (RAS = “L”, CAS = “H”, WE= “H”, BS=Bank, A0 to Al1=Row Address) The Bank Activate command activates the bank designated by the BS (Bank Select) signal. Row addresses are latched on AO to All when this command is issued and the cell data is read out of the sense amplifiers. The maximum time that each bank can be held in the active state is specified as trAs(max)- 1-2 Bank Precharge command (RAS = “L”, CAS = “H”, WE= “L”, BS=Bank, A10= “L”, AO to A9, Al1=Don’t care) The Bank Precharge command precharges the bank designated by BS. The precharged bank is switched from the active state to the idle state. 1-3 Precharge All command (RAS = “L”, CAS = “H”, WE= “L”, BS=Don’t care, Al10= “H”, AO to A9, A11=Don’t care) The Precharge All command precharges all banks simultaneously. All banks are then switched to the idle state. 1-4 Write command (RAS = “H”, CAS = “L”, WE= “L”, BS=Bank, A10= “L”, AO toA9=Column Address) The Write command performs a Write operation to the bank designated by BS. The write data is latched at the positive edges of CLK. The length of the write data (Burst Length) and column access sequence (Addressing Mode) must be in the Mode Resister at power - up prior to the Write operation. The AQ input is “Don’t care” on the TC59S6408BFT/BFTL and the A8 and AQ inputs are “Don’t care” on the TC59S6416BFT/BFTL. 1-5 Write with Auto Precharge command (RAS = “H”, CAS = “L”, WE= “L”, BS=Bank, A10= “H”, AO to A9=Column Address) The Write with Auto Precharge command performs the Precharge operation automatically after the Write operation. This command must not be interrupted by any other commands. The AQ input is “Don’t care” at the TC59S6408BFT/BFTL and the A8 and AQ inputs are “Don’t care” on the TC59S6416BFT/BFTL. 1-6 Read command (RAS = “H”, CAS = “L”, WE= “H”, BS=Bank, A10= “L”, AO to A9=Column Address) The Read command performs a Read operation to the bank designated by BS. The read data is issued sequentially synchronized to the positive edges of CLK. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Write operation. The AQ input is “Don’t care” on the TC59S6408BFT/BFTL and the A8 and AQ inputs are “Don’t care” on the TC59S6416BFT/BFTL. 1998-01-12 32/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 1-7 Read with Auto Precharge command (RAS = “H”, CAS = “L”, WE= “H”, BS=Bank, A10= “H”, AO to A9=Column Address) The Read with Auto Precharge command automatically performs the Precharge operation after the Read operation. This command must not be interrupted by any other command. The AQ input is “Don’t care” on the TC59S6408BFT/BFTL and the A8 and AQ inputs are “Don’t care” on the TC59S6416BFT/BFTL. 1-8 Mode Register Set command (RAS = “L”, CAS = “L”, WE= “L”, BS, AO to All=Register Data) The Mode Register Set command programs the values of CAS latency, Addressing Mode and Burst Length in the Mode Register. The default values in the Mode Register after power - up are undefined, therefore this command must be issued during the power-up sequence. Also, this command can be issued while all banks are in the idle state. 1-9 No-Operation command (RAS = “H”, CAS = “H”, WE= “H”) The No-Operation command simply performs no operation (same command as Device Deselect). 1-10 Burst stop command (RAS = “H”, CAS = “H”, WE= “L”) The Burst stop command is used to stop the burst operation. This command is valid during a Full Page Burst operation. During other types of Burst operation, the command is illegal. 1-11 Device Deselect command (CS = “H”) The Device Deselect command disables the command decoder so that the RAS, CAS, WE and Address inputs are ignored. This command is similar to the No-Operation command. 1-12 Auto Refresh command (RAS = “L”, CAS = “L”, WE= “H”, CKE= “H”, BS, A0 toA11=Don’t care) The Auto Refresh command is used to refresh the row address provided by the internal refresh counter. The Refresh operation must be performed 4096 times within 64ms. The next command can be issued after trc from the end of the Auto Refresh command. When the Auto Refresh command is issued, All banks must be in the idle state. The Auto Refresh operation is equivalent to the CAS-before-RAS operation in a conventional DRAM. 1998-01-12 33/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 1-18 Self Refresh Entry command (RAS = “L”, CAS = “L”, WE= “H”, CKE= “L”, BS, A0 to All=Don’t care) The Self Refresh Entry command is used to enter Self Refresh mode. While the device is in Self Refresh mode, all input and output buffers (except the CKE buffer) are disabled and the Refresh operation is automatically performed. Self Refresh mode is exited by taking CKE “ high” (the Self Refresh Exit command ) 1-14 Self Refresh Exit command (CKE= “H”, CS = “H” or CKE= “H”, RAS = “H”, CAS= “H”) This command is used to exit from Self Refresh mode. Any subsequent commands can be issued after tro from the end of this command. 1-15 Clock Suspend Mode Entry /Power Down Mode Entry command (CKE= “L”) The internal CLK is suspended for one cycle when this command is issued (when CKE is asserted "low"). The device state is held intact while the CLK is suspended. On the other hand, when the device is not operating the Burst cycle, this command performs entry into Power Down mode. All input and output buffers (except the CKE buffer) are turned off in Power Down mode. 1-16 Clock Suspend Mode Exit/ Power Down Mode Exit command (CKE= “H”) When the internal CLK has been suspended, operation of the internal CLK is resumed by providing this command (asserting CKE “high”). When the device is in Power Down mode, the device exits this mode and all disabled buffers are turned on to the active state. Any subsequent commands can be issued after one clock cycle from the end of this command. 1-17 Data Write/Output Enable , Data Mask / Output Disable command (DQM= “L/H” or LDQM, UDQM=“L/H”) During a Write cycle, the DQM or LDQM, UDQM signal functions as Data Mask and can control every word of the input data. During a Read cycle, the DQM or LDQM, UDQM signal functions as the control of output buffers. The LDQM signal controls DQ0 to 7 and the UDQM signal controls DQ8 to 15. 9998-01-12 34/57

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 2. Read Operation Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after trop from the Bank Activate command, the data is read out sequentially, synchronized to the positive edges of CLK (a Burst Read operation). The initial read data becomes available after CAS latency from the issuing of the Read command. The CAS latency must be set in the Mode Register at power-up. In addition, the burst length of read data and Addressing Mode must be set. Each bank is held in the active state unless the Precharge command is issued, so that the sence amplifiers can be used as secondary cache. When the Read with Auto Precharge command is issued, the Prechage operation is performed automatically after the Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Also, when the Burst Length is 1 and trcp(min), the timing from the RAS command to the start of the Auto Precharge operation is shorter than tras(min). In this case, tpas(min) must be satisfied by extending trcp (Figure 9, 15). When the Precharge operation is performed on a bank during a Burst Read operation, the Burst operation is terminated (Figure 20). When the Burst Length is full-page, column data is repeatedly read out until the Burst Stop command or Precharge command is issued. 9998-01-12 35/57

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 3. Write Operation Issuing the Write command after trop from the Bank Activate command, the input data is latched sequentially, synchronizing with the positive edges of CLK after the Write command (Burst Write operation). The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power - up. When the Write with Auto Precharge command is issued, the Precharge operation is performed automatically after the Write cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other command for the entire burst data duration. Also, when the Burst Length is 1 and trcp(min), the timing from the RAS command to the start of the Auto Precharge operation is shorter than tras(min). In this case, tras(min) must be satisfied by extending trcp (Figure 10, 16). When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated (Figure 20). When the Burst Length is full-page, the input data is repeatedly latched until the Burst Stop command or the Precharge command is issued. When the Burst Read and Single Write mode is selected, the write burst length is 1 regardless of the read burst length. 4. Precharge There are two commands which perform the Precharge operation: Bank Precharge and Precharge All. When the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle state. The Bank Precharge command can precharge one bank independently of the other bank and hold the unprecharged bank in the active state. The maximum time each bank can be held in the active state is specifed as tras(max). Therefore, each bank must be precharged within tras(max) from the Bank Activate command. The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed only for the active bank and the precharged bank is then switched to the idle state. 9998-01-12 36/57

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 5. Page Mode The Read or Write command can be issued on any clock cycle. Whenever a Read operation is to be interrupted by a Write command, the output data must be masked by DQM to avoid I/O conflict. Also, when a Write operation is to be interrupted by a Read command, only the input data before the Read command is enable and the input data after the Read command is disabled. 6, Burst Termination When the Precharge command is issued for a bank in a Burst cycle, the Burst operation is terminated. When the Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of (CAS latency-1) from the Precharge command (Figure 20). When the Burst Write cycle is interrupted by the Precharge command, the input circuit is reset at the same clock cycle at which the Precharge command is issued. In this case, the DQM signal must be asserted “High” to prevent writing the invalid data to the cell array (Figure 20). When the Burst Stop command is issued for the bank in a Full-page Burst cycle, the Burst operation is terminated. When the Burst Stop command is issued during Full-page Burst Read cycle, read operation is disabled after clock cycle of (CAS latency-1) from the Burst Stop command. When the Burst Stop command is issued during a Full-page Burst Write cycle, write operation is disabled at the same clock cycle at which the Burst Stop command is issued. (Figure 19) 1998-01-12 37/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 7. Mode Register Operation The Mode register designates the operation mode for the Read or Write cycle. This register is divided into three fields; A Burst Length field to set the length of burst data, an Addressing Mode selected bits to designate the column access sequence in a Burst cycle, and a CAS Latency field to set the access time in clock cycle. The Mode Register is programmed by the Mode Register Set command when all banks are in the idle state. The data to be set in the Mode Register is transferred using the AQ to All address inputs. The initial value of the Mode Register after power-up is undefined; therefore the Mode Register Set command must be issued before proper operation. ¢ Burst Length field (A2 to AO) This field specifies the data length for column access using the A2to AO pins and sets the Burst Length to be 1, 2, 4, 8 words, or full-page. [ae [A | 0] tenant] re poo | 1 fo | words | ee Full-Page @ Addressing Mode Select (A3) The Addressing Mode can be one of two modes; Interleave mode or Sequential mode. When the A3 bit is “0”, Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both Addressing modes support burst length of 1, 2, 4 and 8 words. Additionally, Sequential mode supports the full-page burst. Addressing mode Po | seauentat [1 tereave | 1998-01-12 38/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 e@ Addressing sequence of Sequential mode A column access is performed by incrementing the column address input to the device. The address is varied by the Burst Length as shown in Table 2. Table 2 Addressing sequence for Sequential mode | patao | ons 2 words (Address bits is AO) } not carried from AO to A1 4 words (Address bits is A1,A0) not carried from A1 to A2 8 words (Address bits is A2, A1, AO) not carried from A2 to A3 @ Addressing sequence of Interleave mode A column access is started from the input column address and is performed by inverting the address bits in the sequence shown in Table 3. Table 3 Addressing sequence for Interleave mode —_ 2 words | words 8 words 9998-01-12 39/57

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 Addressing sequence example (Burst Length =8 and input address is 13.) DATA Sequential mode A8 A7 AG AS A4 AZ A2 A1 AO|ADD| [ADD] | Batao foo 0 0 0 1 1 0 1|3]| 73] 13 | , OO 0 0 OT TO Of 12 faset] 14 | aulated using | Dataz foo OOO tt 1 1 15 [iseo] 15 | M Al and A [datas [000 0 0 1 1 1 0| 14 [13+3| 8 |" 000001001] 9 [1344] 9 |not carry from 0000 0 1 0 0 Of B [i345 1 |A2 to A3 bit [datas [oo 000 1 0 1 1] 11 [1346] 11 [ data7 [oo oot to 0 P3712 Read Cycle TAS Latency =3 0 1 2 3 4 5 6 7 8 9 10 #11 command (Read) ee adress (3) BG i DQ0-7 {ao XarxX 2K aX ar KX a5 X06 X07 ) Data interleave mode 13-1215 14 Address | sequential mode 13 14 15 8 9 10 11 12 © CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the Read command to the first data read. The minimum values of CAS Latency depends on the frequency of CLK. The minimum value which satisfies the following formula must be set in this field. tcac (min) = CAS Latency X tox [of + [0 [2 dock] Lo 3 lock @ Test mode entry bit (A7) This bit is used to enter Test mode and must be set to“0” for normal operation. © Reserved bits (A8, A10, All, BS) These bits are reserved for future operations. They must be set to“0” for normal operation. @ Single Write mode (A9) This bit is used to select the write mode. When the AQ bit is “0”, Burst Read and Burst Write mode are selected. When the AQ bit is “1”, Burst Read and Single Write mode are selected. PAs write Mode _| } 0 i Burst Read and Burst Write Burst Read and Single Write 1998-01-12 40/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 8. Refresh Operation Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS-before-RAS refresh of conventional DRAMs and is performed by issuing the Auto Refresh command while all banks are in the idle state. By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation must be performed 4096 times (rows) within 64ms (Figure 11). The period between the Auto Refresh command and the next command is specified by tro. Self Refresh mode is entered by issuing the Self Refresh command (CKE asserted “low”) while all banks are in the idle state. The device is in Self Refresh mode for as long as CKE is held “low”. In Self Refresh mode all input/output buffers (except the CKE buffer) are disabled, resulting in lower power dissipation(Figure 12). 9. Power Down Mode When the device enters the Power Down mode, all input/output buffers (except CKE buffer) are disabled resulting in lower power dissipation in the idle state. Power Down mode is entered by asserting CKE “low” while the device is not running a Burst cycle. Taking CKE “high” exit this mode. When CKE goes high, a No-operation command must be input at next CLK rising edge of CLK (Figure 13). 10.CLK suspension and Input/Output Mask When the device is running a Burst cycle, the internal CLK is suspended by asserting CKE “low” and is frozen from the next cycle. A Read/Write operation is held intact until the CKE signal is taken “high”. The Output Disable/Write Mask signal (DQM) has two functions, controlling the output data in a Read cycle and performing word mask in a Write cycle. When the DQM is asserted “high” at the positive edge of CLK, the output data is disabled after two clock cycles in the case of a Read operation and the write data is masked at the same clock cycle in the case of a Write operation. The timing relation between the CKE timing and DQM is described in Figure21(a) and 21(b). 1998-01-12 41/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 Figure15. Auto Precharge timing (Read cycle) (1)GS Latency = 2 o 1 2 3 4 5 6 7 8 9 10 11 12 13 (a)Burst Length = 1 Po : i i : : i : : : pa (b)Burst Length = 2 E PoE Gg po i | DQ (20 X21} — — (¢) Burst Length = 4 H i i Po i : : : i i oq —— aX aKa Xey— — (d)Burst Length = 8 i : : : : i Hl i i i oa {20 Kar KX a2 K 03 X24 X05 KX 96 K_Q7)-———+ (2)CAS Latency = 3 : i H H H i H H : : H i i (a)Burst Length = 1 i i H ; i : : : : i i : (b)Burst Length = 2 i H i : H H : : DQ (c) Burst Length = 4 : : : i H Hl : : : : : DQ — (20 X_a1 X a2 X93 + — (d)Burst Length = 8 i i H Hi Hi H : i : PoE DC oe ore DQ — (20 Kar KX a2 X03 X a4 X05 XK a6 XQ7 = Note) @ represents the Read with Auto Precharge command. @ <p’, represents the start of internal precharging. ° Chat} represents the Bank Activate command. © When the Auto Precharge command is asseted, the period from the Bank Activate command to the start of internal precharging must be at least taas(min).. 1998-01-12 42/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 Figure16. Auto Precharge timing (Write cycle) 0 1 2 3 4 5 6 7 8 9 10 11 #12 = «13 (1)CAS Latency = 2 i : i i H i i : i H i (a) Burst Length = 1 : H H i H i i i i : i Command Qrite) AP: i i E : i L i : ba (b)Burst Length = 2 : H : i H H i i H i ba (c) Burst Length = 4 : H i i i i i i H i command i ORR’: PoP PG oa —{b0 Xt X02 X03 $< (d)Burst Length = 8 i i i i : i i i i i dg —{ po Kor X02 X03 X04 X05 _K 06 _X 07 ) oo (2)CAS Latency = 3 H H H : i Hi : i i : H i (a) Burst Length = 1 : i H i : i i : i : : i Command write) “AP” ae i i i i i i i i twa. _: tee E po ee! (b)Burst Length = 2 : H i : : i i H : Command ee Ce i : : i L i : ctwai, tae po PoE Gg (c) Burst Length = 4 E E i i i i : i E i (d)Burst Length = 8 H : i i i i i E i Command BG : 7 Bog pa—{oo X01 X02 X03 Xo4 X05 X06 X07 ) —— Note) ¢ represents the Write with Auto Precharge command @ < AP represents the start of internal precharging. . (Act) represents the Bank Activate command. @ When the Auto Precharge command is asseted, the period from the Bank Activate command to the start of internal precharging must be at least taas(min). 1998-01-12 43/51

Figure 17. Timing chart for Read-to-Write cycle Note) © The output data must be masked by DQM to avoid I/O conflict.

Figure 18. Timing chart for Write-to-Read cycle

Figure 19. Timing chart for Burst Stop cycle (Burst_stop command,

TOSHIBA T1C5956416/08/04BFT/BFTL-80,-10 Figure20. Timing chart for Burst Stop cycle (Precharge command) 0 1 2 3 4 5 6 7 8 9 0 1 12 In the case of Burst Length = 8 ! } } i : i : i : : : (1)Read cycle E : i : : : i i : i (a)CAS Latency = 2 : : E i i i i : pQ {20 X91 X02 X03 X a4) ; ———+ (b)CAS Latency = 3 i : : Hl i : : i i i (a) CAS Latency = 2 i i : : : : : : Command po ob Po o¢ i Bo pam va {po X01 X02 X03 X04) : — — (b)CAS Latency = 3 ; : : : : : : i : : Note) @ represents the Precharge command. 88-01-12 7ST

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 Figure21(a). _CKE/DQM Input timing (Write cycle) CLK cycle No. 1 2 3 4 5 6 7 Internal f f é f DQM MASK CKE MASK (1) CLK cycle No. 1 2 3 4 5 6 7 cux( “an Internal DQM MASK CKE MASK (2) CLK cycle No. 1 2 3 4 5 6 7 cux( meena : Hq : i CKE MASK (3) 1998-01-12 48/51

TOSHIBA TC59S6416/08/04BFT/BFTL-80,-10 Figure21(b). CKE, DQM Input timing (Read cycle) CLK cycle No. 1 2 3 4 5 6 7 au( i i : : : Internal / \\_/ \\_/ \\_/ = f \\_/ \\L— poem i p—— H > i pa__an X_ a XX _3_ XK _ 4 oN A 8) (1) CLK cycle No. 1 2 3 4 5 6 7 Internal / \\ / \\_/ \\,/ / + ae — dQ 2 93 OPEN {96 _) (2) CLK cycle No. 1 2 3 4 5 6 7 aux( i \\ ; i i Internal f / \\ ~——__/ \\_/ \\/ \\/ ) ba a1 X_@ XY @ Xa Xo Xo X (a) a (ar) (—3_) (a) (3) 1998-01-12 49/51

Figure 22. Self Refresh / Power Down Mode Exit Timing . represents the No-Operation command.

TOSHIBA 1C5956416/08/04BFT/BFTL-80,-10 OUTLINE DRAWING (TSOPII 54 - P - 400 - 0.80B) Unit in mm ii arte, 222 8 TT Thin hhh. 1998-01-12 51/51