TC59LM818DMB-33

TC59LM818DMB-33 TOSHIBA | Alldatasheet

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Technical content

TC59LM818DMB-33,-40 2005-10-19 1/57 Rev 1.4 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2 − 4,194,304-WORDS × 4 BANKS × 18-BITS

DESCRIPTION

Network FCRAM TM is Double Data Rate Fast Cycle Random Access Memory. TC59LM818DMB is Network FCRAMTM containing 301,989,888 memory cells. TC59LM818DMB is organized as 4,194,304-words × 4 banks × 18 bits. TC59LM818DMB feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. TC59LM818DMB can operate fast core cycle compared with regular DDR SDRAM. TC59LM818DMB is suitable for Network, Server and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAM TM is capable of high quality fast data transfer under light loading condition.

FEATURES

-33 -40 CL = 4 4.5 ns 5.0 ns CL = 5 3.75 ns 4.5 ns tCK Clock Cycle Time (min) CL = 6 3.33 ns 4.0 ns tRC Random Read/Write Cycle Time (min) 22.5 ns 25 ns tRAC Random Access Time (max) 22.5 ns 25 ns IDD1S Operating Current (single bank) (max) 235 mA 210 mA lDD2P Power Down Current (max) 65 mA 60 mA lDD6 Self-Refresh Current (max) 15 mA 15 mA

• Fully Synchronous Operation
• Double Data Rate (DDR) Data input/output are synchronized with both edges of DS / QS.
• Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and QS) is aligned to the crossings of CLK and CLK .
• Fast clock cycle time of 3.33 ns minimum Clock: 300 MHz maximum Data: 600 Mbps/pin maximum
• Quad Independent Banks operation
• Fast cycle and Short Latency
• Selectable Data Strobe
• Distributed Auto-Refresh cycle in 3.9 µs
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length CAS Latency = 4, 5, 6 Burst Length = 2, 4
• Organization: 4,194,304 words × 4 banks × 18 bits
• Power Supply Voltage V DD: 2.5 V ± 0.125V V DDQ: 1.4 V ~ 1.9 V
• Low voltage CMOS I/O covered with SSTL_18 (Half strength driver) and HSTL
• Package: 60Ball BGA, 1mm × 1mm Ball pitch (P-BGA60-0917-1.00AZ) Notice: FCRAM is trademark of Fujitsu limited, Japan.

TC59LM818DMB-33,-40 2005-10-19 2/57 Rev 1.4 PIN NAMES PIN ASSIGNMENT (TOP VIEW) PIN NAME A0~A14 Address Input BA0, BA1 Bank Address DQ0~DQ17 Data Input/Output CS Chip Select FN Function Control PD Power Down Control CLK, CLK Clock Input DS / QS Write/Read Data Strobe VDD Power ( +2.5 V) VSS Ground VDDQ Power (+1.5 V, +1.8 V) (for DQ buffer) VSSQ Ground (for DQ buffer) VREF Reference Voltage NC Not Connected A B C D E F G H J K 1 3 6 4 2 x18 L M N P R VSS DQ17 DQ0 VDD DQ16 VSSQ VDDQ DQ1 DQ15 VDDQ VSSQ DQ2 DQ14 DQ13 DQ4 DQ3 DQ12 VSSQ VDDQ DQ5 DQ11 VDDQ VSSQ DQ6 DQ10 VSSQ VDDQ DQ7 DQ9 DS QS DQ8 VREF VSS VDD A14 CLK CLK FN A13 NCA12 PD CS BA0A11 A9 BA1 A10A8 A7 A0 A1A5 A6 A2 VDDVSS A4 A3 ball pitch=1.0 x 1.0mm : Depopulated Ball Index

TC59LM818DMB-33,-40 2005-10-19 3/57 Rev 1.4 BLOCK DIAGRAM Note: The TC59LM818DMB configuration is 4 Bank of 32768 × 128 × 18 of cell array with the DQ pins numbered DQ0~DQ17. DQ0~DQ17 BANK #1 DLL CLOCK BUFFER CLK CLK PD To each block COMMAND DECODER CS FN ADDRESS BUFFER CONTROL SIGNAL GENERATOR MODE REGISTER REFRESH COUNTER A0~A14 BA0, BA1 BANK #0 MEMORY CELL ARRAY COLUMN DECODER ROW DECODER BURST COUNTER WRITE ADDRESS LATCH/ ADDRESS COMPARATOR DATA CONTROL and LATCH CIRCUIT UPPER ADDRESS LATCH READ DATA BUFFER DQ BUFFER DS LOWER ADDRESS LATCH BANK #2 BANK #3 WRITE DATA BUFFER QS

TC59LM818DMB-33,-40 2005-10-19 4/57 Rev 1.4 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT NOTES VDD Power Supply Voltage −0.3~ 3.3 V VDDQ Power Supply Voltage (for DQ buffer) −0.3~VDD+ 0.3 V VIN Input Voltage −0.3~VDD+ 0.3 V VOUT Output and DQ pin Voltage −0.3~VDDQ + 0.3 V VREF Input Reference Voltage −0.3~VDD+ 0.3 V Topr Operating Temperature (case) 0~85 °C Tstg Storage Temperature −55~150 °C Tsolder Soldering Temperature (10 s) 260 °C PD Power Dissipation 2 W IOUT Short Circuit Output Current ±50 mA Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability. RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1) (TCASE = 0°C ~ 85°C) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES VDD Power Supply Voltage 2.375 2.5 2.625 V VDDQ Power Supply Voltage (for DQ buffer) 1.4  1.9 V VREF Reference Voltage V DDQ/2 × 95% V DDQ/2 V DDQ/2 × 105% V 2 VIH (DC) Input DC High Voltage V REF + 0.125  V DDQ + 0.2 V 5 VIL (DC) Input DC Low Voltage −0.1  V REF − 0.125 V 5 VICK (DC) Differential Clock DC Input Voltage −0.1  V DDQ + 0.1 V 10 VID (DC) Differential Input Voltage. CLK and CLK inputs (DC) 0.4  V DDQ + 0.2 V 7, 10 VIH (AC) Input AC High Voltage V REF + 0.2  V DDQ + 0.2 V 3, 6 VIL (AC) Input AC Low Voltage −0.1  V REF − 0.2 V 4, 6 VID (AC) Differential InputVoltage. CLK and CLK inputs (AC) 0.55  V DDQ + 0.2 V 7, 10 VX (AC) Differential AC Input Cross Point Voltage V DDQ/2 − 0.125  V DDQ/2 + 0.125 V 8, 10 VISO (AC) Differential Clock AC Middle Level V DDQ/2 − 0.125  V DDQ/2 + 0.125 V 9, 10

TC59LM818DMB-33,-40 2005-10-19 5/57 Rev 1.4 NOTES: (1) All voltages referenced to VSS, VSSQ. (2) VREF is expected to track variations in VDDQ DC level of the transmitting device. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC). (3) Overshoot limit: VIH (max) = VDDQ + 0.7 V with a pulse width ≤ 5 ns. (4) Undershoot limit: VIL (min) = −0.7 V with a pulse width ≤ 5 ns. (5) VIH (DC) and VIL (DC) are levels to maintain the current logic state. (6) VIH (AC) and VIL (AC) are levels to change to the new logic state. (7) VID is differential voltage of CLK input level and CLK input level. (8) The value of VX (AC) is expected to equal VDDQ/2 of the transmitting device. (9) VISO means {VICK (CLK) + VICK ( CLK )} /2 (10) Refer to the figure below. (11) In the case of external termination, VTT (termination voltage) should be gone in the range of V REF (DC) ± 0.04 V. CAPACITANCE (VDD = 2.5V, VDDQ = 1.8 V, f = 1 MHz, Ta = 25°C) SYMBOL PARAMETER MIN MAX Delta UNIT CIN Input pin Capacitance 1.5 3.0 0.25 pF CINC Clock pin (CLK, CLK ) Capacitance 1.5 3.0 0.25 pF CI/O DQ, DS, QS Capacitance 2.5 3.5 0.5 pF CNC NC pin Capacitance  1.5  pF Note: These parameters are periodically sampled and not 100% tested. VISO (min) VISO (max) VICK VICK Vx V x V x Vx Vx VICK VICK CLK CLK VSS |VID (AC)|

0 V Differential

VID (AC)

TC59LM818DMB-33,-40 2005-10-19 6/57 Rev 1.4 RECOMMENDED DC OPERATING CONDITIONS (VDD = 2.5 V ± 0.125 V, VDDQ = 1.4 V ~ 1.9 V, TCASE = 0 ~ 85°C) MAX SYMBOL PARAMETER -33 -40 UNIT NOTES IDD1S Operating Current One bank read or write operation ; tCK = min; IRC = min, IOUT = 0mA ; Burst Length = 4, CAS Latency = 6, Free running QS mode ;

0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ,

Address inputs change up to 2 times during minimum IRC, Read data change twice per clock cycle 235 210 1, 2 IDD2N Standby Current All banks: inactive state ; tCK = min, CS = VIH, PD = VIH ;

0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;

Other input signals change one time during 4 × tCK, DQ and DS inputs change twice per clock cycle 95 90 1, 2 IDD2P Standby (power down) Current All banks: inactive state ; tCK = min, PD = VIL (power down) ; CAS Latency = 6, Free running QS mode ; Other input signals change one time during 4 × tCK, DQ and DS inputs are floating (VDDQ/2) 65 60 1, 2 IDD4W Write Operating Current (4Banks)

4 Bank interleaved continuous burst write operation ;

t CK = min, IRC = min ; Burst Length = 4, CAS Latency = 6, Free running QS mode ; Address inputs change once per clock cycle, DQ and DS inputs change twice per clock cycle 450 400 1, 2 IDD4R Read Operating Current (4Banks)

4 Bank interleaved continuous burst read operation ;

tCK = min, IRC = min, IOUT = 0mA ; Burst Length = 4, CAS Latency = 6, Free running QS mode ; Address inputs change once per clock cycle, Read data change twice per clock cycle 450 400 1, 2 IDD5B Burst Auto Refresh Current Refresh command at every IREFC interval ; tCK = min; IREFC = min ; CAS Latency = 6, Free running QS mode ; Address inputs change up to 2 times during minimum IREFC, DQ and DS inputs change twice per clock cycle 235 210 1, 2, 3 IDD6 Self-Refresh Current PD = 0.2 V ; Other input signals are floating (VDDQ/2), DQ and DS inputs are floating (VDDQ/2) 15 15 mA Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK, tRC and IRC. 2. These parameters define the current between V DD and VSS. 3. I DD5B is specified under burst refresh condition. Actual system should use distributed refresh that meet to t REFI specification.

TC59LM818DMB-33,-40 2005-10-19 7/57 Rev 1.4 RECOMMENDED DC OPERATING CONDITIONS (continued) (VDD = 2.5 V ± 0.125 V, VDDQ = 1.4 V ~ 1.9 V, TCASE = 0 ~ 85°C) SYMBOL PARAMETER MIN MAX UNIT NOTES ILI Input Leakage Current ( 0 V ≤ VIN ≤ VDDQ, all other pins not under test = 0 V) −5 5 µA ILO Output Leakage Current (Output disabled, 0 V ≤ VOUT ≤ VDDQ) −5 5 µA IREF VREF Current −5 5 µA IOH (DC) VOH = 1.420 V −5.6  IOL (DC) Normal Output Driver VOL = 0.280 V 5.6  IOH (DC) VOH = 1.420 V −9.8  IOL (DC) Strong Output Driver VOL = 0.280 V 9.8  IOH (DC) VOH = 1.420 V −2.8  IOL (DC) Weak Output Driver Output DC Current (VDDQ = 1.7V~1.9V) VOL = 0.280 V 2.8 mA 1 IOH (DC) VOH = VDDQ – 0.4V −4  IOL (DC) Normal Output Driver VOL = 0.4V 4  IOH (DC) VOH = VDDQ – 0.4V −8  IOL (DC) Strong Output Driver VOL= 0.4V 8  IOH (DC) Not defined   IOL (DC) Weak Output Driver Output DC Current (VDDQ = 1.4V~1.6V) Not defined   mA 1 Notes: 1. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.

TC59LM818DMB-33,-40 2005-10-19 8/57 Rev 1.4 AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (VDD = 2.5 V ± 0.125V, VDDQ = 1.4V ~ 1.9V, TCASE = 0 ~ 85°C) -33 -40 SYMBOL PARAMETER MIN MAX MIN MAX UNIT NOTES tRC Random Cycle Time 22.5  25  3 CL = 4 4.5 7.5 5.0 7.5 3 CL = 5 3.75 7.5 4.5 7.5 3 tCK Clock Cycle Time CL = 6 3.33 7.5 4.0 7.5 3 tRAC Random Access Time  22.5  25 3 tCH Clock High Time 0.45 × tCK  0.45 × tCK  3 tCL Clock Low Time 0.45 × tCK  0.45 × tCK  3 tCKQS QS Access Time from CLK −0.45 0.45 −0.6 0.6 3, 8, 10 tQSQ Data Output Skew from QS  0.25  0.3 tAC Data Access Time from CLK −0.5 0. 5 −0.65 0.65 3, 8, 10 tOH Data Output Hold Time from CLK −0.5 0.5 −0.65 0.65 3, 8 tHP CLK half period (minimum of Actual tCH, tCL) min (tCH, tCL)  min (tCH, tCL)  3 tQSP QS (read) Pulse Width t HP−tQHS  t HP−tQHS  4, 8 tQSQV Data Output Valid Time from QS t HP− tQHS  t HP− tQHS  4, 8 tQHS DQ, QS Hold Skew factor  0.055×tCK + 0.17  0.055×tCK + 0.17 tDQSS DS (write) Low to High Setup Time 0.8 × tCK 1.2 × tCK 0.8 × tCK 1.2 × tCK 3 tDSPRE DS (write) Preamble Pulse Width 0.4 × tCK  0.4 × tCK  4 tDSPRES DS First Input Setup Time 0  0  3 tDSPREH DS First Low Input Hold Time 0.3 × tCK  0.3 × tCK  3 tDSP DS High or Low Input Pulse Width 0.45 × tCK 0.55 × tCK 0.45 × tCK 0.55 × tCK 4 CL = 5 0.8  1.0  3, 4 tDSS DS Input Falling Edge to Clock Setup Time tDSPST DS (write) Postamble Pulse Width 0.45 × tCK  0.45 × tCK  4 CL = 5 0.8  1.0  3, 4 tDSPSTH DS (write) Postamble Hold Time tDS Data Input Setup Time from DS 0.35  0.4  4 tDH Data Input Hold Time from DS 0.35  0.4  4 tIS Command/Address Input Setup Time 0.6  0.7  3 tIH Command/Address Input Hold Time 0.6  0.7  3 tLZ Data-out Low Impedance Time tHZ Data-out High Impedance Time from CLK  0.5  0.65 ns 3,7,8

TC59LM818DMB-33,-40 2005-10-19 9/57 Rev 1.4 AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued) -33 -40 SYMBOL PARAMETER MIN MAX MIN MAX UNIT NOTES tQPDH Last output to PD High Hold Time 0  0  tPDEX Power Down Exit Time 0.6  0.7  3 tT Input Transition Time 0.1 1 0.1 1 tFPDL PD Low Input Window for Self-Refresh Entry −0.5 × tCK 5 −0.5 × tCK 5 ns tREFI Auto-Refresh Average Interval 0.4 3.9 0.4 3.9 5 tPAUSE Pause Time after Power-up 200  200  µs CL = 4 5  5  CL = 5 6  6  IRC Random Read/Write Cycle Time (applicable to same bank) CL = 6 7  7  IRCD RDA/WRA to LAL Command Input Delay (applicable to same bank) 1 1 1 1 CL = 4 4  4  CL = 5 5  5  IRAS LAL to RDA/WRA Command Input Delay (applicable to same bank) CL = 6 6  6  IRBD Random Bank Access Delay (applicable to other bank) 2  2  BL = 2 2  2  IRWD LAL following RDA to WRA Delay (applicable to other bank) BL = 4 3  3  IWRD LAL following WRA to RDA Delay (applicable to other bank) 1  1  CL = 4 7  7  CL = 5 7  7  IRSC Mode Register Set Cycle Time CL = 6 7  7  IPD PD Low to Inactive State of Input Buffer  2  2 IPDA PD High to Active State of Input Buffer 1  1  CL = 4 19  19  CL = 5 23  23  IPDV Power down mode valid from REF command CL = 6 25  25  CL = 4 19  19  CL = 5 23  23  IREFC Auto-Refresh Cycle Time CL = 6 25  25  ICKD REF Command to Clock Input Disable at Self-Refresh Entry IREFC  I REFC  ILOCK DLL Lock-on Time (applicable to RDA command) 200  200  cycle

TC59LM818DMB-33,-40 2005-10-19 10/57 Rev 1.4 AC TEST CONDITIONS SYMBOL PARAMETER VALUE UNIT NOTES VIH (min) Input High Voltage (minimum) V REF + 0.2 V VIL (max) Input Low Voltage (maximum) V REF − 0.2 V VREF Input Reference Voltage V DDQ/2 V VTT Termination Voltage V REF V VSWING Input Signal Peak to Peak Swing 0.8 V Vr Differential Clock Input Reference Level V X (AC) V VID (AC) Input Differential Voltage 1.0 V SLEW Input Signal Minimum Slew Rate 2.5 V/ns VOTR Output Timing Measurement Reference Voltage V DDQ/2 V 9 NOTES: (1) Transition times are measured between VIH min (DC) and VIL max (DC). Transition (rise and fall) of input signals have a fixed slope. (2) If the result of nominal calculation with regard to t CK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., t (3) These parameters are measured from the differential clock (CLK and CLK ) AC cross point. (4) These parameters are measured from signal transition point of DS crossing VREF level. (5) The tREFI (max) applies to equally distributed refresh method. The tREFI (min) applies to both burst refresh method and distributed refresh method. In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 µs (8 × 400 ns) is to 8 times in the maximum. (6) Low Impedance State is specified at V DDQ/2 ± 0.1 V from steady state. (7) High Impedance State is specified where output buffer is no longer driven. (8) These parameters depend on the clock jitter. These parameters are measured at stable clock. (9) Output timing is measured by using Normal driver strength at VDDQ = 1.7 V ∼ 1.9 V. Output timing is measured by using Strong driver strength at VDDQ = 1.4 V ∼ 1.6 V. (10) These parameters are measured at tCK = minimum ∼6.0ns. When tCK is longer than 6.0ns, these parameters are specified as below for all speed version. tCKQS (MIN/MAX) = −0.6ns / 0.6ns, tAC (MIN/MAX) = −0.65ns / 0.65ns SLEW = (VIH min (AC) − VIL max (AC))/∆T VIH min (AC) VREF VIL max (AC) VSWING VSS VDDQ AC Test Load Measurement point Output VTT 25 Ω

TC59LM818DMB-33,-40 2005-10-19 11/57 Rev 1.4 POWER UP SEQUENCE (1) As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection. (2) Apply VDD before or at the same time as VDDQ. (3) Apply VDDQ before or at the same time as VREF. (4) Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min). (5) After stable power and clock, apply DESL and take PD =H. (6) Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note: 1) (7) Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1) (8) Issue two or more Auto-Refresh commands (Note: 1). (9) Ready for normal operation after 200 clocks from Extended Mode Register programming. NOTES: (1) Sequence 6, 7 and 8 can be issued in random order. (2) L = Logic Low, H = Logic High (3) DQ output is Hi-Z state during power upsequence. Address VDD VDDQ VREF DS Q S (Free Running mode) 2.5V(TYP) 1.5V or 1.8V(TYP) 1/2 VDDQ (TYP) op-code EMRS op-code MRS QS (Uni-QS mode) EMRS MRS Auto Refresh cycle Normal Operation Low DQ (Input) Command CLK CLK PD 200us(min) tPDEX lPDA lRSC lRSC lREFC lREFC lLOCK = 200clock cycle(min) RDA MRS DESL RDA MRS DESL WRA REF DESL WRA REF DESL DESL

TC59LM818DMB-33,-40 2005-10-19 12/57 Rev 1.4 TIMING DIAGRAMS Input Timing Timing of the CLK, tT tCK CLK VIH VIL VIH VIL tCL tCH tT VIH (AC) VIL (AC) CLK CLK CLK VX VX VX VID (AC) CLK tIH tIS tIH tCK tCL tCH CS CLK CLK Refer to the Command Truth Table. tCK 1st 2nd tIS tIH tIS tIH 1st 2nd tIH tIS tIH UA, BA LA tIS tIS FN A0~A14 BA0, BA1 DS Command and Address Data DQn (input) tDS tDH tDS tDH tDS tDH tDS tDH DQm (input)

TC59LM818DMB-33,-40 2005-10-19 13/57 Rev 1.4 Read Timing (Burst Length = 4) Unidirectional DS/QS mode Note: DQ0 to DQ17 are aligned with QS. tOH CLK CLK Input (control & addresses) QS (output) DQ (output) CAS latency = 4 QS (output) DQ (output) CAS latency = 5 DS (Input) QS (output) DQ (output) CAS latency = 6 Low LAL (after RDA) tIS tIH Hi-Z tCH tCL tCK Low Low tQSQ Hi-Z Low tCKQS tCKQS tQSP tQSP tCKQS tQSQ tQSQV tQSQV tQSQ tHZ tLZ tOH tACtACtAC tCKQS tCKQS tQSP tQSP tCKQS Q0 Q1 Q2 Q3 tQSQtQSQ tQSQV tQSQV tQSQ tHZ tLZ tOH tAC tACtAC Q0 Q1 Q2 Q3 tCKQS tCKQS tQSP tQSP tCKQS tQStQSQ tQSQV tQSQV tQSQ tHZ tLZ tAC tAC tAC Q0 Q1 Q2 Q3 Low Hi-Z DESL Low

TC59LM818DMB-33,-40 2005-10-19 14/57 Rev 1.4 Read Timing (Burst Length = 4) Unidirectional DS/Free Running QS mode Note: DQ0 to DQ17 are aligned with QS. QS is always asserted in Free Running QS mode. CLK CLK Input (control & addresses) QS (output) DQ (output) CAS latency = 4 QS (output) DQ (output) CAS latency = 5 Hi-Z Hi-Z tQSQ tCKQS tCKQS tQSP tQSP tCKQS tQSQ tQSQV tQSQV tQSQ tHZ tLZ tOH tACtACtAC tCKQS tCKQS tQSP tQSP tCKQS Q0 Q1 Q2 Q3 tQSQtQSQ tQSQV tQSQV tQSQ tHZ tLZ tOH tAC tACtAC Q0 Q1 Q2 Q3 DS (Input) LAL (after RDA) tIS tIH tCH tCL tCK QS (output) DQ (output) CAS latency = 6 Hi-Z tCKQS tQSP tQSP tQSQ tQSQ tQSQV tQSQV tQSQ tHZ tLZ tOHtAC tAC tAC Q0 Q1 Q2 Q3 tCKQS tCKQS DESL

TC59LM818DMB-33,-40 2005-10-19 15/57 Rev 1.4 Write Timing (Burst Length = 4) Unidirectional DS/QS mode, Unidirectional DS/Free Running QS mode Note: DQ0 to DQ17 are sampled at both edges of DS. DQ (input) DS (input) DQ (input) CAS latency = 5 DS (input) CAS latency = 4 tDSPRE tDS tDH D0 D1 tDS tDH tDS tDH tDSS tDQSS tDSPREH tDSP tDSP tDS Preamble Postamble tDSP tDQSS tDSPRES tDSPST tDSPSTH tDH tDS tDH tDS tDH tDSS tDQSS tDSPREH tDSP tDSP Preamble Postamble tDSP tDSS tDSPRES tDSPST tDSS tDSPSTHtDQSS CLK CLK Input (control & addresses) LAL (after WRA) tIS tIH tCH tCL tCK tDSPRE DS (input) DQ (input) CAS latency = 6 tDSPRE tDSS tDSPREH tDSP tDSP tDS Preamble Postamble tDSP tDQSS tDSPRES tDSPST tDSPSTH tDH tDS tDH tDS tDH tDSS tDQSS QS (Uni-QS) QS (Free Runninig) Low DESL D2D0 D0 D2

TC59LM818DMB-33,-40 2005-10-19 16/57 Rev 1.4 tREFI, tPAUSE, IXXXX Timing CLK CLK Input (control & addresses) Command tIS t IH Note: “IXXXX” means “IRC”, “IRCD”, “IRAS”, etc. tREFI, tPAUSE, IXXXX Command tIS tIH

TC59LM818DMB-33,-40 2005-10-19 17/57 Rev 1.4 FUNCTION TRUTH TABLE (Notes: 1, 2, 3) Command Truth Table (Notes: 4)

• The First Command SYMBOL FUNCTION CS FN BA1~BA0 A14~A9 A8 A7 A6~A0 DESL Device Deselect H × × × × × × RDA Read with Auto-close L H BA UA UA UA UA WRA Write with Auto-close L L BA UA UA UA UA
• The Second Command (The next clock of RDA or WRA command) SYMBOL FUNCTION CS FN BA1~ BA0 A14~ A13 A12~ A11 A10~A9 A8 A7 A6~A0 LAL Lower Address Latch H × × V × × × × LA MRS Mode Register Set L × V L L L L V V Notes: 1. L = Logic Low, H = Logic High, × = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address, LA = Lower Address 2. All commands are assumed to issue at a valid state. 3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where CLK goes to High. 4. Operation mode is decided by the combination of 1st command and 2nd command. Refer to “STATE DIAGRAM” and the command table below. Read Command Table COMMAND (SYMBOL) CS FN BA1~BA0 A14~A9 A8 A7 A6~A0 NOTES RDA (1st) L H BA UA UA UA UA Write Command Table COMMAND(SYMBOL) CS FN BA1~ BA0 A14 A13 A12 A11 A10~ A9 A8 A7 A6~A0 WRA (1st) L L BA UA UA UA UA UA UA UA UA LAL (2nd) H × × VW0 VW1 × × × × × LA Notes: 5. A14~ A13 are used for Variable Write Length (VW) control at Write Operation. VW Truth Table Burst Length Function VW0 VW1 Write All Words L × BL=2 Write First One Word H × Reserved L L Write All Words H L Write First Two Words L H BL=4 Write First One Word H H

TC59LM818DMB-33,-40 2005-10-19 18/57 Rev 1.4 FUNCTION TRUTH TABLE (continued) Mode Register Set Command Table COMMAND (SYMBOL) CS FN BA1~BA0 A14~A9 A8 A7 A6~A0 NOTES MRS (2nd) L × V L L V V 6 Notes: 6. Refer to “MODE REGISTER TABLE”. Auto-Refresh Command Table PD FUNCTION COMMAND (SYMBOL) CURRENT STATE n − 1n CS FN BA1~BA0 A14~A9 A8 A7 A6~A0 NOTES Active WRA (1st) Standby H H L L × × × × × Auto-Refresh REF (2nd) Active H H L × × × × × × Self-Refresh Command Table PD FUNCTION COMMAND (SYMBOL) CURRENT STATE n − 1n CS FN BA1~BA0 A14~A9 A8 A7 A6~A0 NOTES Active WRA (1st) Standby H H L L × × × × × Self-Refresh Entry REF (2nd) Active H L L × × × × × × 7, 8 Self-Refresh Continue  Self Refresh L L × × × × × × × Self-Refresh Exit SELFX Self Refresh L H H × × × × × × 9 Power Down Table PD FUNCTION COMMAND (SYMBOL) CURRENT STATE n − 1n CS FN BA1~BA0 A14~A9 A8 A7 A6~A0 NOTES Power Down Entry PDEN Standby H L H × × × × × × 8 Power Down Continue  Power Power Down Exit PDEX Power Notes: 7. PD has to be brought to Low within t FPDL from REF command. 8. PD should be brought to Low after DQ’s state turned high impedance. 9. When PD is brought to High from Low, this function is executed asynchronously.

TC59LM818DMB-33,-40 2005-10-19 19/57 Rev 1.4 FUNCTION TRUTH TABLE (continued) PD CURRENT STATE n − 1 n CS FN ADDRESS COMMAND ACTION NOTES H H H × × DESL NOP H H L H BA, UA RDA Row activate for Read H H L L BA, UA WRA Row activate for Write H L H × × PDEN Power Down Entry 10 H L L × ×  Illegal Idle L × × × ×  Refer to Power Down State H H H × LA LAL Begin Read H H L × Op-code MRS/EMRS Access to Mode Register H L H × × PDEN Illegal H L L × × MRS/EMRS Illegal Row Active for Read H H H × LA LAL Begin Write H H L × × REF Auto-Refresh H L H × × PDEN Illegal H L L × × REF (self) Self-Refresh Entry Row Active for Write H H H × × DESL Continue Burst Read to End H H L H BA, UA RDA Illegal 11 H H L L BA, UA WRA Illegal 11 H L H × × PDEN Illegal H L L × ×  Illegal Read H H H × × DESL Data Write&Continue Burst Write to End H H L H BA, UA RDA Illegal 11 H H L L BA, UA WRA Illegal 11 H L H × × PDEN Illegal H L L × ×  Illegal Write H H H × × DESL NOP → Idle after IREFC H H L H BA, UA RDA Illegal H H L L BA, UA WRA Illegal H L H × × PDEN Self-Refresh Entry 12 H L L × ×  Illegal Auto-Refreshing L × × × ×  Refer to Self-Refreshing State H H H × × DESL NOP → Idle after IRSC H H L H BA, UA RDA Illegal H H L L BA, UA WRA Illegal H L H × × PDEN Illegal H L L × ×  Illegal Mode Register Accessing L L × × ×  Maintain Power Down Mode L H H × × PDEX Exit Power Down Mode → Idle after tPDEX Power Down L H L × ×  Illegal L L × × ×  Maintain Self-Refresh L H H × × SELFX Exit Self-Refresh → Idle after IREFC Self-Refreshing L H L × ×  Illegal Notes: 10. Illegal if any bank is not idle. 11. Illegal to bank in specified states; Function may be legal in the bank inidicated by Bank Address (BA). 12. Illegal if tFPDL is not satisfied.

TC59LM818DMB-33,-40 2005-10-19 20/57 Rev 1.4 MODE REGISTER TABLE Regular Mode Register (Notes: 1) ADDRESS BA1 *1 BA0 *1 A14~A8 A7 *3 A6~A4 A3 A2~A0 Register 0 0 0 TE CL BT BL A7 TEST MODE (TE) A3 BURST TYPE (BT)

0 Regular (default) 0 Sequential

1 Test Mode Entry 1 Interleave

A6 A5 A4 CAS LATENCY (CL) A2 A1 A0 BURST LENGTH (BL) 0 0 × Reserved*2 0 0 0 Reserved *2 0 1 0 Reserved *2 0 0 1 2 0 1 1 Reserved *2 0 1 0 4 1 0 0 4 0 1 1 1 0 1 5 1 × × Reserved*2 1 1 0 6 1 1 1 Reserved *2 Extended Mode Register (Notes: 4) ADDRESS BA1 *4 BA0 *4 A14~A7 A6~A5 A4~A3 A2~A1 A0 *5 Register 0 1 0 SS DIC (QS) DIC (DQ) DS QS DQ A6 A5 STROBE SELECT A4 A3 A2 A1 OUTPUT DRIVE IMPEDANCE CONTROL (DIC) 0 0 Reserved *2 0 0 0 0 Normal Output Driver 0 1 Reserved *2 0 1 0 1 Strong Output Driver 1 0 Unidirectional DS/QS 1 0 1 0 Weak Output Driver 1 1 Unidirectional DS/Free Running QS 1 1 1 1 Reserved A0 DLL SWITCH (DS)

0 DLL Enable

1 DLL Disable

Notes: 1. Regular Mode Register is chosen using the combination of BA0 = 0 and BA1 = 0. 2. “Reserved” places in Regular Mode Register should not be set. 3. A7 in Regular Mode Register must be set to “0” (low state). Because Test Mode is specific mode for supplier. 4. Extended Mode Register is chosen using the combination of BA0 = 1 and BA1 = 0. 5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.

TC59LM818DMB-33,-40 2005-10-19 21/57 Rev 1.4 STATE DIAGRAM STANDBY (IDLE) SELF- REFRESH POWER DOWN PDEN ( PD = L) PDEX ( PD = H) SELFX ( PD = H) MODE REGISTER AUTO- REFRESH ACTIVE ACTIVE (RESTORE) READ WRITE (BUFFER) PD = L PD = H WRA RDA MRSREF Command input LAL Automatic return The second command at Active state must be issued 1 clock after RDA or WRA command input. LAL

TC59LM818DMB-33,-40 2005-10-19 22/57 Rev 1.4 TIMING DIAGRAMS SINGLE BANK READ TIMING (CL = 4) CLK CLK Low DS (input) DQ (output) BL = 2 IRC = 5 cycles Hi-Z Q0 Q1 CL = 4 Command IRC = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA LAL DESL RDA LAL RDA LALDESL DESL IRC = 5 cycles Address UA LA UA LA UA LA IRAS = 4 cycles IRCD=1 cycle IRAS = 4 cycles IRCD=1 cycle IRCD=1 cycle IRAS = 4 cycles Bank Add. #0 #0 #0 Unidirectional DS/QS mode QS (output) CL = 4 Q0 Q1 Q0 CL = 4 Low DS (input) DQ (output) BL = 4 Hi-Z Q0 Q1 CL = 4 QS (output) CL = 4 Q0 Q1 Q0 CL = 4 Q2 Q3 Q2 Q3 DS (input) DQ (output) BL = 2 Hi-Z Q0 Q1 CL = 4 Unidirectional DS/Free Running QS mode QS (output) CL = 4 Q0 Q1 Q0 CL = 4 DS (input) DQ (output) BL = 4 Hi-Z Q0 Q1 CL = 4 QS (output) CL = 4 Q0 Q1 Q0 CL = 4 Q2 Q3 Q2 Q3 RDA UA

TC59LM818DMB-33,-40 2005-10-19 23/57 Rev 1.4 SINGLE BANK READ TIMING (CL = 5) IRC = 6 cycles CLK CLK Low DS (input) DQ (output) BL = 2 Hi-Z Q0 Q1 CL = 5 Command IRC = 6 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA LAL DESL RDA LAL RDA LALDESL Address UA LA UA LA UA LA IRAS = 5 cycles IRCD=1 cycle IRAS = 5 cyclesIRCD=1 cycle IRCD=1 cycle Bank Add. #0 #0 #0 Unidirectional DS/QS mode QS (output) CL = 5 Q0 Q1 Low DS (input) DQ (output) BL = 4 Hi-Z Q0 Q1 CL = 5 QS (output) CL = 5 Q0 Q1 Q2 Q3 Q2 Q3 DS (input) DQ (output) BL = 2 Unidirectional DS/Free Running QS mode QS (output) DS (input) DQ (output) BL = 4 QS (output) DESL Hi-Z Q0 Q1 CL = 5 CL = 5 Q0 Q1 Hi-Z Q0 Q1 CL = 5 CL = 5 Q0 Q1 Q2 Q3 Q2 Q3

TC59LM818DMB-33,-40 2005-10-19 24/57 Rev 1.4 SINGLE BANK READ TIMING (CL = 6) IRC = 7 cycles CLK CLK Low DS (input) DQ (output) BL = 2 Hi-Z Q0 Q1 CL = 6 Command IRC = 7 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDARDA LAL RDA LALDESL Address UA LA UA LA UA LA IRAS = 6 cyclesIRCD=1 cycle IRAS = 6 cycles IRCD=1 cycle IRCD=1 cycle Bank Add. #0 #0 #0 Unidirectional DS/QS mode QS (output) CL = 6 Q0 Q1 Low DS (input) DQ (output) BL = 4 Hi-Z Q0 Q1 CL = 6 QS (output) CL = 6 Q0 Q1Q2 Q3 Q2 DS (input) DQ (output) BL = 2 Unidirectional DS/Free Running QS mode QS (output) DS (input) DQ (output) BL = 4 QS (output) DESL Hi-Z Q0 Q1 CL = 6 CL = 6 Q0 Q1 Hi-Z Q0 Q1 CL = 6 CL = 6 Q0 Q1Q2 Q3 Q2 LAL

TC59LM818DMB-33,-40 2005-10-19 25/57 Rev 1.4 SINGLE BANK WRITE TIMING (CL = 4) CLK CLK Low DS (input) DQ (input) BL = 2 IRC = 5 cycles WL = 3 Command IRC = 5 cycles 0 1 23 4 56789 1 0 1 1 1 2 1 3 1 4 1 5 WRA LAL DESL WRA LAL WRA LALDESL DESL IRC = 5 cycles Address UA LA UA LA UA LA IRAS = 4 cycles IRCD=1 cycle IRAS = 4 cycles IRCD=1 cycle IRCD=1 cycle IRAS = 4 cycles Bank Add. #0 #0 #0 Unidirectional DS/QS mode QS (output) WL = 3 D0 D1 WL = 3 Low DS (input) DQ (input) BL = 4 D0 D1 WL = 3 QS (output) WL = 3 WL = 3 D2 D3 DS (input) DQ (input) BL = 2 Unidirectional DS/Free Running QS mode QS (output) DS (input) DQ (input) QS (output) D0 D1 D0 D1 D0 D1 D2 D3 D0 D1 D2 WL = 3 WL = 3 WL = 3 D0 D1D0 D1 D0 D1 WL = 3 WL = 3 WL = 3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 BL = 4 WRA UA

TC59LM818DMB-33,-40 2005-10-19 26/57 Rev 1.4 SINGLE BANK WRITE TIMING (CL = 5) IRC = 6 cycles CLK CLK Low DS (input) DQ (input) BL = 2 WL = 4 Command IRC = 6 cycles 0 1 23 4 56789 1 0 1 1 1 2 1 3 1 4 1 5 WRA LAL DESL WRA LAL WRA LALDESL Address UA LA UA LA UA LA IRAS = 5 cycles IRCD=1 cycle IRAS = 5 cycles IRCD=1 cycle IRCD=1 cycle Bank Add. #0 #0 #0 Unidirectional DS/QS mode QS (output) WL = 4 Low DS (input) DQ (input) BL = 4 QS (output) DS (input) DQ (input) BL = 2 Unidirectional DS/Free Running QS mode QS (output) DS (input) DQ (input) BL = 4 QS (output) DESL D0 D1 D0 D1 WL = 4 WL = 4 D0 D1 D0 D1 D2 D3 D2 D3 WL = 4 WL = 4 D0 D1 D0 D1 D0 D1 D0 D1 D2 D3 D2 D3 WL = 4 WL = 4

TC59LM818DMB-33,-40 2005-10-19 27/57 Rev 1.4 SINGLE BANK WRITE TIMING (CL = 6) IRC = 7 cycles CLK CLK Low DS (input) DQ (input) BL = 2 WL = 5 Command IRC = 7 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 WRAWRA LAL WRA LALDESL Address UA LA UA LA UA LA IRAS = 6 cycles IRCD=1 cycle IRAS = 6 cycles IRCD=1 cycle IRCD=1 cycle Bank Add. #0 #0 #0 Unidirectional DS/QS mode QS (output) WL = 5 Low DS (input) DQ (input) BL = 4 QS (output) DS (input) DQ (input) BL = 2 Unidirectional DS/Free Running QS mode QS (output) DS (input) DQ (input) BL = 4 QS (output) DESL LAL D0 D1 WL = 5 WL = 5 WL = 5 WL = 5 WL = 5 WL = 5 D0 D1 D0 D1 D2 D3D0 D1 D2 D3 D0 D1 D0 D1 D0 D1 D2 D3D0 D1 D2 D3

TC59LM818DMB-33,-40 2005-10-19 28/57 Rev 1.4 SINGLE BANK READ-WRITE TIMING (CL = 4) CLK CLK Low DS (input) DQ BL = 2 IRC = 5 cycles Hi-Z CL = 4 Command IRC = 5 cycles 0 1 23 4 56789 1 0 1 1 1 2 1 3 1 4 1 5 RDA LAL DESL RDA LAL WRA LALDESL DESL IRC = 5 cycles Address UA LA UA LA UA LA Bank Add. #0 #0 #0 Unidirectional DS/QS mode QS (output) WL = 3 CL = 4 Low DS (input) DQ BL = 4 Hi-Z CL = 4 QS (output) WL = 3 CL = 4 DS (input) DQ BL = 2 Hi-Z CL = 4 Unidirectional DS/Free Running QS mode QS (output) WL = 3 CL = 4 DS (input) DQ BL = 4 Hi-Z CL = 4 QS (output) WL = 3 CL = 4 Read data Write data WRA UA Q0 Q1 D0 D1 Q0 Q1 D0 D1 Q0Q2 Q3 D2 D3 Q0 Q1 D0 D1 Q0 Q0 Q1 Q0Q2 Q3 D0 D1 D2 D3

TC59LM818DMB-33,-40 2005-10-19 29/57 Rev 1.4 SINGLE BANK READ-WRITE TIMING (CL = 5) CLK CLK DS (input) DQ BL = 2 Command 0 1 23 4 56789 1 0 1 1 1 2 1 3 1 4 1 5 DESL Address Bank Add. Unidirectional DS/QS mode QS (output) DS (input) DQ BL = 4 QS (output) DS (input) DQ BL = 2 Unidirectional DS/Free Running QS mode QS (output) DS (input) DQ BL = 4 QS (output) IRC = 6 cycles Low Hi-Z CL = 5 IRC = 6 cycles RDA LAL RDA LAL WRA LALDESL UA LA UA LA UA LA #0 #0 #0 WL = 4 Low Hi-Z CL = 5 DESL Hi-Z CL = 5 Hi-Z CL = 5 WL = 4 WL = 4 WL = 4 Read data Write data Q0 Q1 Q2 Q3 D0 D1 D2 D3 Q0 Q1 D0 D1 Q0 Q1 Q2 Q3 D0 D1 D2 D3 Q0 Q1 D0 D1

TC59LM818DMB-33,-40 2005-10-19 30/57 Rev 1.4 SINGLE BANK READ-WRITE TIMING (CL = 6) IRC = 7 cycles CLK CLK Low DS (input) DQ BL = 2 Hi-Z CL = 6 Command IRC = 7 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDARDA LAL WRA LALDESL Address UA LA UA LA UA LA Bank Add. #0 #0 #0 Unidirectional DS/QS mode QS (output) WL = 5 Low DS (input) DQ BL = 4 Hi-Z CL = 6 QS (output) DS (input) DQ BL = 2 Unidirectional DS/Free Running QS mode QS (output) DS (input) DQ (output) BL = 4 QS (output) DESL Hi-Z CL = 6 Hi-Z CL = 6 LAL WL = 5 WL = 5 WL = 5 Read data Write data Q0 Q1 Q2 Q3 D0 D1 D2 D3 Q0 Q1 D0 D1 Q0 Q1 D0 D1 Q0 Q1 Q2 Q3 D0 D1 D2 D3

TC59LM818DMB-33,-40 2005-10-19 31/57 Rev 1.4 MULTIPLE BANK READ TIMING (CL = 4) RDA UA Bank "b" CLK CLK Low DS (input) DQ (output) BL = 2 IRBD = 2 cycles Hi-Z Qa0Qa1 CL = 4 Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LAL RDARDA LAL RDA LAL Address UA LA UA LA UA LA Bank Add. Bank "a" Unidirectional DS/QS mode QS (output) CL = 4 DS (input) BL = 4 RDA LAL DESL IRBD = 2 cycles RDA LAL RDA IRBD = 2 cyclesIRBD = 2 cycles LAL RDA LAL UA LA UA LA UA LA UA Bank "b" Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" IRC (Bank"a") = 5 cycles IRC (Bank"b") = 5 cycles Qb0Qb1 Qa0Qa1 Qb0 Qb1 Qc0Qc1 IRBD = 2 cycles DQ (output) Hi-Z QS (output) DS (input) DQ (output) BL = 2 Unidirectional DS/Free Running QS mode QS (output) DS (input) DQ (output) BL = 4 QS (output) Low CL = 4 CL = 4 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0Qc1Qc2 CL = 4 CL = 4 CL = 4 CL = 4 Note: lRC to the same bank must be satisfied. Hi-Z Qa0Qa1 Qb0Qb1 Qa0Qa1 Qb0 Qb1 Qc0Qc1 Hi-Z Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0Qc1Qc2 LA

TC59LM818DMB-33,-40 2005-10-19 32/57 Rev 1.4 MULTIPLE BANK READ TIMING (CL = 5) CLK CLK DS (input) DQ (output) BL = 2 Hi-Z CL = 5 Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA LALRDA LAL RDA Address UA LA UA LA UA Bank Add. Bank "a" Unidirectional DS/QS mode QS (output) CL = 5 DS (input) DQ (output) BL = 4 Hi-Z QS (output) DS (input) DQ (output) BL = 2 Hi-Z Unidirectional DS/Free Running QS mode QS (output) DS (input) DQ (output) BL = 4 Hi-Z QS (output) RDA LAL LAL RDA LAL RDA LAL RDA UA LA LA UA LA UA LA UA Bank "b" Bank "a" Bank "b" Bank "c" Bank "d" IRC (Bank"a") = 6 cycles IRC (Bank"b") = 6 cycles Low Low CL = 5 CL = 5 CL = 5 CL = 5 CL = 5 CL = 5 Note: lRC to the same bank must be satisfied. DESL Bank "a" IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles LAL LA Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0 Qa1 Qa2 Qa3 Qb0Qb1Qb2 Qa0Qa1 Qb0Qb1 Qa0 Qa1 Qb0Qb1 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0 Qa1 Qa2 Qa3 Qb0Qb1Qb2 Qa0Qa1 Qb0Qb1 Qa0 Qa1 Qb0Qb1

TC59LM818DMB-33,-40 2005-10-19 33/57 Rev 1.4 MULTIPLE BANK READ TIMING (CL = 6) CLK CLK Low DS (input) DQ (output) BL = 2 Hi-Z CL = 6 Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA LAL RDA LAL Address UA LA UA LA UA Bank Add. Bank "a" Unidirectional DS/QS mode QS (output) CL = 6 DS (input) DQ (output) BL = 4 Hi-Z QS (output) DS (input) DQ (output) BL = 2 Unidirectional DS/Free Running QS mode QS (output) DS (input) DQ (output) BL = 4 QS (output) RDA LAL LAL RDA LAL RDA LAL UA LA LA UA LA UA LA Bank "b" Bank "b" Bank "c" Bank "d" IRC (Bank"a") = 7 cycles IRC (Bank"b") = 7 cycles Low CL = 6 CL = 6 CL = 6 CL = 6 CL = 6 CL = 6 Bank "a" DESL IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles RDA UA Bank "a" Hi-Z Hi-Z RDA Qa0Qa1 Qb0 Qa0Qa1Qb1 Qa0Qa1Qa2Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1 Qb0Qb1 Qa0Qa1 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2

TC59LM818DMB-33,-40 2005-10-19 34/57 Rev 1.4 MULTIPLE BANK WRITE TIMING (CL = 4) CLK CLK Low DS (input) DQ (input) BL = 2 WL = 3 Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LAL WRAWRA LAL WRA LAL Address UA LA UA LA UA LA Bank Add. Bank "a" Unidirectional DS/QS mode QS (output) WL = 3 DS (input) DQ (input) BL = 4 QS (output) Unidirectional DS/Free Running QS mode WRA LAL DESL WRA LAL WRA LAL WRA LAL UA LA UA LA UA LA UA LA Bank "b" Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" IRC (Bank"a") = 5 cycles IRC (Bank"b") = 5 cycles Db0Db1 Da0Da1 Db0Db1 Dc0 Dc1 Low Da0 Da1 Da2Da3Db0Db1Db2Db3 Da0Da1Da2Da3Db0Db1 Db2 Db3 Dc0 Dc1 Dc2Dc3 Note: lRC to the same bank must be satisfied. IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles Da0 Da1 Dd0Dd1 WL = 3 WL = 3 Dd0Dd1 DS (input) DQ (input) BL = 2 WL = 3 QS (output) WL = 3 DS (input) DQ (input) BL = 4 QS (output) Db0Db1 Da0Da1 Db0Db1 Dc0 Dc1 Da0 Da1 Da2Da3Db0Db1Db2Db3 Da0Da1Da2Da3Db0Db1 Db2 Db3 Dc0 Dc1 Dc2Dc3 Da0 Da1 Dd0Dd1 WL = 3 WL = 3 Dd0Dd1 WRA UA Bank "b"

TC59LM818DMB-33,-40 2005-10-19 35/57 Rev 1.4 MULTIPLE BANK WRITE TIMING (CL = 5) CLK CLK Low DS (input) DQ (input) BL = 2 WL = 4 Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 WRA LALWRA LAL WRA Address UA LA UA LA UA LA Bank Add. Unidirectional DS/QS mode QS (output) WL = 4 DS (input) DQ (input) BL = 4 QS (output) Unidirectional DS/Free Running QS mode WRA LAL LAL WRA LAL WRA LAL WRA UA LA UA LA UA LA UA Bank "b" Bank "c" Bank "d" Bank "a" IRC (Bank"a") = 6 cycles IRC (Bank"b") = 6 cycles Db0Db1 Da0Da1 Db0 Db1 Dc0Dc1 Low Da0Da1Da2Da3Db0Db1Db2Db3 Da0Da1 Da2 Da3 Db0 Db1 Db2Db3Dc0Dc1 Note: lRC to the same bank must be satisfied. IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles Da0Da1 DESL WL = 4 WL = 4 DS (input) DQ (input) BL = 2 WL = 4 QS (output) WL = 4 DS (input) DQ (input) BL = 4 QS (output) Db0Db1 Da0Da1 Db0 Db1 Dc0Dc1 Da0Da1Da2Da3Db0Db1Db2Db3 Da0Da1 Da2 Da3 Db0 Db1 Db2Db3Dc0Dc1 Da0Da1 WL = 4 WL = 4 LAL LA Bank "a" Bank "b" Bank "a"

TC59LM818DMB-33,-40 2005-10-19 36/57 Rev 1.4 MULTIPLE BANK WRITE TIMING (CL = 6) Note: lRC to the same bank must be satisfied. CLK CLK Low DS (input) DQ (input) BL = 2 WL = 5 Command 0 1 23 4 56789 1 0 1 1 1 2 1 3 1 4 1 5 WRA LAL WRA LAL WRA Address UA LA UA LA UA LA Bank Add. Bank "a" Unidirectional DS/QS mode QS (output) WL = 5 DS (input) DQ (input) BL = 4 QS (output) Unidirectional DS/Free Running QS mode WRA LAL LAL WRA LAL WRA LAL WRA UA LA UA LA UA LA UA Bank "b" Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" IRC (Bank"a") = 7 cycles IRC (Bank"b") = 7 cycles Db0Db1 Da0 Da1 Db0Db1 Low Da0Da1Da2Da3Db0Db1Db2Db3 Da0 Da1 Da2Da3Db0Db1 IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles Da0Da1 DESL WL = 5 WL = 5 DS (input) DQ (input) BL = 2 WL = 5 QS (output) WL = 5 DS (input) DQ (input) BL = 4 QS (output) Db0Db1 Da0 Da1 Db0Db1 Da0Da1Da2Da3Db0Db1Db2Db3 Da0 Da1 Da2Da3Db0Db1 Da0Da1 WL = 5 WL = 5

TC59LM818DMB-33,-40 2005-10-19 37/57 Rev 1.4 MULTIPLE BANK READ-WRITE TIMING (BL = 2) CLK CLK DS (input) CL = 4 IRBD = 2 cycles WL =3 Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Address Bank Add. Unidirectional DS/QS mode CL =4 Unidirectional DS/Free Running QS mode IRC (Bank"a") IRC (Bank"b") IWRD = 1 cycle IRWD = 2 cycles IWRD = 1 cycle IRWD =2 cycles QS (output) Low DQ Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1Hi-Z DS (input) CL = 5 WL =4 QS (output) CL =5 Low DS (input) CL = 6 WL =5 CL =6 QS (output) Low WRADESLWRAWRAWRA RDALAL LAL DESL DESL RDA LAL LAL RDA LAL LAL UA LA UA LA UA LA UA LA UA LA UA LA UA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" Bank "b" Bank "c" DQ Hi-Z Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1 DQ Hi-Z Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 DS (input) CL = 4 WL =3 CL =4 QS (output) DQ Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1Hi-Z DS (input) CL = 5 WL =4 QS (output) CL =5 DS (input) CL = 6 WL =5 CL =6 QS (output) DQ Hi-Z Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1 DQ Hi-Z Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Note: lRC to the same bank must be satisfied.

TC59LM818DMB-33,-40 2005-10-19 38/57 Rev 1.4 MULTIPLE BANK READ-WRITE TIMING (BL = 4) CLK CLK DS (input) CL = 4 IRBD = 2 cycles WL =3 Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Address Bank Add. Unidirectional DS/QS mode CL =4 Unidirectional DS/Free Running QS mode IRC (Bank"a") IRC (Bank"b") IWRD = 1 cycle IRWD = 3 cycles IWRD = 1 cycle IRWD =3 cycles QS (output) DQ Hi-Z DS (input) CL = 5 WL =4 QS (output) CL =5 Low DS (input) CL = 6 WL =5 CL =6 QS (output) Low DQ Hi-Z DQ Hi-Z DS (input) CL = 4 WL =3 CL =4 QS (output) DQ Hi-Z DS (input) CL = 5 WL =4 QS (output) CL =5 DS (input) CL = 6 WL =5 CL =6 QS (output) DQ Hi-Z DQ Hi-Z Note: lRC to the same bank must be satisfied. LALRDAWRA RDALAL LAL LAL LALWRA RDA WRA LAL DESL DESL UA LA UA LA UA LA UA UA LA LA UALA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" Bank "b" Low Qb0 Qb1Da0 Da1 Da2 Da3 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3 Qb0 Qb1Da0 Da1 Da2 Da3 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3 Qb0 Qb1Da0 Da1 Da2 Da3 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3 Qb0 Qb1Da0 Da1 Da2 Da3 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3 Qb0 Qb1Da0 Da1 Da2 Da3 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qb0 Qb1Da0 Da1 Da2 Da3 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 IWRD = 1 cycle

TC59LM818DMB-33,-40 2005-10-19 39/57 Rev 1.4 WRITE with VARIABLE WRITE LENGTH (VW) CONTROL (CL = 4) CLK CLK DS (input) Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 WRA LAL WRA LALDESL Address UA LA=#3 VW=All UA Bank Add. Bank "a" Bank "a" BL = 2, SEQUENTIAL MODE DESL LA=#1 VW=1 VW0 = Low VW1 = don't care VW0 = High VW1 = don't care DQ (input) D0D0 D1 Lower Address #3 #2 #1 (#0) Last one data is masked. DS (input) Command WRA LAL WRA LALDESL Address UA LA=#3 VW=All UA Bank Add. Bank "a" Bank "a" BL = 4, SEQUENTIAL MODE DESL LA=#1 VW=1 DQ (input) D0D0 D1 Lower Address #3 #0 #1(#2)(#3)(#0) Last three data are masked. DESL WRA LAL VW0 = High VW1 = Low VW0 = High VW1 = High UA LA=#2 VW=2 VW0 = Low VW1 = High Bank "a" D2 D3 D0 D1 #1 #2 Last two data are masked. (#0)(#1)#2 #3 Note: DS input must be continued till end of burst count even if some of laster data is masked.

TC59LM818DMB-33,-40 2005-10-19 40/57 Rev 1.4 POWER DOWN TIMING (CL = 4, BL = 4) Read cycle to Power Down Mode CLK CLK 0 1 2 3 4 5 6 7 8 9 10 n-2 n-1 n n+1 n+2 Power Down Entry Power Down Exit Note: PD must be kept "High" level until end of Burst data output. PD should be brought to "High" within tREFI(max.) to maintain the data written into cell. In Power Down Mode, PD "Low" and a stable clock signal must be maintained. When PD is brought to "High", a valid executable command may be applied lPDA cycles later. QS (output) DS (input) Low Hi-Z Q0 Q1 CL = 4 Q2 Q3 Hi-Z DQ (output) QS (output) DS (input) Hi-Z Q0 Q1 CL = 4 Q2 Q3 Hi-Z DQ (output) Unidirectional DS/Free Running QS mode tIH tIS IPD = 2 cycle tPDEX Command RDA LAL DESL Address UA UA RDA or WRA LA lRC(min) , tREFI(max) tQPDH Unidirectional DS/QS mode PD DESL IPDA

TC59LM818DMB-33,-40 2005-10-19 41/57 Rev 1.4 POWER DOWN TIMING (CL = 4, BL = 4) Write cycle to Power Down Mode CLK CLK 0 1 2 3 4 5 6 7 8 9 10 n-2 n-1 n n+1 n+2 Note: PD must be kept "High" level until WL+2 clock cycles from LAL command. PD should be brought to "High" within tREFI(max.) to maintain the data written into cell. In Power Down Mode, PD "Low" and a stable clock signal must be maintained. When PD is brought to "High", a valid executable command may be applied lPDA cycles later. QS (output) DS (input) Low WL = 3 D0 D1 D2 D3 DQ (input) QS (output) DS (input) DQ (input) Unidirectional DS/Free Running QS mode WL = 3 D0 D1 D2 D3 tIH tIS IPD = 2 cycle tPDEX Command WRA LAL Address UA LA lRC(min) , tREFI(max) Unidirectional DS/QS mode PD 2 clock cyclesWL = 3 UA DESL RDA or WRADESL IPDA

TC59LM818DMB-33,-40 2005-10-19 42/57 Rev 1.4 MODE REGISTER SET TIMING (CL = 4, BL = 2) From Read operation to Mode Register Set operation. CLK CLK DS (input) Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RDA LAL RDA MRSDESL A14~A0 UA Valid (opcode) QS (output) IRSC = 7 cycles DESL RDA or WRA LA UA BA0, BA1 BA BA0="0" BA1="0" BA Unidirectional DS/QS mode Unidirectional DS/Free Running QS mode LAL DQ (output) DS (input) QS (output) DQ (output) CL + BL/2 Low Q0 Q1 Q0 Q1 Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2. LA

TC59LM818DMB-33,-40 2005-10-19 43/57 Rev 1.4 MODE REGISTER SET TIMING (CL = 4, BL = 4) From Write operation to Mode Register Set operation. CLK CLK DS (input) Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 WRA LAL RDA MRSDESL A14~A0 UA Valid (opcode) QS (output) IRSC = 7 cycles DESL RDA or WRA LA UA BA0, BA1 BA BA0="0" BA1="0" BA Unidirectional DS/QS mode Unidirectional DS/Free Running QS mode Low D0 D1 D2 D3 DQ (input) DS (input) QS (output) D0 D1 D2 D3 DQ (input) WL+BL/2 LA LAL Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.

TC59LM818DMB-33,-40 2005-10-19 44/57 Rev 1.4 EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 2) From Read operation to Extended Mode Register Set operation. CLK CLK DS (input) Command 0 1 23 4 56789 1 0 1 1 1 2 1 3 1 4 RDA LAL RDA MRSDESL A14~A0 UA Valid (opcode) QS (output) IRSC = 7 cycles DESL RDA or WRA LA UA BA0, BA1 BA BA0="1" BA1="0" BA Unidirectional DS/QS mode Unidirectional DS/Free Running QS mode DQ (output) DS (input) QS (output) DQ (output) CL + BL/2 Low Q0 Q1 Q0 Q1 Note: Minimum delay from LAL following RDA to RDA of EMRS operation is CL+BL/2. When DQ strobe mode is changed by EMRS, QS output is invalid for l RSC period. DLL switch in Extended Mode Register must be set to enable mode for normal operation. DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence. LA LAL

TC59LM818DMB-33,-40 2005-10-19 45/57 Rev 1.4 EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 4) From Write operation to Extended Mode Register Set operation. CLK CLK DS (input) Command 0 1 23 4 56789 1 0 1 1 1 2 1 3 1 4 WRA LAL RDA MRSDESL A14~A0 UA Valid (opcode) QS (output) WL+BL/2 IRSC = 7 cycles DESL RDA or WRA LA UA BA0, BA1 BA BA0="1" BA1="0" BA Unidirectional DS/QS mode Unidirectional DS/Free Running QS mode Low D0 D1 D2 D3 DQ (input) DS (input) QS (output) D0 D1 D2 D3 DQ (input) Note: When DQ strobe mode is changed by EMRS, QS output is invalid for l RSC period. DLL switch in Extended Mode Register must be set to enable mode for normal operation. DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence. Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2. LAL LA

TC59LM818DMB-33,-40 2005-10-19 46/57 Rev 1.4 AUTO-REFRESH TIMING (CL = 4, BL = 4) CLK WRA REF WRA REF WRA REF WRA REF WRA REF t1 t2 t3 t7 t8

8 Refresh cycle

tREFI = Total time of 8 Refresh cycle t1 + t2 + t3 + t4 + t5 + t6 + t7 + t8 tREFI is specified to avoid partly concentrated current of Refresh operation that is activated larger area than Read / Write operation. CLK CLK QS (output) DQ (output) 0 12 3 4567 n − 1n n + 1 n + 2 RDA LAL Hi-Z Hi-Z CL = 4 Command IRC = 5 cycles DESL RDA or WRA LAL or MRS or REF IRCD = 1 cycle Note: In case of CL = 4, IREFC must be meet 19 clock cycles. When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh command specified by t REFI must be satisfied. tREFI is average interval time in 8 Refresh cycles that is sampled randomly. WRA REF IREFC = 19 cycles Low IRAS = 4 cycles IRCD = 1 cycle DESL CLK CLK QS (output) DQ (output) RDA LAL Hi-Z Hi-Z CL = 4 Command IRC = 5 cycles DESL RDA or WRA LAL or MRS or REF IRCD = 1 cycle WRA REF IREFC = 19 cycles IRAS = 4 cycles IRCD = 1 cycle DESL Unidirectional DS/QS mode Unidirectional DS/Free Running QS mode Bank, UA LA Bank, Address Bank, UA LA Bank, Address Q0 Q1 Q2 Q3 Low Q0 Q1 Q2 Q3

TC59LM818DMB-33,-40 2005-10-19 47/57 Rev 1.4 SELF-REFRESH ENTRY TIMING SELF-REFRESH EXIT TIMING Notes: 1. is don’t care. 2. PD must be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self Refresh mode.When PD is brought to "Low" after lPDV, TC59LM818DMB perform Auto Refresh and enter Power down mode. In case of PD fall between tFPDL(max) and lPDV, TC59LM818DMB will either entry Self-Refresh mode or Power down mode after Auto-Refresh operation. It can’t be specified which mode TC59LM818DMB operates. 3. It is desirable that clock input is continued at least l CKD from REF command even though PD is brought to “Low” for Self-Refresh Entry. 4. In case of Self-Refresh entry after Write Operation, from the LAL command following WRA to the REF command delay time is Write latency(WL)+2 clock cycles minimum. CLK CLK Low QS (output) DQ (output) 0 1 2 3 4 5 m − 1mm + 1 WRA REF Qx Hi-Z Command IRCD = 1 cycle IREFC DESL tFPDL (min) tFPDL (max) IPDV *2 PD Unidirectional DS/QS mode ICKD tQPDH Auto Refresh Self Refresh Entry Hi-Z Notes: 1. is don’t care. 2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode. 3. DESL command must be asserted during I REFC after PD is brought to “High”. 4. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other operation. 5. Any command (except Read command) can be issued after I REFC. 6. Read command (RDA + LAL) can be issued after ILOCK. CLK CLK Hi-Z QS (output) DQ (output) 0 1 2 m − 1mm + 1m + 2 Hi-Z Command ILOCK tPDEX PD DESL*3 LAL*6WRA*4 REF*4 DESL RDA*6 n − 1nn + 1 p − 1 p Command (1st)*5 Command (2nd)*5 IRCD = 1 cycle Self-Refresh Exit Unidirectional DS/QS mode IREFCIREFC IRCD = 1 cycle Low

TC59LM818DMB-33,-40 2005-10-19 48/57 Rev 1.4 SELF-REFRESH ENTRY TIMING SELF-REFRESH EXIT TIMING Notes: 1. is don’t care. 2. PD must be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self Refresh mode. When PD is brought to "Low" after lPDV, TC59LM818DMB perform Auto Refresh and enter Power down mode. In case of PD fall between tFPDL(max) and lPDV, TC59LM818DMB will either entry Self-Refresh mode or Power down mode after Auto-Refresh operation. It can’t be specified which mode TC59LM818DMB operates. 3. It is desirable that clock input is continued at least l CKD from REF command even though PD is brought to “Low” for Self-Refresh Entry. 4. In case of Self-Refresh entry after Write Operation, from the LAL command following WRA to the REF command delay time is Write latency(WL)+2 clock cycles minimum. CLK CLK Hi-Z QS (output) DQ (output) 0 1 2 3 4 5 m − 1mm + 1 WRA REF Qx Hi-Z Command IRCD = 1 cycle IREFC DESL tFPDL (min) tFPDL (max) IPDV *2 PD Unidirectional DS/Free Running QS mode ICKD tQPDH Auto Refresh Self Refresh Entry Notes: 1. is don’t care. 2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode. 3. DESL command must be asserted during I REFC after PD is brought to “High”. 4. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other operation. 5. Any command (except Read command) can be issued after I REFC. 6. Read command (RDA + LAL) can be issued after ILOCK. 7. QS output is invalid until DLL lock from Self-Refresh exit. CLK CLK QS (output) DQ (output) 0 1 2 m − 1mm + 1m + 2 Hi-Z Command ILOCK tPDEX PD DESL*3 LAL*6WRA*4 REF*4 DESL RDA*6 n − 1nn + 1 p − 1 p Command (1st)*5 Command (2nd)*5 IRCD = 1 cycle Self-Refresh Exit Unidirectional DS/Free Running QS mode IREFCIREFC IRCD = 1 cycle

TC59LM818DMB-33,-40 2005-10-19 49/57 Rev 1.4 FUNCTIONAL DESCRIPTION Network FCRAMTM The FCRAMTM is an acronym of Fast Cycle Random Access Memory. The Network FCRAM TM is competent to perform fast random core access, low latency and high-speed data transfer. PIN FUNCTIONS CLOCK INPUTS: CLK & The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the negative edge of CLK . The QS and DQ output data are aligned to the crossing point of CLK and CLK . The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. POWER DOWN: The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being performed. CHIP SELECT & FUNCTION CONTROL: & FN The CS and FN inputs are a control signal for forming the operation commands on FCRAM TM. Each operation mode is decided by the combination of the two consecutive operation commands using the CS and FN inputs. BANK ADDRESSES: BA0 & BA1 The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register Set command (MRS or EMRS). BA0 BA1 Bank #0 0 0 Bank #1 1 0 Bank #2 0 1 Bank #3 1 1 ADDRESS INPUTS: A0~A14 Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank addresse s are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or Extended Mode Register set cycle. I/O Organization UPPER ADDRESS LOWER ADDRESS 18 bits A0~A14 A0~A6 CLK PD CS

TC59LM818DMB-33,-40 2005-10-19 50/57 Rev 1.4 DATA INPUT/OUTPUT: DQ0~DQ17 The input data of DQ0 to DQ17 are taken in synchronizing with the both edges of DS input signal. The output data of DQ0 to DQ17 are outputted synchronizing with the both edges of QS output signal. DATA STROBE: DS, QS Method of data strobe is chosen by Extended mode register. (1) Unidirectional DS / QS mode DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS are used for trigger signal of all DQs at Read operation. During Write, Auto-Refresh and NOP cycle, QS assert always “Low” level. QS is Hi-Z in Self-Refresh mode. (2) Unidirectional DS / Free running QS mode DS is input signal and QS is output signal. Both edge of DS are used to sample all DQs at Write operation. Both edges of QS are used for trigger signal of all DQs at Read operation. QS assert always toggle signal except Self-Refresh mode. This strobe type is easy to use for pin to pin connect application. POWER SUPPLY: VDD, VDDQ, VSS, VSSQ VDD and VSS are power supply pins for memory core and peripheral circuits. VDDQ and VSSQ are power supply pins for the output buffer. REFERENCE VOLTAGE: VREF VREF is reference voltage for all input signals.

TC59LM818DMB-33,-40 2005-10-19 51/57 Rev 1.4 COMMAND FUNCTIONS and OPERATIONS TC59LM818DMB are introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed. Read Operation (1st command + 2nd command = RDA + LAL) Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out sequentially synchronizing with the both edges of QS output signal (Burst Read Operation). Th e initial valid read data appears after CAS latency from the issuing of the LAL command. The valid data is outputted for a burst length. The CAS latency, the burst length of read data and the burst type must be set in the Mode Re gister beforehand. The read operated bank goes back automatically to the idle state after lRC. Write Operation (1st command + 2nd command = WRA + LAL) Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is latche d sequentially synchronizing with the both edges of DS input signal (Burst Write Operation). The data and DS inputs have to be asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. Th e DS has to be provided for a burst length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automatically to the idle state after l RC. Write Burst Length is controlled by VW0 and VW1 inputs with LAL command. See VW truth table. Auto-Refresh Operation (1st command + 2nd command = WRA + REF) TC59LM818DMB are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state. In a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is specified by l REFC. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distributed refresh, Auto-Refresh command has to be issued within once for every 3.9 µs by the maximum. In case of burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles that can be performed within 3.2 µs (8 × 400 ns) is to 8 times in the maximum. Self-Refresh Operation (1st command + 2nd command = WRA + REF with = “L”) In case of Self-Refresh operation, refresh operation can be performed automatically by using an internal timer. When all banks are in the idle state and all outp uts are in Hi-Z states, the TC59LM818DMB become Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to “Low” within tFPDL from the REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the refresh period, the Self-Refresh entry command should be asserted within 3.9 µs after the latest Auto-Refresh command. Once the device enters Self-Refresh mode, the DESL command must be continued for l REFC period. In addition, it is desirable that clock input is kept in l CKD period. The device is in Self-Refresh mode as long as PD held “Low”. During Self-Refresh mode, all input and output buffers are disabled except for PD , therefore the power dissipation lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from “Low” to “High” along with the DESL command, and the DESL command has to be continuously issued in the number of clocks specified by l REFC. The Self-Refresh exit function is asynchronous operation. It is required that one Auto-Refresh command is issued to avoid the violation of the refresh period just after l REFC from Self-Refresh exit. Power Down Mode ( = “L”) When all banks are in the idle state and DQ outputs are in Hi-Z states, the TC59LM818DMB become Power Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output buffers are disabled after specified time except for PD , CLK, CLK and QS. Therefore, the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to “High” and the DESL command has to be issued for lPDA cycle after PD goes high. The Power Down exit function is asynchronous operation. PD PD

TC59LM818DMB-33,-40 2005-10-19 52/57 Rev 1.4 Mode Register Set (1st command + 2nd command = RDA + MRS) When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1 address inputs. The TC59LM818DMB have two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is chosen by BA0 and BA1 in the MRS command. The Regular Mode Register designates the operation mode for a read or write cycle. The Regular Mode Register has four function fields. The four fields are as follows: (R-1) Burst Length field to set the length of burst data (R-2) Burst Type field to designate the lower address access sequence in a burst cycle (R-3) CAS Latency field to set the access time in clock cycle (R-4) Test Mode field to use for supplier only. The Extended Mode Register has three function fields. The three fields are as follows: (E-1) DLL Switch field to choose either DLL enable or DLL disable (E-2) Output Driver Impedance Control field. (E-3) Data Strobe Select Once those fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again by another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued before proper operation.

• Regular Mode Register/Extended Mode Register change bits (BA0, BA1) These bits are used to choose either Regular MRS or Extended MRS BA1 BA0 Mode Register Set 0 0 Regular MRS 0 1 Extended MRS 1 × Reserved Regular Mode Register Fields (R-1) Burst Length field (A2 to A0) This field specifies the data length for column a ccess using the A2 to A0 pins and sets the Burst Length to be 2 or 4 words. A2 A1 A0 BURST LENGTH 0 0 0 Reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 Reserved 1 × × Reserved (R-2) Burst Type field (A3) The Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is “0”, Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both burst types support burst length of 2 and 4 words. A3 BURST TYPE

0 Sequential

1 Interleave

TC59LM818DMB-33,-40 2005-10-19 53/57 Rev 1.4

• Addressing sequence of Sequential mode (A3) A column access is started from the inputted lower address and is performed by incrementing the lower address input to the device. Addressing sequence for Sequential mode DATA ACCESS ADDRESS BURST LENGTH Data 0 n Data 1 n + 1 Data 2 n + 2 Data 3 n + 3 2 words (address bits is LA0) not carried from LA0~LA1 4 words (address bits is LA1, LA0) not carried from LA1~LA2
• Addressing sequence of Interleave mode A column access is started from the inputted lower a ddress and is performed by interleaving the address bits in the sequence shown as the following. Addressing sequence for Interleave mode DATA ACCESS ADDRESS BURST LENGTH Data 0 ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0 Data 1 ּּּA8 A7 A6 A5 A4 A3 A2 A1 0A Data 2 ּּּA8 A7 A6 A5 A4 A3 A2 1A A0 Data 3 ּּּA8 A7 A6 A5 A4 A3 A2 1A 0A 2 words 4 words (R-3) CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to the first data read. The minimum value of CAS Latency depends on the frequency of CLK. In a write mode, the place of clock that should input write data is CAS Latency cycles − 1. A6 A5 A4 CAS LATENCY 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 Reserved (R-4) Test Mode field (A7) This bit is used to enter Test Mode for supplier only and must be set to “0” for normal operation. (R-5) Reserved field in the Regular Mode Register
• Reserved bits (A8 to A14) These bits are reserved for future operations. They must be set to “0” for normal operation. CLK CLK Command QS DQ Data Data Data Data RDA LAL CAS Latency = 4 (Free Running QS mode)

TC59LM818DMB-33,-40 2005-10-19 54/57 Rev 1.4 Extended Mode Register fields (E-1) DLL Switch field (A0) This bit is used to enable DLL. When the A0 bit is set “0”, DLL is enabled. This bit must be set to “0” for normal operation. (E-2) Output Driver Impedanc e Control field (A1 to A4) This field is used to choose Output Driver Strength. Three types of Driver Strength are supported. QS and DQ Driver Strength can be chosen separately. A2-A1 specified the DQ Driver Strength. A4-A3 specified the QS Driver Strength. QS DQ A4 A3 A2 A1 OUTPUT DRIVER IMPEDANCE CONTROL 0 0 0 0 Normal Output Driver 0 1 0 1 Strong Output Driver 1 0 1 0 Weak Output Driver 1 1 1 1 Reserved (E-3) Strobe Select (A6 / A5) Two types of data strobe are supported. This field is used to choose the type of data strobe. (1) Unidirectional DS/QS mode Data strobe is separated DS for write strobe and QS for read strobe. DS is used to sample write data at write operation. QS is aligned with read data at Read operation. (2) Unidirectional DS/Free running QS mode Data strobe is separated DS for write strobe and QS for read strobe. D S i s u s e d t o s a m p l e w r i t e d a t a a t w r i t e o p e r a t i o n . Q S i s a l i g n e d w i t h r e a d d a t a a n d a l w a y s clocking. A6 A5 STROBE SELECT 0 0 Reserved 0 1 Reserved 1 0 Unidirectional DS/QS mode 1 1 Unidirectional DS/Free running QS mode (E-4) Reserved field (A7 to A14) These bits are reserved for future operations and must be set to “0” for normal operation.

TC59LM818DMB-33,-40 2005-10-19 55/57 Rev 1.4 PACKAGE DIMENSIONS P-BGA60-0917-1.00AZ 0.2SB 0.2SA

0.08 SAB

12.518 0 -0.15 16.5 6.2180 -0.15 9.0 0.15 0.1 S 0.2 S 0.15MIN 1.2MAX 0.40.05 1.51.5 1234 56 INDEX R P N M L K J H G F E D C B A 1.0 1.25 2.02.0 1.0 1 B A S 0.5 0.05 Weight: 0.15 g (typ.)

TC59LM818DMB-33,-40 2005-10-19 56/57 Rev 1.4

REVISION HISTORY

1 st edition released.

• Some notes in the page 7 moved to page 6 ( page 6, 7 ).
• Note 2 changed as below ( page 6 ). Before: These parameters depend on the output loading. The specified values are obtained with the output open After: These parameters define the current between V DD and VSS.
• Corrected TYPO ( page 8, 13~15, 51 ).
• t CK,MAX for “-30” changed from 7.5 ns to 5.0 ns ( page 8 )
• VSWING in AC test conditions changed from 0.7 V to 0.8 V ( page 10 )
• Revision History added ( page 56 ). − Rev.1.2 (Mar. 7 ’2005) Corrected figure of lPDA based AC timing spec table ( page 11, 40, 41, 47, 48 ). − Rev.1.3 (Sep.26 ’2005) IDD6( Self-Refresh current ) spec changed from 10mA to 15mA( page 1 and 6 ). − Rev.1.4 (Oct.19 ’2005) “-30”( 333MHz clock/666Mbps ) version dropped.

TC59LM818DMB-33,-40 2005-10-19 57/57 Rev 1.4

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