TC59LM806CFT-50

TC59LM814CFT TOSHIBA | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 38

Technical content

TC59LM814/06CFT-50,-55,-60 2002-08-19 1/38 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 4,194,304-WORDS × 4 BANKS × 16-BITS Network FCRAMTM 8,388,608-WORDS × 4 BANKS × 8-BITS Network FCRAMTM

DESCRIPTION

Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM814/06CFT are Network FCRAMTM containing 268,435,456 memory cells. TC59LM814CFT is organized as 4,194,304-words × 4 banks s× 16 bits, TC59LM806CFT is organized as 8,388,608 words × 4 banks × 8 bits. TC59LM814/06CFT feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. TC59LM814/06CFT can operate fast core cycle using the FCRAM TM core architecture compared with regular DDR SDRAM. TC59LM814/06CFT is suitable for Network, Server and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAM TM is capable of high quality fast data transfer under light loading condition.

FEATURES

-50 -55 -60 CL = 3 5.5 ns 6 ns 6.5 ns tCK Clock Cycle Time (min) CL = 4 5 ns 5.5 ns 6 ns tRC Random Read/Write Cycle Time (min) 25 ns 27.5 ns 30 ns tRAC Random Access Time (max) 22 ns 24 ns 26 ns IDD1S Operating Current (single bank) (max) 190 mA 180 mA 170 mA lDD2P Power Down Current (max) 2 mA 2 mA 2 mA lDD6 Self-Refresh Current (max) 3 mA 3 mA 3 mA

• Fully Synchronous Operation
• Double Data Rate (DDR) Data input/output are synchronized with both edges of DQS.
• Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
• Fast clock cycle time of 5 ns minimum Clock: 200 MHz maximum Data: 400 Mbps/pin maximum
• Quad Independent Banks operation
• Fast cycle and Short Latency
• Bidirectional Data Strobe Signal
• Distributed Auto-Refresh cycle in 7.8 µs
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length CAS Latency = 3, 4 Burst Length = 2, 4
• Organization TC59LM814CFT: 4,194,304 words × 4 banks × 16 bits TC59LM806CFT: 8,388,608 words × 4 banks × 8 bits
• Power Supply Voltage VDD: 2.5 V ± 0.15 V V DDQ: 2.5 V ± 0.15 V
• 2.5 V CMOS I/O comply with SSTL-2 (half strength driver)
• Package: 400 × 875 mil, 66 pin TSOPII, 0.65 mm pin pitch (TSOPII66-P-400-0.65) Notice: FCRAM is a trademark of Fujitsu Limited, Japan.

TC59LM814/06CFT-50,-55,-60 2002-08-19 2/38 PIN NAMES PIN ASSIGNMENT (TOP VIEW) PIN NAME A0~A14 Address Input BA0, BA1 Bank Address DQ0~DQ7 (×8) DQ0~DQ15 (×16) Data Input/Output CS Chip Select FN Function Control PD Power Down Control CLK, CLK Clock Input DQS (×8) UDQS/LDQS (×16) Write/Read Data Strobe VDD Power ( +2.5 V) VSS Ground VDDQ Power (+2.5 V) (for I/O buffer) VSSQ Ground (for I/O buffer) VREF Reference Voltage NC1, NC2 Not Connected TC59LM814CFT TC59LM806CFT 400 mil width 875 mil length 66 pin TSOPII 0.65 mm Lead pitch 1 66 2 65 3 64 4 63 5 62 6 61 7 60 8 59 9 58 10 57 11 56 12 55 13 54 14 53 15 52 16 51 17 50 18 49 19 48 20 47 21 46 22 45 23 44 24 43 25 42 26 41 27 40 28 39 29 38 30 37 31 36 32 35 33 34 PD PD CLK CLK VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 V DDQ DQ8 NC1 VSSQ UDQS NC1 VREF VSS NC1 CLK NC A12 A11 V SS VSS DQ7 VSSQ NC2 DQ6 VDDQ NC2 DQ5 VSSQ NC2 DQ4 VDDQ NC2 NC1 VSSQ DQS NC1 VREF VSS NC1 CLK NC A12 A11 V SS CS CS VDD DQ0 V DDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC1 VDDQ LDQS NC1 VDD NC1 NC1 A14 A13 FN NC1 BA0 BA1 A10 V DD VDD DQ0 VDDQ NC2 DQ1 VSSQ NC2 DQ2 VDDQ NC2 DQ3 VSSQ NC2 NC1 VDDQ NC2 NC1 VDD NC1 NC1 A14 A13 FN NC BA0 BA1 A10 V DD

TC59LM814/06CFT-50,-55,-60 2002-08-19 3/38 BLOCK DIAGRAM Note: The TC59LM806CFT configuration is 32768 × 256 × 8 of cell array with the DQ pins numbered DQ0~DQ7. The TC59LM814CFT configuration is 32768 × 128 × 16 of cell array with the DQ pins numbered DQ0~DQ15. DQ0~DQn BANK #1 DLL CLOCK BUFFER CLK CLK PD To each block COMMAND DECODER CS FN ADDRESS BUFFER CONTROL SIGNAL GENERATOR MODE REGISTER REFRESH COUNTER A0~A14 BA0, BA1 BANK #0 MEMORY CELL ARRAY COLUMN DECODER ROW DECODER BURST COUNTER WRITE ADDRESS LATCH/ ADDRESS COMPARATOR DATA CONTROL and LATCH CIRCUIT UPPER ADDRESS LATCH READ DATA BUFFER DQ BUFFER DQS LOWER ADDRESS LATCH BANK #2 BANK #3 WRITE DATA BUFFER

TC59LM814/06CFT-50,-55,-60 2002-08-19 4/38 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT NOTES VDD Power Supply Voltage −0.3~ 3.3 V VDDQ Power Supply Voltage (for I/O buffer) −0.3~VDD+ 0.3 V VIN Input Voltage −0.3~VDD+ 0.3 V VOUT DQ pin Voltage −0.3~VDDQ + 0.3 V VREF Input Reference Voltage −0.3~3.3 V Topr Operating Temperature 0~70 °C Tstg Storage Temperature −55~150 °C Tsolder Soldering Temperature (10 s) 260 °C PD Power Dissipation 1 W IOUT Short Circuit Output Current ±50 mA Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability. RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1)(Ta ==== 0°~70°C) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES VDD Power Supply Voltage 2.35 2.5 2.65 V VDDQ Power Supply Voltage (for I/O buffer) 2.35 V DD V DD V VREF Input Reference Voltage V DDQ/2 × 96% V DDQ/2 V DDQ/2 × 104% V 2 VIH (DC) Input DC High Voltage V REF + 0.2  V DDQ + 0.2 V 5 VIL (DC) Input DC Low Voltage −0.1  V REF − 0.2 V 5 VICK (DC) Differential Clock DC Input Voltage −0.1  V DDQ + 0.1 V 10 VID (DC) Input Differential Voltage. CLK and CLK inputs (DC) 0.4  V DDQ + 0.2 V 7, 10 VIH (AC) Input AC High Voltage V REF + 0.35  V DDQ + 0.2 V 3, 6 VIL (AC) Input AC Low Voltage −0.1  V REF − 0.35 V 4, 6 VID (AC) Input Differential Voltage. CLK and CLK inputs (AC) 0.7  V DDQ + 0.2 V 7, 10 VX (AC) Differential AC Input Cross Point Voltage V DDQ/2 − 0.2  V DDQ/2 + 0.2 V 8, 10 VISO (AC) Differential Clock AC Middle Level V DDQ/2 − 0.2  V DDQ/2 + 0.2 V 9, 10

TC59LM814/06CFT-50,-55,-60 2002-08-19 5/38 Note: (1) All voltages referenced to V SS, VSSQ. (2) V REF is expected to track variations in VDDQ DC level of the transmitting device. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC). (3) Overshoot limit: V IH (max) = VDDQ + 0.9 V with a pulse width ≤ 5 ns. (4) Undershoot limit: V IL (min) = −0.9 V with a pulse width ≤ 5 ns. (5) V IH (DC) and VIL (DC) are levels to maintain the current logic state. (6) V IH (AC) and VIL (AC) are levels to change to the new logic state. (7) V ID is magnitude of the difference between CLK input level and CLK input level. (8) The value of V X (AC) is expected to equal VDDQ/2 of the transmitting device. (9) V ISO means {VICK (CLK) + VICK ( CLK )} /2 (10) Refer to the figure below. (11) In the case of external termination, VTT (termination voltage) should be gone in the range of V REF (DC) ± 0.04 V. CAPACITANCE (VDD, , , , VDDQ ==== 2.5 V, f ==== 1 MHz, Ta ==== 25°C) SYMBOL PARAMETER MIN MAX UNIT CIN Input pin Capacitance 2.5 4.0 pF CINC Clock pin (CLK, CLK ) Capacitance 2.5 4.0 pF CI/O I/O pin (DQ, DQS) Capacitance 4.0 6.0 pF CNC 1 NC 1 pin Capacitance  1.5 pF CNC 2 NC 2 pin Capacitance 4.0 6.0 pF Note: These parameters are periodically sampled and not 100% tested. The NC2 pins have additional capacitance for adjustment of the adjacent pin capacitance. The NC2 pins have Power and Ground clamp. VISO (min) VISO (max) VICK VICK Vx Vx Vx Vx Vx VICK VICK CLK CLK VSS |VID (AC)|

0 V Differential

VID (AC)

TC59LM814/06CFT-50,-55,-60 2002-08-19 6/38 RECOMMENDED DC OPERATING CONDITIONS (VDD,,,,VDDQ====2.5V ±±±± 0.15V, Ta ==== 0°~70°C) MAX SYMBOL PARAMETER -50 -55 -60 UNIT NOTES IDD1S Operating Current tCK = min; IRC = min, Read/Write command cycling,

0 V ≤ V

IN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ, 1 bank operation, Burst length = 4, Address change up to 2 times during minimum IRC. 190 180 170 1, 2 IDD2N Standby Current tCK = min, CS = VIH, PD = VIH,

0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ,

All banks: inactive state, Other input signals are changed one time during 4 × tCK. 40 40 35 1 IDD2P Standby (power down) Current tCK = min, CS = VIH, PD = VIL (power down),

0 V ≤ VIN ≤ VDDQ,

All banks: inactive state 2 2 2 1 IDD5 Auto-Refresh Current tCK = min; IREFC = min, tREFI = min, Auto-Refresh command cycling, IN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ, Address change up to 2 times during minimum IREFC. 65 65 60 1 IDD6 Self-Refresh Current Self-Refresh mode PD = 0.2 V, 0 V ≤ VIN ≤ VDDQ 3 3 3 mA SYMBOL PARAMETER MIN MAX UNIT NOTES ILI Input Leakage Current ( 0 V ≤ VIN ≤ VDDQ, all other pins not under test = 0 V) −5 5 µA ILO Output Leakage Current (Output disabled, 0 V ≤ VOUT ≤ VDDQ) −5 5 µA IREF VREF Current −5 5 µA IOH (DC) Output Source DC Current VOH = VDDQ − 0.4 V −10  3 IOL (DC) Normal Output Driver Output Sink DC Current VOL = 0.4 V 10  3 IOH (DC) Output Source DC Current VOH = VDDQ − 0.4 V −11  3 IOL (DC) Strong Output Driver Output Sink DC Current VOL = 0.4 V 11  3 IOH (DC) Output Source DC Current VOH = VDDQ − 0.4 V −8  3 IOL (DC) Weaker Output Driver Output Sink DC Current VOL = 0.4 V 8  3 IOH (DC) Output Source DC Current VOH = VDDQ − 0.4 V −7  3 IOL (DC) Weakest Output Driver Output Sink DC Current VOL = 0.4 V 7  mA Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK, tRC and IRC. 2. These parameters depend on the output loading. The specified values are obtained with the output open. 3. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.

TC59LM814/06CFT-50,-55,-60 2002-08-19 7/38 AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) -50 -55 -60 SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX UNIT NOTES tRC Random Cycle Time 25  27.5  30  3 CL = 3 5.5 8.5 6 12 6.5 12 3 tCK Clock Cycle Time CL = 4 5 8.5 5.5 12 6 12 3 tRAC Random Access Time  22  24  26 3 tCH Clock High Time 0.45 × tCK  0.45 × tCK  0.45 × tCK  3 tCL Clock Low Time 0.45 × tCK  0.45 × tCK  0.45 × tCK  3 tQSQ Data Output Skew from DQS  0.4  0.45  0.5 4 tQSPRE DQS (read) Preamble Pulse Width 0.9 × tCK − 0.2 1.1 × tCK + 0.2 0.9 × tCK − 0.2 1.1 × tCK + 0.2 0.9 × tCK − 0.2 1.1 × tCK + 0.2 3, 8 tHP CLK half period (minimum of Actual tCH, t CL) min(tCH, tCL)  min(tCH, tCL)  min(tCH, tCL)  3 tQSP DQS (read) Pulse Width tHP− 0.55  t HP− 0.6  tHP− 0.65  4, 8 tQSQV Data Output Valid Time from DQS tHP− 0.55  t HP− 0.6  tHP− 0.65  4, 8 tDQSS DQS (write) Low to High Setup tDSPRE DQS (write) Preamble Pulse Width 0.4 × tCK  0.4 × tCK  0.4 × tCK  4 tDSPRES DQS First Input Setup Time 0  0  0  3 tDSPREH DQS First Low Input Hold Time 0.25 × tCK  0.25 × tCK  0.25 × tCK  3 tDSS DQS Input Falling Edge to Clock Setup Time CL = 4 1.3  1.4  1.5  3, 4 tDSPST DQS (write) Postamble Pulse Width 0.45 × tCK  0.45 × tCK  0.45 × tCK  4 tDSPSTH DQS (write) Postamble Hold Time CL = 4 1.3  1.4  1.5  3, 4 tDS Data Input Setup Time from DQS 0.5  0.5  0.6  4 tDH Data Input Hold Time from DQS 0.5  0.5  0.6  4 tDIPW Data Input Pulse Width (for each device) 1.5  1.5  1.9  tIS Command/Address Input Setup Time 0.9  0.9  1.0  3 tIH Command/Address Input Hold Time 0.9  0.9  1.0  3 tIPW Command/Address Input Pulse Width (for each device) 2.0  2.0  2.2  tLZ Data-out Low Impedance Time tHZ Data-out High Impedance Time from CLK  0.65  0.75  0.85 ns 3,7,8

TC59LM814/06CFT-50,-55,-60 2002-08-19 8/38 AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued) -50 -55 -60 SYMBOL PARAMETER MIN MAX MIN MAX MIN MAX UNIT NOTES tQSLZ DQS-out Low Impedance Time tQSHZ DQS-out High Impedance Time tQPDH Last output to PD High Hold Time 0  0  0  tPDEX Power Down Exit Time 2  2  2  3 tT Input Transition Time 0.1 1 0.1 1 0.1 1 tFPDL PD Low Input Window for Self-Refresh Entry −0.5 × tCK 5 −0.5 × tCK 5 −0.5 × tCK 5 ns tPAUSE Pause Time after Power-up 200  200  200  µs CL = 3 5  5  5  IRC Random Read/Write Cycle Time (applicable to same bank) C L = 4 5  5  5  IRCD RDA/WRA to LAL Command Input Delay (applicable to same bank) 1 1 1 1 1 1 CL = 3 4  4  4  IRAS LAL to RDA/WRA Command Input Delay (applicable to same bank) CL = 4 4  4  4  IRBD Random Bank Access Delay (applicable to other bank) 2  2  2  BL = 2 2  2  2  IRWD LAL following RDA to WRA Delay (applicable to other bank) BL = 4 3  3  3  IWRD LAL following WRA to RDA Delay (applicable to other bank) 1  1  1  CL = 3 5  5  5  IRSC Mode Register Set Cycle Time CL = 4 5  5  5  IPD PD Low to Inactive State of Input Buffer  1  1  1 IPDA PD High to Active State of Input Buffer  1  1  1 CL = 3 15  15  15  IPDV Power down mode valid from REF command CL = 4 18  18  18  CL = 3 15  15  15  IREFC Auto-Refresh Cycle Time CL = 4 18  18  18  ICKD REF Command to Clock Input Disable at Self-Refresh Entry 16  16  16  ILOCK DLL Lock-on Time (applicable to RDA command) 200  200  200  cycle

TC59LM814/06CFT-50,-55,-60 2002-08-19 9/38 AC TEST CONDITIONS SYMBOL PARAMETER VALUE UNIT NOTES VIH (min) Input High Voltage (minimum) V REF + 0.35 V VIL (max) Input Low Voltage (maximum) V REF − 0.35 V VREF Input Reference Voltage V DDQ/2 V VTT Termination Voltage V REF V VSWING Input Signal Peak to Peak Swing 1.0 V Vr Differential Clock Input Reference Level V X (AC) V VID (AC) Input Differential Voltage 1.5 V SLEW Input Signal Minimum Slew Rate 1.0 V/ns VOTR Output Timing Measurement Reference Voltage V DDQ/2 V Note: (1) Transition times are measured between V IH min (DC) and VIL max (DC). Transition (rise and fall) of input signals have a fixed slope. (2) If the result of nominal calculation with regard to t CK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., t (3) There parameters are measured from the differential clock (CLK and CLK ) AC cross point. (4) These parameters are measured from signal transition point of DQS crossing V REF level. (5) Te t REFI (max) applies to equally distributed refresh method. The tREFI (min) applies to both burst refresh method and distribted refresh method. In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 µs (8 × 400 ns) is to 8 times in the maximum. (6) Low Impedance State is specified at V DDQ/2 ± 0.2 V from steady state. (7) High Impedance State is specified where output buffer is no longer driven. (8) These parameters depend on the clock jitter. These parameters are measured at stable clock. Z = 50 Ω AC Test Load Output VTT CL = 30 pF RT = 50 Ω Measurement point SLEW = (VIH min (AC) − VIL max (AC))/∆T Output VIH min (AC) VREF VIL max (AC) VSWING VSS VDDQ VREF

TC59LM814/06CFT-50,-55,-60 2002-08-19 10/38 POWER UP SEQUENCE (1) As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection. (2) Apply V DD before or at the same time as VDDQ. (3) Apply V DDQ before or at the same time as VREF. (4) Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min). (5) After stable power and clock, apply DESL and take PD =H. (6) Issue EMRS to enable DLL and to define driver strength. (Note: 1) (7) Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1) (8) Issue two or more Auto-Refresh commands (Note: 1). (9) Ready for normal operation after 200 clocks from Extended Mode Register programming. Note: (1) Sequence 6, 7 and 8 can be issued in random order. (2) L = Logic Low, H = Logic High CLK Command DQ Address VDD VDDQ VREF CLK PD 2.5V(TYP) 2.5V(TYP) 1.25V(TYP) 200 us(min) tPDEX lPDA lRSC lRSC lREFC lREFC 200clock cycle(min) DESL RDA DESL RDA MRS DESL WRA REF DESL WRA REF DESL op-code EMRS op-code MRS Hi-Z DQS EMRS MRS Auto Refresh cycle Normal Operation MRS

TC59LM814/06CFT-50,-55,-60 2002-08-19 11/38 TIMING DIAGRAMS Input Timing Timing of the CLK, tCK tCL tCH CS DQ (input) CLK CLK Refer to the Command Truth Table. tCK 1st 2nd tIS tIH tIS tIH tIPW 1st 2nd tIS tIH tIS tIH tIPW UA, BA LA tIS tIH tIS tIH tIPW FN A0~A14 BA0, BA1 tDS tDH tDS tDH tDIPW tDIPW DQS tT tCK CLK VIH VIL VIH VIL tCL tCH tT VIH (AC) VIL (AC) CLK CLK CLK VX VX VX VID (AC) CLK

TC59LM814/06CFT-50,-55,-60 2002-08-19 12/38 Read Timing (Burst Length = 4) LDQS DQ0~DQ7 UDQS DQ8~DQ15 CLK CLK Input (control & a ddresses) Hi-Z DQS (output) DQ (output) CAS latency = 3 LAL (after RDA) tIS t IH tIPW Hi-Z tCH tCL tCK Hi-Z DQS (output) DQ (output) CAS latency = 4 Hi-Z Note: The correspondence of LDQS, UDQS to DQ. (TC59LM814CFT) tQSQ tQSLZ tQSPRE tCKQS tCKQS tQSP t QSP tCKQS tQSHZ tQSQ tQSQV tQSQV t QSQ t HZ tLZ tOH tAC tAC tAC Preamble Postamble tQSLZ tQSPRE tCKQS tCKQS tQSP t QSP tCKQS tQSHZ Preamble Postamble Hi-Z Hi-Z tQSQtQSQ tQSQV tQSQV t QSQ t HZ tLZ tOH tAC tAC tAC (DESL)

TC59LM814/06CFT-50,-55,-60 2002-08-19 13/38 Write Timing (Burst Length = 4) LDQS DQ0~DQ7 UDQS DQ8~DQ15 tREFI, tPAUSE, IXXXX Timing CLK CLK Input (control & addresses) DQS (input) DQ (input) CAS latency = 3 LAL (after WRA) tIS t IH tIPW tCH tCL tCK Note: the correspondence of LDQS, UDQS to DQ. (TC59LM814CFT) DQS (input) DQ (input) CAS latency = 4 tDSPREH tDSP t DSP tDS Preamble Postamble tDSP tDSS tDSPRES tDSPST tDSS tDSPSTH tDSPRE tDQSS tDH tDIPW tDS tDH tDS tDH tDSPREH tDSP t DSP tDS Preamble Postamble tDSP tDQSS tDSPRES tDSPST tDSS tDSPSTH tDSPRE tDQSS tDH tDIPW tDS tDH tDS tDH tDSS tDQSS (DESL) CLK CLK Input (control & addresses) Command tIS t IH Note: “IXXXX” means “IRC”, “IRCD”, “IRAS”, etc. tREFI, tPAUSE, IXXXX Command tIS t IH (DESL)

TC59LM814/06CFT-50,-55,-60 2002-08-19 14/38 Write Timing (x16 device) (Burst Length = 4) Preamble CLK CLK Input (control & addresses) LDQS DQ0~DQ7 CAS latency = 3 UDQS DQ8~DQ15 LAL WRA LDQS DQ0~DQ7 CAS latency = 4 UDQS DQ8~DQ15 tDS Postamble tDSSK tDH D0 D1 tDS tDH D2 D3 tDS tDH tDS Preamble Postamble tDH tDS tDH tDS tDH tDS tDH tDSSK tDSSK t DSSK tDH tDS tDS Preamble tDSSK tDH D0 D1 tDS tDH D2 D3 tDS tDH tDS Preamble tDH tDS tDH tDS tDH tDS tDH tDSSK tDSSK t DSSK tDH tDS (DESL)

TC59LM814/06CFT-50,-55,-60 2002-08-19 15/38 FUNCTION TRUTH TABLE (Notes: 1, 2, 3) Command Truth Table (Notes: 4)

• The First Command SYMBOL FUNCTION CS FN BA1~BA0 A14~A9 A8 A7 A6~A0 DESL Device Deselect H × × × × × × RDA Read with Auto-close L H BA UA UA UA UA WRA Write with Auto-close L L BA UA UA UA UA
• The Second Command (The next clock of RDA or WRA command) SYMBOL FUNCTION CS FN BA1~ BA0 A14~ A13 A12~ A11 A10~A9 A8 A7 A6~A0 LAL Lower Address Latch ( ×16) H × × V V × × × LA LAL Lower Address Latch ( ×8) H × × V × × × LA LA MRS Mode Register Set L × V L L L L V V Notes: 1. L = Logic Low, H = Logic High, × = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address, LA = Lower Address 2. All commands are assumed to issue at a valid state. 3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where CLK goes to High. 4. Operation mode is decided by the combination of 1st command and 2nd command. Refer to “STATE DIAGRAM” and the command table below. Read Command Table COMMAND (SYMBOL) CS FN BA1~BA0 A14~A9 A8 A7 A6~A0 NOTES RDA (1st) L H BA UA UA UA UA LAL (2nd) H × × × × LA LA 5 Notes: 5. For x16 device, A7 is " ×" (either L or H). Write Command Table
• TC59LM814CFT COMMAND(SYMBOL) CS FN BA1~ BA0 A14 A13 A12 A11 A10~ A9 A8 A7 A6~A0 WRA (1st) L L BA UA UA UA UA UA UA UA UA LAL (2nd) H × × LVW0 LVW1 UVW0 UVW1 × × × LA
• TC59LM806CFT COMMAND(SYMBOL) CS FN BA1~ BA0 A14 A13 A12 A11 A10~ A9 A8 A7 A6~A0 WRA (1st) L L BA UA UA UA UA UA UA UA UA LAL (2nd) H × × VW0 VW1 × × × × LA LA Notes: 6. A14~ A11 are used for Variable Write Length (VW) control at Write Operation.

TC59LM814/06CFT-50,-55,-60 2002-08-19 16/38 FUNCTION TRUTH TABLE (continued) VW Truth Table SYMBOL Function VW0 VW1 Write All Words L × BL=2 Write First One Word H × Reserved L L Write All Words H L Write First Two Words L H BL=4 Write First One Word H H Notes: 7. For x16 device, LVW0 and LVW1 control DQ0~DQ7. UVW0 and UVW1 control DQ8~DQ15. Mode Register Set Command Table COMMAND (SYMBOL) CS FN BA1~BA0 A14~A9 A8 A7 A6~A0 NOTES MRS (2nd) L × V L L V V 8 Notes: 8. Refer to “MODE REGISTER TABLE”. Auto-Refresh Command Table PD FUNCTION COMMAND (SYMBOL) CURRENT STATE n − 1 n CS FN BA1~BA0 A14~A9 A8 A7 A6~A0 NOTES Active WRA (1st) Standby H H L L × × × × × Auto-Refresh REF (2nd) Active H H L × × × × × × Self-Refresh Command Table PD FUNCTION COMMAND (SYMBOL) CURRENT STATE n − 1 n CS FN BA1~BA0 A14~A9 A8 A7 A6~A0 NOTES Active WRA (1st) Standby H H L L × × × × × Self-Refresh Entry REF (2nd) Active H L L × × × × × × 9, 10 Self-Refresh Continue  Self-Refresh L L × × × × × × × Self-Refresh Exit SELFX Self-Refresh L H H × × × × × × 11 Power Down Table PD FUNCTION COMMAND (SYMBOL) CURRENT STATE n − 1 n CS FN BA1~BA0 A14~A9 A8 A7 A6~A0 NOTES Power Down Entry PDEN Standby H L H × × × × × × 10 Power Down Continue  Power Down L L × × × × × × × Power Down Exit PDEX Power Down L H H × × × × × × 11 Notes: 9. PD has to be brought to Low within t FPDL from REF command. 10. PD should be brought to Low after DQ’s state turned high impedance. 11. When PD is brought to High from Low, this function is executed asynchronously.

TC59LM814/06CFT-50,-55,-60 2002-08-19 17/38 FUNCTION TRUTH TABLE (continued) PD CURRENT STATE n − 1 n CS FN ADDRESS COMMAND ACTION NOTES H H H × × DESL NOP H H L H BA, UA RDA Row activate for Read H H L L BA, UA WRA Row activate for Write H L H × × PDEN Power Down Entry 12 H L L × ×  Illegal Idle L × × × ×  Refer to Power Down State H H H × LA LAL Begin Read H H L × Op-code MRS/EMRS Access to Mode Register H L H × × PDEN Illegal H L L × × MRS/EMRS Illegal Row Active for Read H H H × LA LAL Begin Write H H L × × REF Auto-Refresh H L H × × PDEN Illegal H L L × × REF (self) Self-Refresh Entry Row Active for Write H H H × × DESL Continue Burst Read to End H H L H BA, UA RDA Illegal 13 H H L L BA, UA WRA Illegal 13 H L H × × PDEN Illegal H L L × ×  Illegal Read H H H × × DESL Data Write&Continue Burst Write to End H H L H BA, UA RDA Illegal 13 H H L L BA, UA WRA Illegal 13 H L H × × PDEN Illegal H L L × ×  Illegal Write H H H × × DESL NOP → Idle after IREFC H H L H BA, UA RDA Illegal H H L L BA, UA WRA Illegal H L H × × PDEN Self-Refresh Entry 14 H L L × ×  Illegal Auto-Refreshing L × × × ×  Refer to Self-Refreshing State H H H × × DESL NOP → Idle after IRSC H H L H BA, UA RDA Illegal H H L L BA, UA WRA Illegal H L H × × PDEN Illegal H L L × ×  Illegal Mode Register Accessing L L × × ×  Maintain Power Down Mode L H H × × PDEX Exit Power Down Mode → Idle after tPDEX Power Down L H L × ×  Illegal L L × × ×  Maintain Self-Refresh L H H × × SELFX Exit Self-Refresh → Idle after IREFC L H L × ×  Illegal Self-Refreshing Notes: 12. Illegal if any bank is not idle. 13. Illegal to bank in specified states; Function may be legal in the bank inidicated by Bank Address (BA). 14. Illegal if tFPDL is not satisfied.

TC59LM814/06CFT-50,-55,-60 2002-08-19 18/38 MODE REGISTER TABLE Regular Mode Register (Notes: 1) ADDRESS BA1 *1 BA0 *1 A14~A8 A7 *3 A6~A4 A3 A2~A0 Register 0 0 0 TE CL BT BL A7 TEST MODE (TE) A3 BURST TYPE (BT)

0 Regular (default) 0 Sequential

1 Test Mode Entry 1 Interleave

A6 A5 A4 CAS LATENCY (CL) A2 A1 A0 BURST LENGTH (BL) 0 0 × Reserved*2 0 0 0 Reserved *2 0 1 0 Reserved *2 0 0 1 2 0 1 1 3 0 1 0 4 1 0 0 4 0 1 1 1 0 1 Reserved *2 1 × × Reserved*2 1 1 × Reserved *2 Extended Mode Register (Notes: 4) ADDRESS BA1 *4 BA0 *4 A14~A7 A6 A5~A2 A1 A0 *5 Register 0 1 0 DIC 0 DIC DS A6 A1 OUTPUT DRIVE IMPEDANCE CONTROL (DIC) 0 0 Normal Output Driver 0 1 Strong Output Driver 1 0 Weaker Output Driver 1 1 Weakest Output Driver A0 DLL SWITCH (DS)

0 DLL Enable

1 DLL Disable

Notes: 1. Regular Mode Register is chosen using the combination of BA0 = 0 and BA1 = 0. 2. “Reserved” places in Regular Mode Register should not be set. 3. A7 in Regular Mode Register must be set to “0” (low state). Because Test Mode is specific mode for supplier. 4. Extended Mode Register is chosen using the combination of BA0 = 1 and BA1 = 0. 5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.

TC59LM814/06CFT-50,-55,-60 2002-08-19 19/38 STATE DIAGRAM STANDBY (IDLE) SELF- REFRESH POWER DOWN PDEN ( PD = L) PDEX ( PD = H) SELFX ( PD = H) MODE REGISTER AUTO- REFRESH ACTIVE ACTIVE (RESTORE) READ WRITE (BUFFER) PD = L PD = H WRA RDA MRS REF Command input LAL Automatic return The second command at Active state must be issued 1 clock after RDA or WRA command input. LAL

TC59LM814/06CFT-50,-55,-60 2002-08-19 20/38 TIMING DIAGRAMS SINGLE BANK READ TIMING (CL = 3) SINGLE BANK READ TIMING (CL = 4) CLK CLK Hi-ZDQS (output) DQ (output) BL = 2 IRC = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 RDA LAL RDA LAL RDA Hi-Z Hi-Z Q0 Hi-Z Q1 Q0 Q1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Q0 Hi-Z Q1 Q0 Q1 Hi-Z Hi-ZQ2 Q3 Q2 Q3 CL = 3 Command DQS (output) DQ (output) BL = 4 DESL DESL IRC = 5 cycles LAL IRAS = 4 cycles IRCD=1 cycle I RAS = 4 cycles IRCD=1 cycle CL = 3 CL = 3 CL = 3 CLK CLK Hi-ZDQS (output) DQ (output) BL = 2 IRC = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 RDA LAL RDA LAL RDA Hi-Z Q0 Hi-Z Q1 Q0 Q1 Hi-Z Hi-Z Hi-Z Q0 Hi-Z Q1 Q0 Q1 Hi-ZQ2 Q3 Q1 CL = 4 Command DQS (output) DQ (output) BL = 4 DESL DESL IRC = 5 cycles LAL IRAS = 4 cycles IRCD = 1 cycle I RAS = 4 cycles IRCD = 1 cycle CL = 4 CL = 4 CL = 4 IRCD = 1 cycle

TC59LM814/06CFT-50,-55,-60 2002-08-19 21/38 SINGLE BANK WRITE TIMING (CL = 3) SINGLE BANK WRITE TIMING (CL = 4) CLK CLK DQS (input) DQ (input) BL = 2 0 1 2 3 4 5 6 7 8 9 10 11 WRA LAL D0 D1 WL = 2 Command DQS (input) DQ (input) BL = 4 IRC = 5 cycles D0 D1 tDQSS D0 D1 tDQSS D2 D3 DESL WRA LAL DESL WRA LAL IRC = 5 cycles IRAS = 4 cycles IRCD = 1 cycle I RAS = 4 cycles IRCD = 1 cycle WL = 2 WL = 2 D0 D1 D2 D3 WL = 2 tDQSS CLK CLK DQS (input) DQ (input) BL = 2 0 1 2 3 4 5 6 7 8 9 10 11 WRA LAL D0 D1 WL = 3 Command DQS (input) DQ (input) BL = 4 IRC = 5 cycles D0 D1 D0 D1 tDQSS D2 D3 DESL WRA LAL DESL WRA LAL IRC = 5 cycles IRAS = 4 cycles IRCD = 1 cycle I RAS = 4 cycles IRCD = 1 cycle WL = 3 D0 D1 D2 D3 tDQSS WL = 3 WL = 3 IRCD = 1 cycle Note: means H or L

TC59LM814/06CFT-50,-55,-60 2002-08-19 22/38 SINGLE BANK READ-WRITE TIMING (CL = 3) SINGLE BANK READ-WRITE TIMING (CL = 4) CLK CLK DQS DQ BL = 2 0 1 2 3 4 5 6 7 8 9 10 11 RDA LAL Command BL = 4 WRA LAL DQS DQ DESL DESL RDA LAL IRC = 5 cycles IRC = 5 cycles Hi-Z Hi-Z Hi-Z Q0 Hi-Z Q1 D0 D1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Q0 Hi-Z Q1 D0 D1 Hi-Z Hi-ZQ2 Q3 D2 D3 CL = 3 IRAS = 4 cycles IRCD = 1 cycle I RAS = 4 cycles IRCD = 1 cycle CL = 3 WL = 2 WL = 2 tDQSS CLK CLK DQS DQ BL = 2 0 1 2 3 4 5 6 7 8 9 10 11 RDA LAL Command BL = 4 WRA LAL DQS DQ DESL DESL RDA LAL IRC = 5 cycles IRC = 5 cycles Hi-Z Hi-Z Q0 Hi-Z Q1 D0 D1 Hi-Z Hi-Z Hi-Z Q0 Hi-Z Q1 D0 D1 Hi-ZQ2 Q3 D2 D3 CL = 4 IRAS = 4 cycles IRCD = 1 cycle I RAS = 4 cycles IRCD = 1 cycle WL = 3 tDQSS CL = 4 WL = 3

TC59LM814/06CFT-50,-55,-60 2002-08-19 23/38 MULTIPLE BANK READ TIMING (CL = 3) MULTIPLE BANK READ TIMING (CL = 4) CLK CLK BL = 2 0 1 2 3 4 5 6 7 8 9 10 11 RDAa LALa Command IRC = 5 cycles Hi-Z Qa0Hi-Z Hi-Z Hi-Z CL = 3 RDAb LALb DESL LALa RDAc LALc RDAd LALd RDAb Bank “a” × Bank Add. (BA0, BA1) Bank “b” Bank “c” × Bank “d” × IRCD = 1 cycle I RAS = 4 cycles I RCD = 1 cycle IRBD = 2 cycles Qa1 Qb0Qb1 Qa0Qa1 Qc0Hi-Z Hi-Z Hi-Z DQS (output) DQ (output) Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qc0 BL = 4 DQS (output) DQ (output) RDAa IRCD = 1 cycle IRCD = 1 cycle IRBD = 2 cycles IRBD = 2 cycles Hi-Z CL = 3 CL = 3 CL = 3 Hi-Z Qa0Qa1Qa2Qa3 CL = 3 CL = 3 IRBD = 2 cycles CLK CLK BL = 2 0 1 2 3 4 5 6 7 8 9 10 11 RDAa LALa Command IRC = 5 cycles Hi-Z Qa0Hi-Z Hi-Z Hi-Z CL = 4 RDAb LALb DESL LALa RDAc LALc RDAd LALd RDAb Bank “a” × Bank Add. (BA0, BA1) Bank “b” Bank “c” × Bank “d” × IRCD = 1 cycle I RAS = 4 cycles I RCD = 1 cycle IRBD = 2 cycles Qa1 Qb0Qb1 Qa0Qa1Hi-Z Hi-Z DQS (output) DQ (output) Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 BL = 4 DQS (output) DQ (output) RDAa IRCD = 1 cycle IRCD = 1 cycle IRBD = 2 cycles IRBD = 2 cycles Hi-Z CL = 4 CL = 4 CL = 4 Hi-Z Qa0Qa1Qa2 CL = 4 CL = 4 Note: “×” is don’t care. IRC to the same bank must be satisfied. IRBD = 2 cycles

TC59LM814/06CFT-50,-55,-60 2002-08-19 24/38 MULTIPLE BANK WRITE TIMING (CL = 3) MULTIPLE BANK WRITE TIMING (CL = 4) CLK CLK BL = 2 0 1 2 3 4 5 6 7 8 9 10 11 WRAa LALa Command IRC = 5 cycles Da0 WL = 2 WRAb LALb DESL LALa WRAc LALc WRAd LALd WRAb Bank “a” × Bank Add. (BA0, BA1) Bank “b” Bank “c” × Bank “d” × IRCD = 1 cycle I RAS = 4 cycles I RCD = 1 cycle IRBD = 2 cycles Da1 Db0 Db1 Da0 Da1 DQS (input) DQ (input) Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 BL = 4 DQS (input) DQ (input) WRAa IRCD = 1 cycle IRCD = 1 cycle IRBD = 2 cycles IRBD = 2 cycles tDQSS IRBD = 2 cycles Dc0 Dc1 WL = 2 tDQSS tDQSS tDQSS Da0 Da1 Da2 Da3 Dc0 Dc1 Dc2 WL = 2 WL = 2 tDQSS CLK CLK BL = 2 0 1 2 3 4 5 6 7 8 9 10 11 WRAa LALa Command IRC = 5 cycles Da0 WL = 3 WRAb LALb DESL LALa WRAc LALc WRAd LALd WRAb Bank “a” × Bank Add. (BA0, BA1) Bank “b” Bank “c” × Bank “d” × IRCD = 1 cycle I RAS = 4 cycles I RCD = 1 cycle IRBD = 2 cycles Da1 Db0 Db1 Da0 Da1 DQS (input) DQ (input) Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 BL = 4 DQS (input) DQ (input) WRAa IRCD = 1 cycle IRCD = 1 cycle IRBD = 2 cycles IRBD = 2 cycles tDQSS IRBD = 2 cycles Dc0 Dc1 WL = 3 tDQSS tDQSS tDQSS Da0 Da1 Da2 Da3 Dc0 Dc1 WL = 3 WL = 3 tDQSS Note: means H or L. “×” is don’t care IRC to the same bank must be satisfied.

TC59LM814/06CFT-50,-55,-60 2002-08-19 25/38 MULTIPLE BANK READ-WRITE TIMING (BL = 2) MULTIPLE BANK READ-WRITE TIMING (BL = 4) CLK CLK CL = 3 0 1 2 3 4 5 6 7 8 9 10 11 WRAa LALa Command IRBD = 2 cycles RDAb LALb DESL WRAc LALc RDAd DESL WRAc LALc Bank “a” × Bank Add. (BA0, BA1) Bank “b” Bank “c” × Bank “d” Bank “c” × IRCD = 1 cycle IRC = 5 cycles IRWD = 2 cycles IRBD = 2 cycles DQS DQ CL = 4 tDQSS LALd IRCD = 1 cycle IRWD = 2 cycles × × IWRD = 1 cycle IRCD = 1 cycle IWRD = 1 cycle IRCD = 1 cycle Hi-Z Hi-Z Hi-Z tDQSS Hi-Z WL = 2 Da0 Da1 Qb0Qb1 Dc0 Dc1 CL = 3 WL = 2 CL = 3 Qd0 Hi-Z tDQSS Hi-Z Hi-Z tDQSS Hi-Z Da0 Da1 Qb0Qb1 Dc0 Dc1 WL = 3 CL = 4 WL = 3 CL = 4 Hi-Z Hi-Z Hi-Z Hi-Z DQS DQ CLK CLK CL = 3 0 1 2 3 4 5 6 7 8 9 10 11 WRAa LALa Command IRBD = 2 cycles RDAb LALb WRAc LALc RDAd LALd Bank “a” × Bank Add. (BA0, BA1) Bank “b” Bank “c” × Bank “d” IRCD = 1 cycle IRWD = 3 cycles IRBD = 2 cycles DQS DQ CL = 4 tDQSS IRCD = 1 cycle IWRD = 1 cycle IRCD = 1 cycle IWRD = 1 cycle Hi-Z Hi-Z WL = 2 Da0 Da1 Qb0Qb1 Dc0 Dc1 CL = 3 WL = 2 tDQSS Hi-Z Hi-Z Da0 Da1 Qb0Qb1 WL = 3 CL = 4 WL = 3 DQS DQ IRCD = 1 cycle DESL DESL × × tDQSS Da2 Da3 Qb2Qb3 Dc2 Dc3 Da2 Da3 Qb2Qb3 Dc0 Dc1 Dc2 Note: “×” is don’t care IRC to the same bank must be satisfied. tDQSS

TC59LM814/06CFT-50,-55,-60 2002-08-19 26/38 SINGLE BANK WRITE with VARIABLE WRITE LENGTH (VW) CONTROL (CL = 3, BL = 4, Sequential mode) CLK CLK 0 1 2 3 4 5 6 7 8 9 10 11 WRA LAL Command IRC = 5cycles WRA LAL WRA LAL UA LA=#3 VW=2 Address UA LA=#1 VW=1 UA LA=#3 VW=2 IRC = 5cycles DQS (input) DQ (input) Last two data are masked. DESL DESL D0 D1 D0 WRA LAL Command WRA LAL WRA LAL UA LA =#3 UVW=2 LVW=1 Address UA UA UDQS (input) DQ8~DQ15 (input) x16 DESL DESL LA=#1 UVW=1 LVW=1 LA=#3 UVW=2 LVW=1 D0 D1 D0 UDQS (input) DQ0~DQ7 (input) D0 D0 Note: DQS input must be continued till end of burst count even if some of laster data is masked. Refer to "VW Truth Table". Last three data are Last three data are Last three data are Last two data are masked. Last three data are (Write First Two Words) (Write First One Word) Upper byte: Write First Two Words Lower byte: Write First One Word Upper byte: Write First One Word Lower byte: Write First One Word

TC59LM814/06CFT-50,-55,-60 2002-08-19 27/38 MODE REGISTER SET TIMING (CL = 3, BL = 2) POWER DOWN TIMING (CL = 3, BL = 2) CLK CLK Hi-ZDQS (output) DQ (output) IRC = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 RDA LAL RDA MRS Hi-Z Q0 Hi-Z Q1 Hi-Z IRSC = 5 cycles CL = 3 Command IRCD = 1 cycle I RAS = 4 cycles I RCD = 1 cycle RDA or WRA BA, UA LA Valid (op- code) BA, UA A14~A0 BA0, BA1 DESL × × DESL CLK CLK Hi-ZDQS (output) DQ (output) 0 1 2 3 4 5 6 7 n − 1 n n + 1 n + 2 RDA LAL Hi-Z Q0 Hi-Z Q1 Hi-Z CL = 3 Command IPDA = 1 cycle × DESL RDA or WRA DESL IRCD = 1 cycle tIH tIS IPD = 1 cycle tPDEXtQPDH PD Power Down Entry Power Down Exit Note: “×” is don’t care IPD is defined from the first clock rising edge after PD is brought to “Low”. IPDA is defined from the first clock rising edge after PD is brought to “High”. PD must be kept "High" level until end of Burst data output. PD should be brought to high within t REFI(max) to maintain the data written into cell. Read cycle to Power Down Mode lRC(min), tREFI(max)

TC59LM814/06CFT-50,-55,-60 2002-08-19 28/38 POWER DOWN TIMING (CL = 4) Write cycle to Power Down Mode CLK CLK DQS (Input) DQ (Input) 0 1 2 3 4 5 6 7 n − 1 n n + 1 n + 2 WRA LAL Hi-Z D0 D1 Hi-Z Command IPDA = 1 cycle × DESL RDA or WRA DESL WL=3 tIH tIS IPD = 1 cycle tPDEX PD Power Down Entry Power Down Exit Note: “×” is don’t care PD must be kept "High" level until WL+2 clock cycles from LAL command. PD should be brought to high within t REFI(max) to maintain the data written into cell. lRC(min), tREFI(max) 8 9 2 clock cycles D2 D3 BL = 4 Hi-Z Hi-Z DQS (Input) DQ (Input) Hi-Z D0 D1 Hi-Z BL = 2 Hi-Z Hi-Z

TC59LM814/06CFT-50,-55,-60 2002-08-19 29/38 AUTO-REFRESH TIMING (CL = 3, BL = 4) CLK CLK Hi-ZDQS (output) DQ (output) 0 1 2 3 4 5 6 7 n − 1 n n + 1 n + 2 RDA LAL Q0 Hi-Z Q1 Hi-Z CL = 3 Command IRC = 5 cycles DESL RDA or WRA LAL or MRS or REF IRCD = 1 cycle Note: In case of CL = 3, IREFC must be meet 15 clock cycles. When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh command specified by tREFI must be satisfied. tREFI is average interval time in 8 Refresh cycles that is sampled randomly. WRA REF IREFC = 15 cycles Hi-Z IRAS = 4 cycles IRCD = 1 cycle Q2 Q3 CLK WRA REF WRA REF WRA REF WRA REF WRA REF t1 t2 t3 t7 t8

8 Refresh cycle

tREFI = Total time of 8 Refresh cycle t1 + t2 + t3 + t4 + t5 + t6 + t7 + t8 tREFI is specified to avoid partly concentrated current of Refresh operation that is activated larger area than Read / Write operation. DESL

TC59LM814/06CFT-50,-55,-60 2002-08-19 30/38 SELF-REFRESH ENTRY TIMING (CL = 3) SELF-REFRESH EXIT TIMING CLK CLK Hi-ZDQS (output) DQ (output) 0 1 2 m − 1 m m + 1 m + 2 ×*1 Hi-Z Command Notes: 1. “ ×” is don’t care. 2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode. 3. DESL command must be asserted during I REFC after PD is brought to “High”. 4. I PDA is defined from the first clock rising edge after PD is brought to “High”. 5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other operation. 6. Any command (except Read command) can be issued after I REFC. 7. Read command (RDA + LAL) can be issued after ILOCK. ILOCK tPDEX IPDA = 1 cycle*4 PD DESL*3 LAL*7WRA*5 REF*5 DESL RDA*7 n − 1 n n + 1 p − 1 p IREFC Command (1st)*6 Command (2nd)*6 IRCD = 1 cycle IRCD = 1 cycle IREFC Self-Refresh Exit Notes: 1. “ ×” is don’t care. 2. PD must be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self Refresh mode.When PD is brought to "Low" after lPDV, FCRAMTM perform Auto Refresh and enter Power down mode. 3. It is necessary that clock input is continued at least 16 clock cycles from REF command even though PD is brought to “Low” for Self-Refresh Entry. CLK CLK Hi-ZDQS (output) DQ (output) 0 1 2 3 4 5 m − 1 m m + 1 WRA REF Qx Hi-Z Command IRCD = 1 cycle IREFC ICKD = 16 cycles*3 DESL ×*1 tFPDL (min) t FPDL (max) IPDV *2 tQPDH PD Self Refresh Entry Auto Refresh

TC59LM814/06CFT-50,-55,-60 2002-08-19 31/38 FUNCTIONAL DESCRIPTION Network FCRAMTM The FCRAMTM is an acronym of Fast Cycle Random Access Memory. The Network FCRAM TM is competent to perform fast random core access, low latency, low consumption and high-speed data transfer. PIN FUNCTIONS CLOCK INPUTS: CLK & The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the negative edge of CLK . The DQS and DQ output data are referenced to the crossing point of CLK and CLK . The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. POWER DOWN: The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being performed. CHIP SELECT & FUNCTION CONTROL: & FN The CS and FN inputs are a control signal for forming the operation commands on FCRAM TM. Each operation mode is decided by the combination of the two consecutive operation commands using the CS and FN inputs. BANK ADDRESSES: BA0 & BA1 The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for the operation. BA0 BA1 Bank #0 0 0 Bank #1 1 0 Bank #2 0 1 Bank #3 1 1 ADDRESS INPUTS: A0~A14 Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or Extended Mode Register set cycle. UPPER A DDRESS LOWER ADDRESS TC59LM806CFT A0~A14 A0~A7 TC59LM814CFT A0~A14 A0~A6 CLK PD CS

TC59LM814/06CFT-50,-55,-60 2002-08-19 32/38 DATA INPUT/OUTPUT: DQ0~DQ7 or DQ15 The input data of DQ0 to DQ15 are taken in synchronizing with the both edges of DQS input signal. The output data of DQ0 to DQ15 are outputted synchronizing with the both edges of DQS output signal. DATA STROBE: DQS or LDQS, UDQS The DQS is bi-directional signal. Both edges of DQS are used as the reference of data input or output. The LDQS is allotted for Lower Byte (DQ0 to DQ7) Data. The UDQS is allotted for Upper Byte (DQ8 to DQ15) Data. In write operation, the DQS used as an input signal is utilized for a latch of write data. In read operation, the DQS that is an output signal provides the read data strobe. POWER SUPPLY: VDD, VDDQ, VSS, VSSQ VDD and VSS are power supply pins for memory core and peripheral circuits. VDDQ and VSSQ are power supply pins for the output buffer. REFERENCE VOLTAGE: VREF VREF is reference voltage for all input signals.

TC59LM814/06CFT-50,-55,-60 2002-08-19 33/38 COMMAND FUNCTIONS and OPERATIONS TC59LM814/06CFT are introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed. Read Operation (1st command + 2nd command = RDA + LAL) Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out sequentially synchronizing with the both edges of DQS output signal (Burst Read Operation). The initial valid read data appears after CAS latency from the issuing of the LAL command. The valid data is outputted for a burst length. The CAS latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back automatically to the idle state after lRC. Write Operation (1st command + 2nd command = WRA + LAL) Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of DQS input signal (Burst Write Operation). The data and DQS inputs have to be asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. The DQS have to be provided for a burst length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automatically to the idle state after lRC. Auto-Refresh Operation (1st command + 2nd command = WRA + REF) TC59LM814/06CFT are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all outputs are in Hi-Z states. In a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is specified by l REFC. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distributed refresh, Auto-Refresh command has to be issued within once for every 7.8 µs by the maximum. In case of burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 µs (8 × 400 ns) is to 8 times in the maximum. Self-Refresh Operation (1st command + 2nd command = WRA + REF with = “L”) It is the function of Self-Refresh operation that refresh operation can be performed automatically by using an internal timer. When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM814/06CFT become Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to “Low” within t FPDL from the REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the refresh period, the Self-Refresh entry command should be asserted within 7.8 µs after the latest Auto-Refresh command. Once the device enters Self-Refresh mode, the DESL command must be continued for l REFC period. In addition, it is necessary that clock input is kept in l CKD period. The device is in Self-Refresh mode as long as PD held “Low”. During Self-Refresh mode, all input and output buffers except for PD are disabled, therefore the power dissipation lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from “Low” to “High” along with the DESL command, and the DESL command has to be continuously issued in the number of clocks specified by l REFC. The Self-Refresh exit function is asynchronous operation. It is required that one Auto-Refresh command is issued to avoid the violation of the refresh period just after l REFC from Self-Refresh exit. Power Down Mode ( = “L”) When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM814/06CFT become Power Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output buffers except for PD are disabled after specified time. Therefore, the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to “High” and the DESL command has to be issued at next CLK rising edge after PD goes high. The Power Down exit function is asynchronous operation. PD PD

TC59LM814/06CFT-50,-55,-60 2002-08-19 34/38 Mode Register Set (1st command + 2nd command = RDA + MRS) When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1 address inputs. The TC59LM814/06CFT have two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is chosen by BA0 and BA1 in the MRS command. The Regular Mode Register designates the operation mode for a read or write cycle. The Regular Mode Register has four function fields. The four fields are as follows: (R-1) Burst Length field to set the length of burst data (R-2) Burst Type field to designate the lower address access sequence in a burst cycle (R-3) CAS Latency field to set the access time in clock cycle (R-4) Test Mode field to use for supplier only. The Extended Mode Register has two function fields. The two fields are as follows: (E-1) DLL Switch field to choose either DLL enable or DLL disable (E-2) Output Driver Impedance Control field. Once those fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again by another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued before proper operation.

TC59LM814/06CFT-50,-55,-60 2002-08-19 35/38

• Regular Mode Register/Extended Mode Register change bits (BA0, BA1) These bits are used to choose either Regular MRS or Extended MRS BA1 BA0 A14~A0 0 0 Regular MRS Cycle 0 1 Extended MRS Cycle 1 × Reserved Regular Mode Register Fields (R-1) Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2 or 4 words. A2 A1 A0 BURST LENGTH 0 0 0 Reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 Reserved 1 × × Reserved (R-2) Burst Type field (A3) The Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is “0”, Sequential mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both burst types support burst length of 2 and 4 words. A3 BURST TYPE

0 Sequential

1 Interleave

• Addressing sequence of Sequential mode (A3) A column access is started from the inputted lower address and is performed by incrementing the lower address input to the device. The address is varied by the Burst Length as the following. Addressing sequence for Sequential mode DATA ACCESS ADDRESS BURST LENGTH Data 0 n Data 1 n + 1 Data 2 n + 2 Data 3 n + 3 2 words (address bits is LA0) not carried from LA0~LA1 4 words (address bits is LA1, LA0) not carried from LA1~LA2 CLK CLK Command DQS DQ Data Data Data Data RDA LAL CAS Latency = 3

TC59LM814/06CFT-50,-55,-60 2002-08-19 36/38

• Addressing sequence of Interleave mode A column access is started from the inputted lower address and is performed by interleaving the address bits in the sequence shown as the following. Addressing sequence for Interleave mode DATA ACCESS ADDRESS BURST LENGTH Data 0 ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0 Data 1 ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0 Data 2 ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0 Data 3 ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0 2 words 4 words (R-3) CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to the first data read. The minimum values of CAS Latency depends on the frequency of CLK. In a write mode, the place of clock which should input write data is CAS Latency cycles − 1. A6 A5 A4 CAS LATENCY 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 3 1 0 0 4 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved (R-4) Test Mode field (A7) This bit is used to enter Test Mode for supplier only and must be set to “0” for normal operation. (R-5) Reserved field in the Regular Mode Register
• Reserved bits (A8 to A14) These bits are reserved for future operations. They must be set to “0” for normal operation. Extended Mode Register fields (E-1) DLL Switch field (A0) This bit is used to enable DLL. When the A0 bit is set “0”, DLL is enabled. (E-2) Output Driver Impedance Control field (A1 / A6) This bit is used to choose Output Driver Strength. Four types of Driver Strength are supported. A6 A1 OUTPUT DRIVER IMPEDANCE CONTROL 0 0 Normal Output Driver 0 1 Strong Output Driver 1 0 Weaker Output Driver 1 1 Weakest Output Driver (E-3) Reserved field (A2 to A5, A7 to A14) These bits are reserved for future operations and must be set to “0” for normal operation.

TC59LM814/06CFT-50,-55,-60 2002-08-19 37/38 PACKAGE DIMENSIONS Weight: 0.51 g (typ.)

TC59LM814/06CFT-50,-55,-60 2002-08-19 38/38

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices, ” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( “Unintended Usage ”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice. 000707EBARESTRICTIONS ON PRODUCT USE