TC58FVT800FT-85 TOSHIBA | Alldatasheet
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TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 8-MBIT (1M x 8 BITS / 512K x 16 BITS) CMOS FLASH MEMORY
DESCRIPTION
The TC58FVT800/B800 is a 8,388,608 - bit, 3.0-V read-only electrically erasable and programmable flash memory, organized as 1,048,576 words X 8 bits or as 524,288 words X 16 bits. The TC58FVT800/B800 features commands for Read, Program and Erase operations to allow easy interfacing with microprocessors. The commands are based on the JEDEC standard. The Program and Erase operations are automatically executed in the chip. The device has Chip, Block and Multi - Block ase capability. The "Tes8FV1800/B800 is available in either a 44-pin plastic SOP or a 48-pin TSOP package to suit a variety of design applications.
FEATURES
@ Power Supply ® Mode Control Vpp = 2.7 V to 3.6V Compatible with JEDEC standard commands © Organization @ Erase / Program Cycles 1M x 8 bits / 512K xX 16 bits 105 Cycles typ. ®@ Modes ® Access Time Auto Program, Auto Chip Erase 85 ns (Vpp = 3.0 V to 3.6 V) Auto Block Erase, Auto Multiple Block Erase 100ns/120ns (Vpp = 2.7V to 3.0 V) Erase Suspend/ Resume, Block Protection @ Power Dissipation Data Polling /Toggle Bit 250 vA (Standby TTL level) Block Erase Architecture 10 vA (Standby CMOS level) 1X 16 Kbytes / 2 x 5 Kbytes / 30mA (Read operation)
1 X 32 Kbytes / 15 X 64 Kbytes 40 mA (Program / Erase Operations)
Boot Block Architecture e Package TC58FVT800F/FT -Top Boot Block TC58. '800F/B800F : SOP44-P-600-1.27 TC58FVB800F/FT --- Bottom Boot Block Weight: 2.0 g typ.) TC58FVT800FT/B800FT : TSOP48 - P - 1220 - 0.50 PIN ASSIGNMENT (TOP VIEW) (Weight: 0.53 g typ.) RDY/BSY 41 44p RESET ais d4 43 b Ate PIN NAMES A182 43P WE aia q2O 47 B BYTE ATG 4 ab ag Ala 4 4 45 p DQIS/A-1 A6d5 40PA10 aio dé 3 pats DQO to DQ14 | Data Input/Output A5 G6 39P ait ~od7 42 6 Das A3q8 37RA13 NC d 9 40 p DQS | __[chiptnabeimoue | A2d9 36PA14 NC d 10 39 b pQi2 ce Chip Enable Input q 34P A16 q h Vss g 13 32P Vss RDY/BSY q 15 34 B DQIO — DQ8 q 16 29P DQ14 a6 4 19 30 b Das DQ9 4 18 27P DQi3 A4q 21 28 B OF paio 2 b A2 4 23 26 b CE pai d22__a3pvso TC58FVTBOOFT / BBOOFT (TSOP) TC58FVT800F/B800F (SOP)
961001 EBA
@ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. Sine products described in this document are subject to foreign exchange and foreign trade control laws. The information contained herein is resented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 8987-12-10 1728
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 BLOCK DIAGRAM RDY/BSY Vpp o——_—> RDY /BSY DQo DQis Vss_ 0 Buffer | ene | [Leste] WE o Control Auto Sequence Circuit Control Circuit BYTE o RESET 0 Command Register Program Erase aoll GCE Control A0 0 >] A i qd 3 R H q d ° is iq w ile € | 3 3 2 Memory Cell Array i | 8B L 6 E 3 a d A18 o— f t ? Ato 1997-12-10 2/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 MODE SELECTION ed Ce fom emwawea fe[r}*|vwele[i[e] «| com | com | fomiceec [se w|wle[e[*[ | ee [ee fons we ef pe me | fovsw omnes Pepe feof pe | me [ne | a Oe Oe er Oe fweivawaroe ter fw fwls[»[o>* | oe | om | Frenpoav aeons | [-]-|-[-[-|-[%]- |_| Prom toeusnty f= L=>-[->-[*]=] «| wre | none | Notes: *: Vy or Vi. 1) DQ8 to DQ15 are High-Z in Byte mode. ID_ CODE TABLE [went fm ef || Notes: *: Viq or Vit 1) DQ8 to DQ15 are High-Z in Byte mode 2) BA: Block Address 3) 0001H — Protected Block Q000H - Unprotected Block BYTE = Vi_ : Byte mode BYTE = Vij: Word mode 8997-12-10 3/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 COMMAND DEFINITIONS BUS FIRSTBUS | SECONDBUS | THIRD BUS FOURTH BUS FIFTH BUS SIXTH BUS COMMAND WRITE WRITE CYCLE | WRITECYCLE | WRITECYCLE |READ/WRITECYCLE| WRITECYCLE | WRITE CYCLE SEQUENCE CYCLES neQ’o | Addr. [pata | addr. [data| addr [data] Addr | data | Addr. [ data | addr | data | Read/Reset 5555H_ | AAH 55H | 5555H RA” [sss | 1D Read/ 5555H | AAH 55H | 5555H | 90H | IA? Verify Block Auto 4 | 5555H_ | AAH | 24AAH | SSH | 5555H | AOH | PA? Program Auto 5555H_| AAH 55H | 5555H | 80H | 5555H | AAH 55H [ ssssu | Chip E Auto 5555H_| AAH 55H | 5555H | 80H | 555SH | AAH 55H | BA” | 30H Block E1 “_e 5555H 5555H Block 5555H_ | AAH 55H | 5555H | 9AH | 555SH | AAH 55H [ ssssu | 9AH Protect Block Erase Suspend Addr: Viy or Vi, Data: BOH Block Erase Resume Addr: Viy or Vi, Data: 30H Notes: The system should generate the following address patterns: 4)'D : ID Data Word mode: 5555H or 2AAAH to addresses A14 to AO 0098H - Manufacturer Code Byte mode: AAAAH or 5555H to addresses A14 to A-1 O04FH - Device Code (TC58FVT800) DQB to DQI5 are ignored in Word mode OOCEH - Device Code (TC58FVB800) 0001H - Protected Block 1) RA: Read Address 0000H - Unprotected Block 2) RD: Read Data 5) PA: Program Address 3) IA: ID Address (A6, A1, AO) 6) PD: Program Data 00H = Manufacturer Code 7) BA: Block Address 01H = Device Code 02H = Verify Block Protect (A18to A12 = Block Address) Addresses are A18 : A1 in Byte mode (BYTE = Vi) Addresses are A18 : AO in Word mode (BYTE = Vix) HARDWARE STATUS FLAGS Auto Programming togle | 0 [| o [ o | In Progress | Auto Erase (Erase Hold Time) | __0 | Toggle | 0 | o | o | [Auto trae To roagie | of Time Limits |_Auto Programming toggle | 1 | 1 | o | Exceeded [auto erase To | tooge | tt To Notes: 1. DQ outputscell data and RDY/BSY outputs 1 when the operation has completed. 2. DQO, DQ1 and DQ2 pins are reserved for future use. 3. DQ8 to DQI5 : Output 0 or 1 in Word mode. 4. DQO toDQ2 and DQ4: Output 0. 1997-12-10 4/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 BLOCK ERASE ADDRESS TABLES TC58FVT800 (Top Boot Block) BLOCK # | A18 | A17 | A16 A13 | A12 p sao ft fe fe fe T * [= J * Jooo00n to orrrH | 64 kbytes [000001 to o7FFFH | 32K words | pear fe fe Pe Tw | * [= [ = |10000H to rrerFH | 64 kbytes [08000H to OFFFFH | 32k words | } saz fe fe fu te [ * [= [ = |20000H to rere | 64xkbytes [10000H to 17FFFH | 32K words | peas fe Tt Tw Tw | * [= [ * | 300008 to arrrFH | 64 kbytes [18000H to 1FFFFH | 32k words | p sae fe fw fe Te | * [= [ * |40000H to aFerFH | 64 kbytes [20000H to 27FFFH | 32K words | peas ft Th fe [wh | * [ * [ * | 50000H to srrFFH | 64Kbytes | 28000H to 2FFFFH | 32K words | | eas fu fH Tw Te | * [ = [ = |60000H to orrrFH | 64 Kbytes [30000H to 37FFFH | 32K words | }_sar fu [| Hf HW | | * [+ [ * | 70000H to zrrFFH | 64 Kbytes [38000H to aBFFFH | 32K words | peas fH Tt ft Tt | = [= [ = |80000H to arrrF | 64 kbytes [40000H to 47FFFH | 32k words | | sao fH} e te tu [= [= [ * |90000H to oFtrFH | 64 kbytes [48000H to 4FFFFH | 32k words | | earo [ H | it [wn |e | * [ * [ * [Aoo0on toarrerH | 64 kbytes [50000H to S7FFFH | 32K words | Peart fH tt [aw [a | * [= [ = |e0000H to arrrrH | 64 kbytes [58000H to SFFFFH | 32k words | } earz fH | we fe te | * [ * [ * |co000n to crerrH | 64 kbytes [60000H to 67FFFH | 32K words | | ears [ H | cH | ct [cH * [ * | * |0000H toDFFFFH | 64Kbytes | 68000H to 6FFFFH | 32K words | } eae fH | HT wT | * [ = [ = | e0000nto errrrH | 64 Kbytes [70000H to 77FFFH | 32K words | | sats { H | H | Hf | tu [ * | * | F0000H to F7rFFH | 32Kbytes | 78000H to 7BFFFH | 16K words | Pears [ H | eH | wT | wT tT & | Fe000H to ForrFH | kbytes [7c000H to 7crFFH | 4K words | | ear7 [ H | H |W | w | w | t [ H [FA000H to ForrH| kbytes [7D000H to 7DFFFH | 4K words | TC58FVB800 (Bottom Boot Block) BLOCK # | A18 | A17 | A16 | A15 | A14 | A13 | A12 | sao fe} ete te | te | t | * |00000H to o3FFFH | 16Kbytes |00000H to O1FFFH | 8K words | posar fe fe Pe Te Tt Tw Tt |osooorto osFtrH | ekbytes [02000H to o2FFFH | 4k words | paz fu fe fe te |e [ [ |o6000H to o7FFH | skbytes [03000H to o3FFFH | 4K words | peas fe ft Pt Tt | a [= [= |oa000H to oFrrF | 32 Kbytes [04000H to o7FFFH | 16K words | p eae fe fe ft Tw | * [= [ * |10000H to rFeFFH | 64 kbytes [08000H to OFFFFH | 32k words | } sas fe ft fu [ie | * [= [ * | 20000H to 2rerrH | 64 kbytes [10000H to 17FFFH | 32K words | peap ft fe [ch [HT * [ * [ * | 30000H to arrFFH | 64 Kbytes | 18000H to 1FFFFH | 32K words | | sar ff ef HT Tt | * [= [ * |40000H to aFerFH | 64xkbytes [20000H to 27FFFH | 32k words | peas ft fw fe | wh | * [ * J * | 50000H to srFFFH | 64Kbytes | 28000H to 2FFFFH | 32K words | | sao fu fw fw Te | * [= [ = |60000H to orrrFH | 64 kbytes [30000H to 37FFFH | 32k words | | earo { . | h | w | w | * [| * | * |70000H to 7FrFFH | 64 kbytes [38000H to 3FFFFH | 32K words | pear fH te fe Te [= [= [ = | 80000 to arrre | 64 kbytes [40000H to 47FFFH | 32k words | } earz [He te tu | * [ * [ * |90000H to ortrrH | 64 kbytes [48000H to 4FFFFH | 32k words | | ears fH | ct [cH Tt | * [ * [ * [Ao000n toarrer | 64 Kbytes [50000H to S7FFFH | 32K words | Pears [ H | it [a | a | * [= [ * |e0000h to arrrrH | 64 kbytes [58000H to SFFFFH | 32k words | | eas fH | HT et Tt | * [ * [ * |c0000k to creFFH | 64 kbytes [60000H to 67FFFH | 32K words | | sate [ H | Hf] te [| wh | * [ * | * |00000H topFrFrFH | 64Kbytes |68000H to 6FFFFH | 32K words | | ear7 fH | wt we | * [ = [ = |e0000H to errrrH | 64 kbytes [70000H to 77FFFH | 32k words | * Vig or Vit Addresses are A18 : A1 in Byte mode (BYTE = Vi.) Addresses are A18 : AO in Word mode (BYTE = Vix) 1997-12-10 5/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 ABSOLUTE MAXIMUM RATINGS a 1) Vion supply for more than 10 seconds is not recommended. The device could be damaged. 2) Outputs should be shorted for no more than one second. No more than one output should be shorted at a time. CAPACITANCE (Ta = 25°C, f= 1 MHz) Tem | meena [vary f «fe [| cor | onan cpacons | v=o | [| ® | | [eas | comalico | vunov [| 0 | This parameter is periodically sampled and is not tested for every device. RECOMMENDED DC OPERATING CONDITIONS (Ta=-40 to 85°C) a ee ee ee 1) -2V (pulse width of 20ns Max) 2) Vip supply for more than 10 seconds is not recommended. The device could be damaged. 8987-12-10 6/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 DC CHARACTERISTICS (Ta = —40 to 85°C, Vpp = 2.7 to 3.6V) a a [ic | tout ents carers [avs vos veo || et er eee Vou2 Output High Voltage (CMOS) v Feweasma doesn] | a ee cycle = tac (min) [oor | veo Awoae reson covet | vn=vn/vis ozone [= | | [sor | veo Awoae ewe cree [vine rome | =| Fs [von Sy cove cy) | RFs RSET = Vn nSET= wn | =| ao _| eS or RESET = Vss + 0.2V Pe | ah veto preven | ave wo stee 9 | - | ao | [ss | tow vn eco votwe [Si ds 1) Less than 10 seconds AC TEST CONDITIONS [ns i ie ca Tnetow wom | TOO TTD
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 AC CHARACTERISTICS AND OPERATING CONDITIONS pos TT svie0t PARAMETER ont [win [wax win | wax [min | wax | [isc |Read Gide mes 00 20 | [tace Address Access Time as | 00 020 | [ice] Ce Access Time as | t00 = 120 P| [tog JOE Access Time as a 50 | [ieee | CE to Output lowe SS of = 0 ps | [tore JOE to Output owz do 0 = 0 | [tocy [OF Hold Time(Read) | 0 |=} 0 |=] 0 | =} ns | [tou [Output Data Hold Time | 0 | ~-|o |=] 0 | =} ns | [torr [cE to Output Highz a0 a0 50 [toe [OE to Output High? 30 a0 50 | [scum [Command Write Cycle Time | es _| - | 100 | - | 120 | - [ns | [tas [Address Setup Time SSS 0-0 | =| 0 | [tain [Address Hold Time | as [=| so] =| so | - [ns | [tos | Data Setup Time | 4s [= [so] =| 60 [| - [ns | [tox [Data Hold Time SSS 0 0] = 0 | [swein [WE Low Level Hold Time» | as_| =| so] =| s0_| - [ns | [twenu [WE High Level Hold Time» | 20| =| 20 | =| 20 [| - [ns | [ices] CE Setup Time to WE Active» SSS 0 0 0 | [sce [CE Hold Time from WE High tevel_* [0 | ~- | o | - | 0 | - ns | [tors [OE Setup to We Active SSS 0 | =P 0] = 0 | [torus [OE Hold Time (Toggle, Data Polling) | 10 | - | 10 | - | 10 [| - [ns | [tour [OE High Level Hold Time (Toggle) | 20| - | 20 | - | 20| - [ns | [tecew [Auto Chip Erase Time SSS nw | oe | de Ps | [tenew [Auto Block Erase Time SSS | | - fis] - fs | [tvs [Von Setup Times 500 YS | [tausy | Program/ Erase Valid to RDY/ESY Delay | 35 | - | 40 | =] so} ns | [ise] RESET Low Level Hold Time SSS 00] 500] = | 500] ns | [tse [ROY /BSY Recovery Time _——SCSCSCSCS 9 | - 0] - | 0 f= po | [in [RESET Recovery Time | 500 = 800] = 00 | [icears [CE Setup time BYTE Transition SSCS Ss Ps | [tsp [BYTE to Output Highz SSCS = | 30 - | a0 50 | [iver |Vip Transition Time a | [ives [Vip Setup Time es | [tye [OF Hold Time Glock Protea) SSS as | [tenia [WE Low Level Hold Time (Block Protec) | 100 | - | 100 | =] 100 | [vs | [teas [Protect Address Setup Time _—=——SSSSSCSCS 0 | 0 = 0 po | [temic [Protect Address Hold Time | 0 | =| 0] =] 0 | =} ns | [icese CE Setup Time (Block Protect) SSCS | [iccue [cE Hold Time (Block Protect) SSS 8) ds | * ; WE Control ** > Typ. 1997-12-10 8/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 OPERATING MODES READ MODE When the device is set to Read mode, it acts as an asynchronous ROM with an access time of 85/100/120 ns. The device is set to Read mode at power-on or when an Auto - Program / Erase operation completes. A software or hardware reset is necessary to return the device to Read mode when an Auto Program /Erase operation fails. STANDBY MODE There are two methods of entering Standby mode: the first involves using both CE and RESET and the second using only RESET. The first method involves using CE and RESET for mode control. If Vpp + 0.2 V (CMOS level) is applied to CE and RESET when the device is operating in Read mode, the current is reduced below 10 vA, Similarly, if Vi (TTL level) is applied to CE and RESET, the current is reduced below 250 yA. When using CE for control, make sure that the device is operating in Read mode; otherwise, it is not possible to enter Standby mode. The second method involves using only RESET for mode control. IF Vsg+0.2 V (CMOS level) is applied to RESET when the device is operating in Read mode, the current is reduced below 10 “A. Similarly, if Vi, (TTL level) is applied to RESET, the current is reduced below 250 A. The difference the control method using CE described above, is that if Vi, is applied to RESET when the device is operating in any mode other than Read mode, it enters Standby mode after stopping the operating which is currently being executed. This is a hardware reset and is described later. In standby mode, DQ is put in high-impedance state. COMMAND WRITE The TC58FVT800/B800 utilizes the JEDEC command control standard for a single power supply E2PROM. A command is executed by inputting an address and data into the Command register. The command is entered by a WE Control Write (WE pulse with CE = Vy, and OE = Vyy) or a CE Control Write (CE pulse with WE = Vj, and OE = Vyyq). The address is latched on the falling edge of either WE or CE. The data is latched on the rising edge of either WE or CE. V/O0 to7 are valid for data input and 1/08 to 15 are ignored. A command is when the Reset command is input. The device then enters Read Mode. When an undefined command is input, the Command register is reset and the device enters Read mode. RESET (Software Reset) The device does not enter Read mode automatically when a command such as Auto Program/ Erase or ID Read is not correctly executed (for example, if Program or Erase fails). The Reset or Read Command is necessary to return the device to Read mode. The Reset and Read commands must also be used to reset the Command register. RESET (Hardware Reset) A hardware reset is used for aborting Auto mode operations such as Auto Program/Erase and for resetting the operation mode. The device enters Read mode 20 vs after a 500-ns Low level input pulse tothe RESET pin. Data may be corrupted if the device is reset during an Auto mode operation. 1997-12-10 9/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 After a hardware reset the device enters Read mode when RESET = Viy and Standby mode when RESET = Vi. The DQ pins are High-Impedance when RESET = Vj. The Read operation sequence and input of any command are allowed after the device enters Read mode. ID READ MODE The ID Read mode is used to establish the device type. The ID Read mode is set either from the Command mode by inputting a 90H command or from the EPROM mode by applying Vip to the AQ pin. When AO, Al and A6 = Vjz, the data that is read is the manufacturer code (0098H). When AO = Vin and Al and A6 = Vjz, the data that is read is the device code (4FH). The access time for an ID Read is the same as that of a normal Read operation. I/O8 to 15 are in High-Impedance state in Byte mode. A reset command is necessary to return the device to Read mode from command mode. And applying Vjy to the AQ pin is necessary to return the device to Read mode from EPROM mode. AUTO PROGRAM MODE The TC58FVT800/B800 can be programmed in either byte or word units. The Auto Program mode is set using the Program command. The program address is latched on the falling edge of the WE signal and data is latched on the rising edge of the fourth bus cycle. Auto programming starts on the rising edge of the WE signal in the fourth bus cycle. The Program and Program Verify commands are automatically executed by the chip. The device status during programming is determined from the Hardware Sequence flag. Programming of a protected block is ignored. The device enters Read mode 3 ys after the rising edge of the WE signal in the fourth bus cycle. The device allows the programming of memory cells from 1 to 0. The programming of Memory cells from 0 to 1 will fail. A cell must be erased to turn it from 0 to 1. If an Auto Program operation fails, the device remains in programming state and does not automatically return to Read mode. The device status can be determined from the setting of the Hardware Sequence flag. Either a Reset command or a hardware reset is necessary to return the device to Read mode after a failure. If a programming operation fails, please do not try to use the block which contains the address to which data could not be programmed. Auto Chip Erase Mode The Auto Chip Erase mode is set using the Chip Erase command. The Auto Chip Erase operation starts on the rising edge of WE in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased and verified as erased by the chip. The device status is determined from the Hardware Sequence flag. Command inputs are ignored during an Auto Chip Erase. The hardware reset allows interruption of an Auto Chip Erase operation. The Auto Chip Erase operation does not complete correctly when interrupted. Hence a further Erase operation is necessary. An attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not be executed and the device will enter Read mode 100 vs after the rising edge of the WE signal in the sixth bus cycle. If an Auto Chip Erase operation fails, the device remains in, erasing state and does not return to Read mode. The device status is determined from the Hardware Sequence flag. Either a Reset command or a hardware reset is necessary to return the device to Read mode after a failure. 1997-12-10 10/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 Auto Block / Multi Block Erase Mode The Auto Block and Multi Block Erase modes are set using the Block Erase command. The block address is latched on the falling edge of the WE signal in the sixth bus cycle. The Block Erase starts as soon as the hold time has elapsed after the rising edge of the WE signal. All memory cells in the selected block are automatically programmed to 0, erased and verified as erased by the chip. The Multi Block Erase operation allows erasing of multiple blocks. Any additional block addresses or Multi Block Erase commands must be input within the Erase Hold Time - that is, within 50 us of any WE signal rising edge. The device status can be determined from the setting of the Hardware Sequence flag. Commands (except Erase Suspend) are ignored during a Block/Multi Block Erase operation. The operation can be aborted by a hardware reset. The Auto Erase operation does not complete correctly when aborted, therefore, a further Erase operation is necessary. An attempt to erase a protected block is ignored. If all the selected blocks are protected, the Auto Erase operation is not executed and the device returns to Read mode 100 ws after the rising edge of the WE signal in the last bus cycle. If an Auto Erase operation fails, the device remains in erasing state and does not return to Read mode. The device status is determined from the Hardware Sequence flag. Either a Reset command or a hardware reset is necessary to return the device to Read mode after a failure. Erase Suspend / Resume Mode The Erase Suspend mode is used to read data from a block not selected for erasing. The Erase Suspend command is allowed during a Block Erase operation or during the Block Erase Hold Time; it is ignored in other operation modes. A Block Erase operation is also suspended if the Suspend command is input during the Block Erase Hold Time. The device is reset if any command other than Suspend is input. The suspended device recognizes only Read and Resume commands. The device enters Suspend mode 15 vs after the Erase Suspend command is input. The device then enters a pseudo-Read Mode. Data can be read out from an unselected block but is invalid if the address is set to a block selected for erasing. The device status can be determined from the Hardware Sequence flag. DQ6 (the toggle bit) stops toggling and RDY/BSY outputs 1 once the device is set to pseudo-Read mode. The host processor must track the current device mode since there is no way of telling whether the device is in pseudo-or ordinary Read mode. The device remains in pseudo-Read mode even if a Suspend command is input. The device restarts the Block Erase operation after receiving a Resume command. The device returns to the status in which the Suspend command was input. The DQ6 output toggles and RDY/BSY outputs a 0. 1997-12-10 11/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 BLOCK PROTECT The TC58FVT800/B800 has a block protection feature to prevent programing and erasing of protected blocks. Block protection is enabled by either hardware protection (1) or a software command mode (2). The initial device is shipped with all blocks unprotected. (1) A blocks is protected when: A9 = OF = Vip, CE = Vit, A0/A6 = Vi,, Al = Vin; the block address is set using A12 to A18. The block protect data is programmed within tpp_H of the WE signal going Low. (2) A block can also be protected using a software command. Block protection is executed by setting the WE signal to Low for tppLH while CE = Vyy. After the command input in the sixth bus cycle A12 to A18 = the block address. Block protection can be verified using the Verify Block Protect command. TEMPORARY BLOCK UNPROTECTION The TC58FVT800/B800 has a temporary block unprotection feature which disables block protection for all protected blocks. Unprotection is enabled by applying Vip to the RESET pin. In this state any block can be programmed or erased. The device returns to the previous condition after Vip is removed from the RESET pin. That is, previously protected blocks are protected again. VERIFY BLOCK PROTECT The Verify Block Protect command is used to check whether a block is protected or unprotected. Verify Block Protect is enabled either through hardware (1) or by a software command (2). In Word mode 0001H is output when the block is protected and 0000H is output when it is unprotected. DQ8 to 15 are High-Impedance in Byte mode. (1) Verify Block Protection is enabled when: A9 = Vjp, AO and A6 = Vj, and Al = Vyy. A12 to A18 = the block address. (2) Verify Block Protection can also be enabled using a software command. 1997-12-10 12/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 HARDWARE SEQUENCE FLAG The TC58FVT800/B800 has a Hardware Sequence flag which allows the device status to be determined during Auto operation. The output data is read out with the same timing as Read mode at CE = OF = Vj,. RDY/BSY outputs either High or Low. The device re-enters the Read mode automatically after Auto operation has completed successfully. The device status is read out from the Hardware Sequence flag and the operation result is verified by comparing the read-out data to the original data. DQ7 (DATA Polling) The device status can be determined using the data polling function during an Auto Program or Auto Erase operation. DATA polling begins on the rising edge of WE in the last bus cycle. In an Auto Program operation, DQ7 outputs inverted data during the programming operation and outputs real data after programming has finished. In an Auto Erase operation, DQ7 outputs 0 during the Erase operation and outputs 1 when the Erase operation has finished. If an Auto Program operation fails, DQ7 simply outputs the data. The latched address is reset after an operation has finished. The polling data is asynchronous with the OE signal. DQ6 (Toggle Bit) The device status can be determined by the Toggle Bit function during an Auto Program or Auto Erase operation. In an Auto Program operation the Toggle bit begins toggling on the rising edge of WE in the last bus cycle. In an Auto Erase operation The Toggle bit begins toggling as soon as the Erase Hold Time has elapsed after the rising edge of the WE signal in the last bus cycle. DQ6 alternately outputs a 0 or a 1 for each attempt (OE access) while CE = Viz, while the device is busy. When the internal operation has been completed, toggling stops and valid memory cell data can be read by subsequent reading. If the operation failed, the DQ6 output toggles. DQ6 toggles for around 3 ws when an attempt is made to execute an Auto Program operation on a protected block. It then stops toggling. DQ6 toggles for around 100 ~s when an attempt is made to execute an Auto Erase operation on a protected block. It then stops toggling. After toggling stops the device returns to Read mode. DQ5 (Internal Time-out) DQ5 outputs a 1 when the Internal Timer has timed out during a Program or Erase operation. This indicates that the operation has not completed within the allotted time. An attempt to program 1 into a cell containing 0 will fail (see Auto Program mode). DQ5 outputs 1 in this case. Either a hardware reset or a software Reset command is required to put the device into Read mode. 1997-12-10 13/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 DQ3 (Block Erase Timer: The Block Erase operation starts 50 ~s (Erase Hold Time) after the rising edge of WE in the last command cycle. DQ3 outputs a 0 during the Block Erase Hold Time and a 1 when the Erase operation starts. Additional Block Erase commands can only be accepted during this Block Erase Hold Time. Each Block Erase command received within this hold time resets the timer, allowing additional blocks to be marked for erasing. DQ3 outputs a 1 if the Program or Erase operation fails. RDY/BSY (READY/BUSY) TC58FVT800/B800 has a RDY/BSY signal to indicate the device status to the host processor. A 0 (Busy state) indicates that an Auto Program or Auto Erase operation is in progress. A 1 (Ready state) indicates that the operation has finished and that the device can accept a new command. The RDY/BSY signal outputs a 0 when an operation has failed. The RDY/BSY signal outputs a 0 after the rising edge of WE in the last command cycle of a Program operation and during the Erase Hold Time after the last command cycle of an Erase operation. During an Auto Block Erase operation, commands other than Erase Suspend are ignored. The RDY/BSY signal outputs a 1 during an Erase Suspend operation. The output buffer for the RDY/BSY pin is an open drain type circuit, allowing a wired-OR connection. A pull-up resistor needs to be inserted between Vpp and the RDY/BSY pin. DATA PROTECTION The TC58FVT800/B800 utilizes a JEDEC standard command sequence which protects data against accidental alteration due to noise. Vpp Lock-out Voltage The device is reset when Vpp is less than VLKo to protect memory cell data against Vpp noise, and during power-up and power-down. An Auto Program or Erase operation stops when Vpp drops below Viko. An Erase Suspend operation is reset and an Erase operation stops if the device is in Suspend mode. An operation will not complete correctly if it is interrupted by Vpp Lock-out. WE Glitch Pulses Glitches must be suppressed (to less than 5ns) in order for operation to proceed smoothly. Protection at Power-on A command is not recognized on the rising edge of WEif Vpp rises from 0 V to the operating voltage while WE = Vj, CE = Vi and OF = Vjy. In this case the device is reset and enters Read mode. 1997-12-10 14/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 tec
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 Auto Program Operation (WE Control) L274 Auto Chip Erase / Auto Block Erase option WE sonra or 1997-12-10 16/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 DATA Polling during Program/Erase Operation & YY WU tort * == ee Ve Dout7 om | Toggle Bit warns Proments Operation 1997-12-10 17728
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 RDY/BSY during Auto Program/Erase Operation Command input sequence During operation ROviBSY Ly tausy Hardware Reset Operation WE tre RESET a RDY/BSY Read after RESET tre RESET tacc ton 1997-12-10 18/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 Block Protect Operation (Hardware Block Protect Verify Block Protect Al Y} BA:Block address *: 0001H indicates that block is protected. 1997-12-10 20/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 Block Protect (Software) Block Protect Setup Block Protect Verify Block Protect a pg CK _sies KK KKK KE XK > 6th Command Cycle “ACC € TP nn re ot | WE | BA: Block address * —: 0001H indicates that block is protected. 1997-12-10 21/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 FLOWCHARTS Auto Program Auto Program Command Sequence (see below) Yes Auto Program Command Sequence (Address/Command) Note: Word mode command sequence is shown. 1997-12-10 22/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 Auto Erase Auto Erase Command Sequence (see below) DATA Polling or Toggle Bit Auto Erase Completed Auto Chip Erase Command Sequence Auto Block/Multiple Block (Address/Command) Erase Command Sequence (Address/Command) 5555H/AAH 5S5SH/AAH 2AAAH/SSH 2AAAH/SSH 5555H/80H 5555H/80H 555SH/AAH 555SH/AAH 5555H/10H Block Address/30H Block Address/30H Additional Block Erase commands are optional Block Address/30H Note: Word mode command sequence is shown. 1997-12-10 23/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 DQ7 DATA Polling Read Byte (DQ0 to DQ7) Addr. = VA Read Byte (DQO to DQ7) Addr. = VA No VA: Byte address for programming. Any of the addresses within the block being erased during a Block Erase operation. Don't care during a Chip Erase operation Note: 1) DQ7 must be rechecked even if DQ5= 1 because DQ7 may change at the same time as DQ5. DQ6 Toggle Bit Read Byte (DQO to DQ7) Addr. = VA He Yes S005 = 17 Yes 1) Read Byte (DQO to DQ7) Addr. = VA No Yes VA: Byte address for programming. Any of the addresses within the block being erased during a Block Erase operation. Don't care during a Chip Erase operation Any address not within the current block during an Erase Suspend operation Note: 1) DQ6 must be rechecked even if DQ5 = 1 because DQ6 may stop toggling at the same time that DQS changes to 1. 1997-12-10 24/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 Block Protect (Hardware. Set up Block Address Addr. = BA OE = AD = Vip, CE = Vit AG, Al, AO = 0, 1,0 Read from Block Address = BA; A6, A1, AO = 0, 1, 0 No i =O n= Data = 01H? Yes Yes No BA: Block address 1997-12-10 25/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 Block Protect (Software) PLSCNT = 1 Write Block Protect Command Sequence CE = Vin, OF = Vin, WE = Vin Set up Block Address Address = BA Time-out 100 ,s Write ID Read Command Sequence Write Reset Command Sequence Read from Block Address = BA; A6,A1,A0 = 0, 1,0 No No Data = 01H? a Yes Yes Write Reset Command Sequence Device Failed Yes Protect Another Block? No Block Protect Complete BA: Block Address 1997-12-10 26/28
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 PACKAGE DIMENSIONS @ Plastic SOP SOP44-—P-600-1.27 Unit: mm HOOHORAAU oan oenannooon y BA A A A AA A A A ce I , | | 1 22 0.765TYP 0.3594 Ea TEG 28.7MAX 28.230.2 a Po ‘| 3B OOO} uu g 3 ZI a =p 3 0.840.2 8997-12-10 27728
TOSHIBA TC58FVT800/B800F/FT-85,-10,-12 PACKAGE DIMENSIONS @ Plastic TSOP TSOP I 48—P—1220—0.50 Unit: mm fe Bl a 1 ey i= 48a] an = fe ba oo =| aI Fy es = N & = = = = =| Ee = Be : = | 24 cal E = 2 § [tear & 1.040.1 0.140.05 20.040.2 s t.emax |_| wm its) a Lt — s a ee 8 lt: 0.540.1 1997-12-10 28/28