TC58DAM72A1FT00

TC58DVM72A1F TOSHIBA | Alldatasheet

Document overview

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Technical content

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 1/34 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 128-MBIT (16M u 8 BITS/8M x 16BITS) CMOS NAND E2PROM

DESCRIPTION

The TC58DxM72x1xxxx is a 128-Mbit (138,412,032) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes/264 words u 32 pages u 1024 blocks. The device uses static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte/256-words increments. The Erase operation is implemented in a single block unit (16 Kbytes 512 bytes: 528 bytes u 32 pages/8k words + 256 words:264 words x 32 pages). The TC58DxM72x1xxxx is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage.

FEATURES

x Organization TC58DxM72A1xxxx TC58DxM72F1xxxx Memory cell allay 528 u 32K u 8 264 x 32k x 16 Register 528 u 8 264 x 16 Page size 528 bytes 264 words Block size (16K 512) bytes (8k + 256) words x Modes Read, Reset, Auto Page Program Auto Block Erase, Status Read x Mode control Serial input/output Command control x Power supply TC58DVM72x1xxxx TC58DAM72x1xxxx V c c : 2 . 7 V t o 3 . 6 V 2 . 7 V t o 3 . 6 V V c c q : 2 . 7 V t o 3 . 6 V 1 . 6 5 V t o 1 . 9 5 V x Program/Erase Cycles 1E5 cycle (with ECC) x Access time Cell array to register 25 Ps max Serial Read Cycle 50 ns min x Operating current Read (50 ns cycle) 10 mA typ. Program (avg.) 10 mA typ. Erase (avg.) 10 mA typ. Standby 50 PA max. x Package TSOP I 48-P-1220-0.50 (Weight:0.53g typ) xTOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in ge neral can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to a void situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Gui de for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. xThe TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and /or reliability or a malfunction o r failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this docume nt shall be made at the customer’s own risk. xThe products described in this document are subject to the foreign exchange and foreign trade laws. xThe information contained herein is presented only as a guide for the applications of our products. No responsibility is assume d by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from i ts use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION o r others. xThe information contained herein is subject to change without notice. 000707EBA1

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 2/34 PIN ASSIGNMENT (TOP VIEW) PINNAMES I/O1 to I/O8 I/O port I/O9 to I/O16 I/O port (x16) CE Chip enable WE Write enable RE Read enable CLE Command latch enable ALE Address latch enable WP Write protect BY/RY Ready/Busy GND Ground input VCC Power supply VCCQ I/O port Power supply VSS Ground TC58DVM72A1FT00 / TC58DAM72A1FT00 NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC V CCQ VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 NC NC NC NC NC GND BY/RY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC x16 NC NC NC NC NC GND BY/RY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC TC58DVM72F1FT00 / TC58DAM72F1FT00 x16 VSS I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 NC NC V CCQ NC NC NC I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 V SS

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 3/34 BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS VALUE SYMBOL RATING TC58DVxxxxx TC58DAxxxx unit VCC Power Supply Voltage 0.6~4.6 0.6~4.6 V VCCQ I/O port Power Supply Voltage 0.6~4.6 0.6~2.6 V VIN Input Voltage for Control pins 0.6~4.6 0.6~2.6 V PD Power Dissipation 0.3 0.3 W Tsolder Soldering Temperature(10s) 260 260 °C Tstg Storage Temperature 55~150 55~150 °C Topr Operating Temperature 0~70 0~70 °C CAPACITANCE *(Ta =25°C, f= 1 MHz) SYMB0L PARAMETER CONDITION MIN MAX UNIT CIN Input V IN 0 V  10 pF COUT Output V OUT 0 V  10 pF * This parameter is periodically sampled and is not tested for every device. VCC I/O Control circuit Status register Address register Command register Column buffer Column decoder Data register Sense amp Memory cell arrayControl HV generator Row address decoder Logic control BY/RY I/O1 VSS I/O8 or I/O16 to WP CE CLE ALE WE RE BY/RY Row address buffer decoder VCCQ

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 4/34 VALID BLOCKS (1) SYMBOL PARAMETER MIN TYP. MAX UNIT NVB Number of Valid Blocks 1004  1024 Blocks (1) The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document. (2) The first block (block address #00) is guaranteed to be a valid block at the time of shipment. RECOMMENDED DC OPERATING CONDITIONS TC58DVM72A1xxxx,TC58DVM72F1xxxx SYMBOL PARAMETER MIN TYP. MAX UNIT VCC Power Supply Voltage 2.7 3.3 3.6 V VCCQ I/O Port Power Supply Voltage 2.7 3.6 V VIH High Level input Voltage 2.0  VCCQ 0.3 V VIL Low Level Input Voltage 0.3*  0.8 V * 2 V (pulse width lower than 20 ns) TC58DAM72A1xxxx,TC58DAM72F1xxxx SYMBOL PARAMETER MIN TYP. MAX UNIT VCC Power Supply Voltage 2.7 3.3 3.6 V VCCQ I/O Port Power Supply Voltage 1.65 1.8 1.95 V VIH High Level input Voltage V CCQ X 0.78  VCCQ 0.3 V VIL Low Level Input Voltage 0.3*  VCCQ X 0.22 V * 2 V (pulse width lower than 20 ns) DC CHARACTERISTICS (Ta = 0° to 70°C, VCC 2.7 V to 3.6 V) SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT IIL Input Leakage Current V IN 0 V to VCCQ r 10 PA ILO Output Leakage Current V OUT 0 V to VCCQ  r 10 PA ICCO1 Operating Current (Serial Read) CE VIL, IOUT 0 mA, tcycle 50 ns  10 30 mA ICCO3 Operating Current (Command Input) tcycle 50 ns  10 30 mA ICCO4 Operating Current (Data Input) t cycle 50 ns  10 30 mA ICCO5 Operating Current (Address Input) tcycle 50 ns  10 30 mA ICCO7 Programming Current   10 30 mA ICCO8 Erasing Current  10 30 mA ICCS1 Standby Current CE VIH, WP 0 V/VCCQ  1 mA ICCS2 Standby Current CE VCCQ 0.2 V, WP 0 V/VCCQ  10 50 PA VOH High Level Output Voltage I OH mA VCCQ -0.5  V VOL Low Level Output Voltage I OL 2.1 mA  0.4 V IOL ( BY/RY ) Output Current of BY/RY pin V OL 0.4 V  8  mA

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 5/34 AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Ta 0° to 70°C, VCC 2.7 V to 3.6 V) SYMBOL PARAMETER MIN MAX UNIT NOTES tCLS CLE Setup Time 0  ns tCLH CLE Hold Time 10  ns tCS CE Setup Time 0  ns tCH CE Hold Time 10  ns tWP Write Pulse Width 25  ns tALS ALE Setup Time 0  ns tALH ALE Hold Time 10  ns tDS Data Setup Time 20  ns tDH Data Hold Time 10  ns tWC Write Cycle Time 50  ns tWH WE High Hold Time 15  ns tWW WP High to WE Low 100  ns tRR Ready to RE Falling Edge 20  ns tRP Read Pulse Width 35  ns tRC Read Cycle Time 50  ns tREA RE Access Time (Serial Data Access)  35 ns tCEA CE Access Time (Serial Data Access,ID Read)  45 ns tALEA ALE Access Time (ID Read)  ns tCEH CE High Time for Last Address in Serial Read Cycle  Ns (2) tREAID RE Access Time (ID Read)  35 ns tOH Data Output Hold Time 10  ns tRHZ RE High to Output High Impedance  30 ns tCHZ CE High to Output High Impedance  20 ns tREH RE High Hold Time 15  ns tIR Output-High-impedance-to- RE Falling Edge 0  ns tRSTO RE Access Time (Status Read)  35 ns tCSTO CE Access Time (Status Read)  45 ns tRHW RE High to WE Low 0  ns tWHC WE High to CE Low 30  ns tWHR WE High to RE Low 30  ns tR Memory Cell Array to Starting Address  25 Ps tWB WE High to Busy  200 ns tAR2 ALE Low to RE Low (Read Cycle) 50  ns tRB RE Last Clock Rising Edge to Busy(in Sequential Read)  200 ns tCRY CE High to Ready(When interrupted by CE in Read Mode)  tr( BY/RY ) Ps (1)(2) tRST Device Reset Time (Read/Program/Erase)  6/10/500 Ps AC TEST CONDITIONS CONDITION PARAMETER TC58DVxxxxx TC58DAxxxx Input level 2.4 V, 0.4 V V CCQ -0.2 V, 0.2 V Input pulse rise and fall time 3 ns 3 ns Input comparison level 1.5 V, 1.5 V 0.9 V, 0.9 V Output data comparison level 1.5 V, 1.5 V 0.9 V, 0.9 V Output load C L (100 pF) 1 TTL C L (30 pF)

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 6/34 Note: (1) CE High to Ready time depends on the pull-up resistor tied to the BY/RY pin. (Refer to Application Note (9) toward the end of this document.) (2) Sequential Read is terminated when t CEH is greater than or equal to 100 ns. If the RE to CE delay is less than 30 ns, BY/RY signal stays Ready. PROGRAMMING AND ERASING CHARACTERISTICS (Ta =0° to 70°C, VCC 2.7 V to 3.6 V) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES tPROG Programming Time  200 1000 Ps N Number of Programming Cycles on Same Page  3 (1) tBERASE Block Erasing Time  2 10 ms (1): Refer to Application Note (12) toward the end of this document. : 0 to 30 ns oBusy signal is not output.A CE RE tCEH t 100 ns 525 Busy BY/RY *: VIH or VIL A526 527

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 7/34 TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data Command Input Cycle Timing Diagram CLE ALE CE RE WE Hold Time tDH Setup Time tDS I/O1 to I/O8 : VIH or VIL tCS tDHtDS tALS tALH tWP tCLS tCH tCLH : VIH or VIL CE CLE WE ALE I/O1 to I/O8

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 8/34 Address Input Cycle Timing Diagram Data Input Cycle Timing Diagram : VIH or VIL WE tWP tWP tWH tWP tALS tWC tDHtDS DIN0 DIN1 tCLH tCH ALE CLE CE I/O1 to I/O8 DIN 527 tDHtDS tDHtDS tCH tCS tCS tDHtDS : VIH or VIL tDHtDS tCLS CLE tALS tWP tALH tWH tWP tWH tWP A0 to A7 tDHtDS A9 to A16 A17 to A23 tCS tWC tCS CE WE ALE I/O1 to I/O8 tCH

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 9/34 Serial Read Cycle Timing Diagram Status Read Cycle Timing Diagram tWHR WE tDHtDS tCLS tCLS tCS tCLH tCHtWP Status output70H* tWHC tCSTO tIR tRSTO tRHZ tCHZ CE CLE RE BY/RY I/O1 to I/O8 : VIH or VIL tOH * 70H represents the hexadecimal number tREH tCHZ CE tRHZtREA tRC tRR tRHZtREAtRHZtREA RE BY/RY I/O1 to I/O8 tOH tOH tOH tRPtRP tRP tCEA tCH

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 10/34 Read Cycle (1) Timing Diagram Read Cycle (1) Timing Diagram: When Interrupted by CE tCS tCLS tCLH tCH 00H A0 to A7 A9 to A16 A17toA23 DOUT N DOUT N 1 tDHtDS tWC tALStALH tALH tR tAR2 tRR tRC tREA tWB tCHZ WE CLE CE ALE RE BY/RY Column address DOUT N 2 tRHZ : VIH or VIL I/O1 to I/O8 tDHtDStDHtDStDHtDS tOH * Read Operation using 00H Command N: 0 to 255 I/O1 to I/O8 tCS tCLS tCLH tCH 00H A0 to A7 A9 to A16 A17toA23 DOUT N DOUT N 1 tDHtDS tWC tALStALH tALH tR tAR2 tRR tRC tREA tWB WE CLE CE ALE RE BY/RY : VIH or VIL tDHtDStDHtDStDHtDS DOUT N 2 Column address DOUT 527 * Read Operation using 00H Command N: 0 to 255

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 11/34 Read Cycle (2) Timing Diagram Read Cycle (3) Timing Diagram tCS tCLS tCLH tCH 50H A0 to A7 A9 to A16 A17toA23 DOUT tALStALH tALH tAR2 tRC tREA tWB WE CLE CE ALE RE BY/RY Column address DOUTDOUT tR tRR tDHtDS

512 M 512 M 1

: VIH or VIL tDHtDS 527 * Read Operation using 50H Command N: 0 to15 tCS tCLS tCLH tCH 01H A0 to A7 A9 to A16 A17toA23 DOUT tALStALH tALH tAR2 tRC tREA tWB WE CLE CE ALE RE BY/RY Column address DOUTDOUT tR tRR tDHtDS

256 M 256 M 1

: VIH or VIL tDHtDS 527 * Read Operation using 01H Command N: 0 to 255

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 12/34 Sequential Read (1) Timing Diagram Sequential Read (2) Timing Diagram A0 to A7 A9 to A16 A17toA23 tR WE CLE CE ALE RE BY/RY Column address N N N 1 N 2 527 52700H tR 0 1 2 Page address M Page M access Page M 1 access : VIH or VIL A0 to A7 A9 to A16 A17toA23 tR WE CLE CE ALE RE BY/RY Column address N 527 52701H tR 0 1 2 Page address M Page M access Page M 1 access : VIH or VIL I/O1 to I/O8 256 N 256 N 1

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 13/34 Sequential Read (3) Timing Diagram A0 to A7 A9 to A16 A17toA23 tR WE CLE CE ALE RE BY/RY Column address N 527 52750H tR Page address M Page M access Page M 1 access : VIH or VIL I/O1 to I/O8 512 N 512 N 1 512 N 2 512 513

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 14/34 Auto-Program Operation Timing Diagram Auto Block Erase Timing Diagram 60H A17toA23 WE CLE CE ALE RE BY/RY : VIH or VIL tCS tCLS tCLH tCLS A9 to A16 tDS tDH tALS : Do not input data while data is being output. tALH D0H 70H tWB tBERASE Busy Status Read command Erase Start command Auto Block Erase Setup command I/O1 to I/O8 Status output 80H A9 to A16 A17toA23 tDH WE CLE CE ALE RE BY/RY tPROG : VIH or VIL tCS tCLS tCLH tCH tCS tCLS A0 to A7 DIN0 Status output DIN 527DIN1 tWB 70H tDS tDS tDH tALS tALH tALH tALS 10H tDS tDH : Do not input data while data is being output. I/O1 to I/O8 tDS tDH

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 15/34 ID Read Operation Timing Diagram : VIH or VIL Device code tALEA WE I/O1 to I/O8 tDHtDS tCLS tCS tCLS tCH 90H Maker code CE CLE RE tCStCH tALHtALStALH tCEA 00 98H 73H tREAID Address input ALE tREAID

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 16/34 PIN FUNCTIONS The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs are configured as shown in Figure 1. Command Latch Enable: CLE The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE signal while CLE is High. Address Latch Enable: ALE The ALE signal is used to control loading of either address information or input data into the internal address/data register. Address information is latched on the rising edge of WE if ALE is High. Input data is latched if ALE is Low. Chip Enable: The device goes into a low-power Standby mode when CE goes High during a Read operation. The CE signal is ignored when device is in Busy state ( BY/RY L), such as during a Program or Erase operation, and will not enter Standby mode even if the CE input goes High. The CE signal must stay Low during the Read mode Busy state to ensure that memory array data is correctly transferred to the data register. Write Enable: The WE signal is used to control the acquisition of data from the I/O port. Read Enable: The RE signal controls serial data output. Data is available t REA after the falling edge of RE . The internal column address counter is also incremented (Address Address l) on this falling edge. I/O Port: I/O1 to 8 The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the device. I/O Port: I/O9 to 16 The I/O9 to 16 pins are used as a port for input/output data to and from the device. The I/O9 to 16 pins are low level(VIL) when address and command are asserted. Write Protect: The WP signal is used to protect the device from accidental programming or erasing. The internal voltage regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. Ready/Busy: The BY/RY output signal is used to indicate the operating condition of the device. The BY/RY signal is in Busy state ( BY/RY L) during the Program, Erase and Read operations and will return to Ready state ( BY/RY H) after completion of the operation. The output buffer for this signal is an open drain. CE WE RE WP BY/RY NC NC NC NC NC GND BY/RY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 Vss I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 NC NC V CCQ NC NC NC I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1 Vss Figure 1 pinout

ALE, CE , WE , RE and WP signals, as shown in Table 2. Table 2. Logic table Table 3. Command table (HEX) 01 command isn’t implemented by x16. Table 4 shows the operation states for Read mode. Table 4. Read mode operation states

16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte 527. This mode allows the sequential reading of pages without additional address input. the device continues to output the data from this address ** on each RE clock signal. Figure 5. Read mode (3) operation redundant memory cells, while A4~A7 are ignored.

RE clock after a 70H command input. The resulting information is outlined in Table 5. Table 5. Status output table An application example with multiple devices is shown in Figure 6. diagram, the Status Read function can be used to determine the status of each individual device. Figure 6. Status Read timing application example

the address and data have been input. The sequence of command, address and data input is shown below.

70 I/O

completion of the operation. Figure 7. Auto Page Program operation page on the rising edge of WE following input of the “10H” command.

60 D0 70

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 23/34 Reset The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally generated voltage is discharged to 0 volts and the device enters Wait state. The response to an “FFH” Reset command input during the various device operations is as follows: When a Reset (FFH) command is input during programming When a Reset (FFH) command is input during erasing When a Reset (FFH) command is input during Read operation When a Status Read command (70H) is input after a Reset When two or more Reset commands are input in succession Figure 12. BY/RY FF FF (3)(2)(1) The second command is invalid, but the third command is valid.FF FF FF Internal VPP 80 10 FF 00 BY/RY tRST (max 10 Ps) Figure 8. Internal erase voltage D0 FF 00 BY/RY tRST (max 500 Ps) Figure 9.

00 FF 00

tRST (max 6 Ps) Figure 10. Figure 11. FF 70 BY/RY I/O status: Pass/Fail o Pass Ready/Busy o Ready FF 70 BY/RY I/O status: Ready/Busy o Busy

The device contains ID codes which identify the device type and the manufacturer. Table 6. ID Codes read out by ID read command 90H Figure 13. ID Read timing For the specifications of the access times tREAID, tCR and tAR1 refer to the AC Characteristics.

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 28/34 (9) BY/RY : termination for the Ready/Busy pin ( BY/RY ) A pull-up resistor needs to be used for termination because the BY/RY buffer consists of an open drain circuit. This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value. VCCQ Device VSS R BY/RY CL tf Ready VCCQ tr Busy 1.5 Ps 1.0 Ps 0.5 Ps 0 1 K: 4 K:3 K:2 K: 15 ns 10 ns 5 ns tftr R tr tf VCCQ 1.8 V Ta 25°C CL 30 pF Figure 21. DIN

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 29/34 (10) Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming Disable Programming Enable Erasing Disable Erasing WP tWW (100 ns min) 80 10 WE BY/RY DIN WP tWW (100 ns min) 60 D0 WE BY/RY DIN WP tWW (100 ns min) 80 10 WE BY/RY DIN WP tWW (100 ns min) 60 D0 WE BY/RY DIN

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 31/34 (12) Several programming cycles on the same page (Partial Page Program) A page can be divided into up to 3 segments. Each segment can be programmed individually as follows: Data Pattern 3 Data Pattern 1 All 1s Figure 24. 1st programming 2nd programming 3rd programming Result Data Pattern 1 Data Pattern 3 Data Pattern 2 All 1s Data Pattern 2 All 1s Note: The input data for unprogrammed or previously programmed page segments must be “1” All 1s

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 33/34 (14) Failure phenomena for Program and Erase operations The device may fail during a Program or Erase operation. The following possible failure modes should be considered when implementing a highly reliable system. FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE Block Erase Failure Status Read after Erase o Block Replacement Page Programming Failure Status Read after Program o Block Replacement (1) Block Verify after Program o Retry Single Bit Programming Failure 1 o 0 (2) ECC x ECC: Error Correction Code x Block Replacement Program Erase When an error occurs in an Erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). (15) Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery is low. Power shoetage and/or power failure before write/erase operation is complete will cause loss of data and/or damage to data. When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, prevent further system accesses to Block A (by creating a bad block table or by using an another appropriate scheme). Block A Block B Error occurs Buffer memory Figure 28.

TC58DVM72A1FT00/ TC58DVM72F1FT00 TC58DAM72A1FT00/ TC58DAM72F1FT00 2003-01-24 34/34 Package Dimensions Unit : mm Weight: 0.53g (typ.)