TC58A040 | DigiCamel IC Datasheet

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TC58A040F TOSHIBA | Alldatasheet

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Technical content

TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS AMBIT (4M x 1BITS) CMOS AUDIO NAND E2PROM

DESCRIPTION

The TC58A040 is a 5-volt 4 Mbit NAND Electrically Erasable and Programmable Read Only Memory (NAND EEPROM) organized as 256 bits X 128 pages X 128 blocks. The device has a 256-bit static register which allows the program and read data to be transferred between the register and the memory cell array in 256-bit increments. The Erase operation is implemented in a single block unit (4 Kbytes). The TC58A040 is suitable for digital recording systems such as digital answering machines and personal digital recorders.

FEATURES

@ Organization @ Power supply Memory cell array 4MX1 Veco = 5 V + 10% Block size 4 Kbytes Cell array-Register 25 us. Serial Read Cycle 250 ns @ Mode . @ Operating current Read, Auto Program > Read (500 ns cycle) 5mA typ Auto Block Erase, Status Read Write 15mA typ © Mode control Erase 10 mA typ Serial input/output Standby 50 vA Command control e Package TC58A040F : SOP28 - P - 450 - 1.27 (Weight: 0.81 g typ) PIN ASSIGNMENT (TOP VIEW) PIN NAMES cs 4 25 FNC = 7 ne O18 21 FNC nc 9 20 INC Nc C10 19 FANc nc 18 FNC Ne (12 17 Fane Ne 13 16 ONC Ne C14 15 FIne

961001 EBA

@ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. Sine products described in this document are subject to foreign exchange and foreign trade control laws. The information contained herein is resented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1997-04-01 1/30

Charge pumps/Control gate drivers ] if D D e e $ 4Mbit memory cell array $ Lh e e r r . = ~ Interface/Control logic Ss SK ABSOLUTE MAXIMUM RATINGS SYMBOL RATING VALUE es storage Temperature 755 to 150 Operating Temperature CAPACITANCE *(Ta = 25°C, f = 1MHz) SYMBOL PARAMETER CONDITION UNIT a DD [cour Lute Torso Ps Tt Tr * This parameter is periodically sampled and is not tested for every component. 1997-04-01 2/30

(1) The number of valid blocks in the range Block 0 to Block 126 (2) is: a co Note 1: The TC58A040 occasionally contains unusable blocks. Refer to Application Note (8) toward the end of this document. Note 2: Block 127 is guaranteed to be good. DC RECOMMENDED OPERATING CONDITIONS Tsrmece [ean [we [| wo [war] es ee oe a * — 2V (pulse width S 20 ns) DC CHARACTERISTICS (Ta = 0° to 70°C, Vcc = 5V + 10%) a Pi [rennet areveve po Po esa ce onseav ove [fe fa | ere eer ere Fess [ese cron moet” [uae ts | ee ee ee re er cs ee re ee ee re Ce ee rs ee | vou | tow tevel output vortge — Lign=2ima T= To |v 9997-04-07 3/30

Serial Data Input: DI The DI pin is used for inputting commands and data. Commands and data are latched on the rising edge of SK. Serial Data Output: DO The DO pin is used for outputting status and data. Data is available tpp after the falling edge of SK. DO indicates the internal state except during data output. A low level indicates that the device is busy. A high level indicates that the device is ready. Chip Select: CS This signal enables the device. When this signal is high, the device ignores SK. This signal can be tied to ground when there is only one Audio-NAND device. The CS pin may be pulled high to reset the device. Serial Clock: SK This signal controls serial data input and output. Commands and data are latched on the rising edge of SK. Data is output on the falling edge of SK. ORGANIZATION The TC58A040F is a 4 Mbit device organized as 128 blocks of 16 master pages. A master page is further segmented into 8 pages as shown in the following figure. The Write and Read operations are executed on a page basis and Erase is executed on a block basis. Register (256 bits) 1 Block CI : - ELLE , Mebyes Page120| Page121] Page122| Page 123] Page 124] Page 125| Page126| Page127| (Page 120 to 127) 1 page = 256 bits 1 master page = 8 pages = 256 bytes 1 block = 16 master pages = 128 pages = 4096 bytes A page is the unit of reading and programming. A block is the unit of erasure. A master page is divided into 8 pages. These 8 pages are controlled by a common word line. 1997-04-01 5/30

The address is acquired through the DI pin using 16 consecutive clock cycles. The first 8 bits are the block address. The last 8 bits are the page address. a example: Page 100 in block 50 block page 00110010 01100100 (16-bit serial data) MsB LSB WRITE-ONCE BLOCK The TC58A040 has 128 blocks (blocks 0 to 127). The final block (block 127) has been set aside as a read-only block. Once data is written, this block cannot be erased. This block needs a special command for reading and writing. Block 127 may be used for storing system configuration information that cannot be lost. Block 0 to Block 127 Final block cannot be erased. (Block 127) COMMAND TABLE There are 12 commands in the TC58A040 command set. All operations are controlled by these commands, shown in the following table. Peerstaus | 1 | oom | oo | om _— [set address | 1 [coor] oa firemen [+ [wor oo | ao | read | tT corn oat Jwite Tt ooo oT tw [ose sen [1 | ono | oo | am | [oate sit ow [fon | oo |_| Jwrte enable | 1 | too oo] eo [wit osabie [1 [or | ooo | ean | [wives ick [1 | 110 | ooo | ron | [Read tast slock | 1 | toro Too 1997-04-01 6/30

The Set Address command defines which block and page of the memory an operation will operate on. The Set Address command is followed by two bytes, the first indicating the block number and the second indicating the page number. The Set Address command is usually followed by a Read or a Data Shift In command. Between the page address byte and the next command there is a delay of tsapp. The address that is selected remains the active address until a new Set Address or Increment command is given. Set address Block address Page address Read, Data Shift In tsapp Example: If inputting the 88H command, the MSB must be input first. sk OLS DI 1 0 0 0 1 0 0 0 MSB LSB Increment The Increment command automatically increments the page address. When the last page in a block is selected, if the Increment command is input, the address is set to 00H (Page 0) in the next block. However, when the last page in the last block (Block 126) is selected, if the Increment command is input, the address is indeterminate. Read The Read command transfers data from the selected page of the memory array into the on-chip buffer (256-bit shift register). The Read command is usually followed by a Data Shift Out command. There is a delay of tp between the Read command and the Data Shift Out command as the data is transferred from the memory array to the on-chip buffer. Write The Write command programs data from the on-chip buffer into the selected page of the memory array. A security code (55H) follows the Write command to ensure against accidental writes. Get Status may be used to ensure that the operation was successful. The Write command will be ignored if Write Disable has been set. Erase The Erase command erases a selected block. The Erase command is followed by the block address. A security code (55H) follows the block address to ensure against accidental erasure. The Get Status command may be used to verify that the operation was successful. The Erase command will be ignored if Write Disable has been set. Erase Block address Security code 1997-04-01 7/30

The Get Status command is used to output the status of the TC58A040. The eight status bits are defined as follows. a |} 2 | Write enable / Write disable Write enable : ‘1’ — Write disable : ‘0’ ee ee a ee The status is output LSB first. Bit 1 tells whether device is busy performing an operation (Write, Erase, etc) or is ready for a new command. Bit2 tells it previous Write or Erase operation just completed were performed successfully. Bit3 tells it the device is in a Write enabled or Write disabled mode. Get Status o Bit 1 Bit2 Bits Bits Data Shift In The Data Shift In command is used to shift data into the on-chip buffer. The number of bits sent into the buffer is determined by an 8-bit argument following the command. The Data Shift In command is usually used prior to the Write command. Number of bits Data shift in to shift in Bit1 Bitn (1) (*2) The value of (*1) is 1 less than the actual number of bits to be shifted in (*2). Example: Number of bits argument (*1) 00H = 00000000 1997-04-01 8/30

The data Shift Out command is used to shift data out of the on-chip buffer. The number of bits sent out of the buffer is determined by an 8-bit argument following the command. The Data Shift Out command is usually used after a Read command. Number of bits Data shift out to shift out (*1) Bit1 Bitn (*2) bo OF OO The value of (*1) is 1 less than the actual number of bits to be shifted out (*2). Example : [wonber orbs) ——SSSC*idC nse Write Disable The Write Disable command is used to prevent inadvertent writing or erasure. Once this command has been executed, no subsequent Write or Erase commands will be accepted. The Status Read operation (Get Status command) can be used to determine whether the device is in the Write Enable or Disable state. Write Enable The Write Enable command is used to cancel Write Disable mode. Read Last Block The Read Last Block command is used to read the contents of the final block (Block 127). The Set Address command and 2 address bytes are required to set the page address. The block address is automatically set to 127, so the first address byte is ignored. Write Last Block The Write Last Block command is used to program into the selected page in the final block (Block 127). Once data is written into the last block, it cannot be erased. A security code (55H) follows the Write Last Block command to ensure against accidental writes. 1997-04-01 9/30

The TC58A040 has separate input and output pins. Address, command and input data are input as serial data through DI. Status data and output data are output as serial data through DO. Input and output operations are as follows. (1) Address input Block address Page address O0000000 OO0000000 MsB LSB MSB LSB 8 bits 8 bits << prection of input (MB first) (2) Command input (3) Data input 00000000, 20000 CO Start MsB LsB Start 012 254 255 OP Code 256 bits data <——— Direction of input <_< Direction of input (4) Data output (5) Status data output 255 254 ccc 210 SS Re “1 or “O" Pass/Fail Direction of output (Bit 0 first) Unknown Write Enable/Disable Direction of output-———> (RB first) Register operation The TC58A040 has a 256-bit shift register on the chip. This register is used to transfer data to and from the memory cell array. The register operation is as follows: Input: 8-bit data input (new data shifts out oldest data) Initial register state [o] 1] 2] 3] wveneneeeneee [253 [254 ]255] State after inputting sbits [8] 9]10]-----[254]255|@|e/a|@|e|6|a|e]<— 92996608 Serial Input daté Output: 8-bit data output (register acts as a circular buffer) eran inpur eae Data is output again after 256 bits. 1997-04-01 10/30

synchronized to SK. This operation is shown in Figure 1.

0 CC) => Co)

Figure 1. Read operation diagram The set address command is input for every page read cycle.

0 CE) $C) — GD) Co)

The Increment command is used instead of applying the Set Address command.

0 C)—CoD—Go) =D GD

D0 becomes low and is held low during the Busy state.

The device state (Busy or Ready) can be output by executing the Status Read operation.

This operation outputs the device’s internal state by using the Get Status command. 8 clock pulses are necessary. register into the selected page in the memory array. This operation is shown in Figure 2.

1 CoG) 00) 000 COO 0D 5H)

Figure 2. Write operation diagram

Number of bits to shift in: 256 (#FFH) should be input. If the number of bits to shift in is less than 256 (#FFH), previous data will be written into the memory array. Previous data New input data 0 255 a ; Pp Previous data is written. The Write operation is executed page by page. When writing two or more consecutive pages, two methods are possible: + Write Mode (1) The Set Address command is input for every Page Write operation. Set Block Page Data Number of bits Security Address Address Address Shift In to shift in Write code

0 C9) CED} CON —$O + ODED

+ Write Mode (2) The Increment command is used instead of applying the Set Address command. Address set to page X + 1 Set Block Page Data Number of bits Security Increment Address Address Address Shift In _to shift in Write code Bit1 Bitn a ae cs ie ‘tsapp tproG 1997-04-01 13/30

Partial Page Write operation The TC58A040 allows a master page to be divided into a maximum of 50 segments with each page segment written individually as follows: Page! Page2 Page3 Page4 PageS Page6 Page7 Page8 Nae 78 Page Register. L\\ Npp = nt +n2 +3 +n4+n5 +n6 +n7 +n8 = 50 * n1 to n8: Number of partial programs in a page *Npp _: Number of partial programs in a master page The input data for unprogrammed or previously programmed page segments must be “1”. Example: Oa 256 bits Erase Operation The Erase operation is executed block by block. The Erase operation sequence is shown below. Block Security Erase Address code bo es tBERASE 1997-04-01 14/30

Read and Write operation for the final block (write-once block The final block (Block 127) has been set aside as a read-only block. Hence, the final block needs special commands for the Read and Write operations. Read Last Block The block address is ignored. set Block Page Data Number of bits Address Address Address Read Shift Out to shift out

0 CDC D>

The block address is ignored. Set Block Page Data Number of bits Security Address Address Address Shift In to shift in Write code Bit1 Bitn a i as i tsapp tproc 1997-04-01 15/30

an : tskL = y la a sc 2 tsku | R 0 ian PRO@OROAOOOR@aT p) Block address 2 Sy tg PDA NANNANIS, » Wl LIK XOK NIE NIE NENT, p) Page address Ny g téKL poe Note 1 tes a a a a & H H tsaod tor “ga OY DO BUSY GY, * Note 1: Refer to Application Note (7). Note: The above 4 timing diagrams are contiguous.

2), an : Ola Se On eS DO BUSY Y * Note 2: Refer to Application Note (7). TTT -47'?°97-04-01 17730

sY ‘ess — : DI YW), "yn YUN LE lll My Syl DANNANANINSL d Number of bits to shift out (OOH-FFH) ny ° a ] an x » 7 (Note 4) » MMMM" TTT“ 7'7797-04-01 18/30

a — : DI YY “ WM "0" [ss Mle Me [Tx MZ MZ» Wl bo oC SK 4 | — » "MTT TT TOOT «2197380

tse ISKH » la Ss eS KS RR PAD ANANANANARSL & r Y Y Yy Yy Yy Y yng KX K_XOK_XOK_XTK_ XT XK STK

2 Number of bits to shift in (QOH-FFH) 2

2 Data input (Note7)_

po Note 7: FFH input as the number of bits to shift in. Note 8: Refer to Applicaton Note (9). Note: The above 3 timing diagrams are contiguous. 1997-04-01 20/30

/ as : DI oll: “ YUNG WA “= Ws WD" Wa L,, la s ooo *«*VIVIVINVSI VIVIAN NT ee a a a DO BUSY GY

TOSHIBA. SSCS AD4OF Erase 1 YG*Q»GieO:GerOD.: BR Ra Zi, la ee x 2 tsk <>} 2 Qe locke accross ee ron a a ce oe a bie) BUSY WY, * Note 10: Refer to Applicaton Note (7). TTT 9957-04-07 22180

APPLICATION NOTES AND COMMENTS (1) Prohibition of unspecified commands The 12 operation commands are listed in the command table. Commands other than these specified commands are prohibited. Stored data may be corrupted if an unspecified command is entered during the command cycle. (2) Interruption by CS going high During the period when the TC58A040 is reading a page from the array (tp), writing a page to the array (tproG), or erasing a block (tgERASE) or setting address (tsapp), the operation will complete regardless of the state of CS. When the CS pin go high during busy, the DO pin is in high impedance. (3) Device reset The TC58A040 is reset whenever CS changes from low to high. The command register will be cleared at this point. The data register will continue to hold whatever data is in the register. To clear the data register, 32 bytes of “OOH” data must be input. CS does not affect operations as described in Application Note (2) above. (4) Write disable at power-up On power-up, the TC58A040 is set to Write Disable mode. This prevents any spurious writes to the device. To enable write operations, the Write Enable (EOH) command must be given. (5) Prohibition of extra clocks If an unexpected clock pulse is induced on the SK terminal by noise, the device may malfunction. Also, the device has no reset command. Therefore, noise must be controlled. (6) Prohibition of data output and data input in the same cycle Input and output operations in one cycle is prohibited. The following diagram shows an example. (a) (b) (©) Data output | Data input Data must not be input. / Data must be input in the next cycle’ (7) Busy state signal When the device is in the Busy state (when the TC58A040 reads a page from the array (tp), writes a page to the array (tproG), erases a block (tgERASE), or decodes an address (tsapp) ), the DO pin outputs a low level (Busy status). During this period operations, other than Status Read, are prohibited. If SK is clocked during this period, other than during a Status Read operation, the DI pin must be kept low. If SK is held high or low, the DI pin = “don’t care”. 1997-04-01 23/30

(8) Identification of bad blocks The TC58A040 may contain unusable blocks. Bad blocks must be identified by user software during initial operation. The figure below describes how to identify bad blocks. c : Checkerboard Pattern Pass ¢c : Inverse Checkerboard Pattern Blank Check: 1 Block Read (FFH) Note: Block 127 is intentionally excluded from this flow chart. No Yes fa Pass Erase Bad Pass Block

8 Page Fail

(9) End-of-operation signal When a Data Shift Out, Data Shift In, or Status Read operation finishes, the CS pin must go high or SK must stay low for at least 250.ns. This must occur before subsequent commands are input, such as Increment, Write Enable, or Write Disable. (Case 1) (Case 2) | tes cs cs 250 ns min sk 250 ns min J sk kt "| tes >H< don't care 20s min 1997-04-01 24/30

(10) Error in Program or Erase operation (failure of at Status Read) The device may fail during a Program or Erase operation due, for example, to the Write/Erase cycle limits being exceeded. The following system architecture will ensure high system reliability if a failure occurs: Program error occurs |_-—] a rr Block A Tf an error occurs in Block A, try to reprogram | | the data into another block, Block B, by loading =} from an external buffer. Then, prevent further system accesses to Block A (by creating a “bad block” table or some other appropriate scheme). b } “ae Erase When the error occurs after an Erase operation, prevent future accesses to this bad block (again by creating a table within the system or some other appropriate scheme). 1997-04-01 25/30

TC58A040 is a 4Mbit NAND E2PROM designed to provide the most cost effective solution for digital audio recording applications. For digital audio storage, the TC58A040 has been matched with DTAD CODEC LSI TC88411F. Applications that can benefit from this combination include digital answering machines and personal digital recorders. Customers can quickly bring to market systems capable of recording up to 15 minutes of audio on a single 4 Mbit device. Multiple TC58A040s can be used to extend the recording time. ce pe PAG bo T¢as411F TC58A040F DTAD CODEC LSI DATA TRANSFER RATE The data transfer rate of the TC58A040 is as follows: Fwinas a | araini | stato | oem | wom _| Pewetwuaszony |---| 700s 1997-04-01 26/30

SOP28—P—450—1.27 UNITS: mm 28 15 ; HHUHHEHHEEEEOE ) | ul e ») 3g 3 EG | oF = = HOP Hoogooeooeeoe ~] 1 14 19.0MAX 18.5+0.2 nN COs a Bas wo) o 170.1] $4 S 1,040.2 1997-04-01 30/30

Product Information

TC58A040 specifications and overview.

Summary

4 MBIT (4M x 1BITS) CMOS AUDIO NAND E2PROM

Description

4 MBIT (4M x 1BITS) CMOS AUDIO NAND E2PROM

Source title TC58A040 Datasheet(PDF) - Toshiba Semiconductor

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