TC581282A

TC581282AXB TOSHIBA | Alldatasheet

Document overview

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• PDF pages: 31

Technical content

• Power supply V CC = 2.7 V to 3.6 V
• Program/Erase Cycles 1E5 cycle (with ECC)
• Access time Cell array to register 25 µs max Serial Read Cycle 50 ns min
• Operating current Read (50 ns cycle) 10 mA typ. Program (avg.) 10 mA typ. Erase (avg.) 10 mA typ. Standby 100 µA
• Packageç P-TFBGA56-0710-0.80AZ (Weight: g typ.) TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 128-MBIT (16M × 8 BITS) CMOS NAND E2PROM

DESCRIPTION

The TC581282A is a single 3.3 V 128-Mbit (138,412,032) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E 2PROM) organized as 528 bytes × 32 pages × 1024 blocks. The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes × 32 pages). The TC581282A is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density non-volatile memory data storage.

FEATURES

• Organization Memory cell allay 528 × 32K × 8 Register 528 × 8 Page size 528 bytes Block size (16K + 512) bytes
• Modes Read, Reset, Auto Page Program Auto Block Erase, Status Read
• Mode control Serial input/output Command control PIN ASSIGNMENT (TOP VIEW) PIN NAMES 1 2 3 4 5 6 7 8 A NC NC B NC NC C NU CLE NU NU NU NU D NU ALE NU NU NU NU E WP WE NU NU NU GND F NU NU NU NU NU NU G NU NU NU NU BY/RY NU H CE I/O1 I/O3 NU NU NU J RE NU NU V CC I/O8 I/O7 K V SS I/O2 I/O4 I/O6 I/O5 NC L NC NC M NC NC
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage t o property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Gui de for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfun ction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this docume nt shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assume d by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from i ts use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice. 000707EBA1 I/O1 to I/O8 I/O port CE Chip enable WE Write enable RE Read enable CLE Command latch enable ALE Address latch enable WP Write protect BY/RY Ready/Busy GND Ground input VCC Power supply VSS Ground NU : Not used, NC : Not Connected

VCC Power Supply Voltage −0.6 to 4.6 V VIN Input Voltage −0.6 to 4.6 V VI/O Input/Output Voltage −0.6 V to VCC + 0.3 V (≤ 4.6 V) V PD Power Dissipation 0.3 W Tsolder Soldering Temperature (10s) 260 °C Tstg Storage Temperature −55 to 125 °C Topr Operating Temperature −40 to 85 °C CAPACITANCE *(Ta ==== 25°C, f ==== 1 MHz) SYMB0L PARAMETER CONDITION MIN MAX UNIT CIN Input V IN = 0 V  10 pF COUT Output V OUT = 0 V  10 pF * This parameter is periodically sampled and is not tested for every device. I/O Control circuit Status register Address register Command register Column buffer Column decoder Data register Sense amp Memory cell array Control HV generator Row address decoder Logic control BY/RY VCC I/O1 VSS I/O8 to WP CE CLE ALE WE RE BY/RY Row address buffer decoder

VALID BLOCKS (1) SYMBOL PARAMETER MIN TYP. MAX UNIT NVB Number of Valid Blocks 1004  1024 Blocks (1) The TC581282A occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document. RECOMMENDED DC OPERATING CONDITIONS SYMBOL PARAMETER MIN TYP. MAX UNIT VCC Power Supply Voltage 2.7 3.3 3.6 V VIH High Level input Voltage 2.0  VCC + 0.3 V VIL Low Level Input Voltage −0.3*  0.8 V * −2 V (pulse width lower than 20 ns) DC CHARACTERISTICS (Ta ==== −−−−40° to 85°C, VCC ==== 2.7 V to 3.6 V) SYMBOL PARAMETER CONDITION MIN TYP. MAX UNIT IIL Input Leakage Current V IN = 0 V to VCC   ±10 µA ILO Output Leakage Current V OUT = 0.4 V to VCC   ± 10 µA ICCO1 Operating Current (Serial Read) CE = VIL, IOUT = 0 mA, tcycle = 50 ns  10 30 mA ICCO3 Operating Current (Command Input) tcycle = 50 ns  10 30 mA ICCO4 Operating Current (Data Input) t cycle = 50 ns  10 30 mA ICCO5 Operating Current (Address Input) tcycle = 50 ns  10 30 mA ICCO7 Programming Current   10 30 mA ICCO8 Erasing Current   10 30 mA ICCS1 Standby Current CE = VIH, WP = 0 V/VCC   1 mA ICCS2 Standby Current CE = VCC − 0.2 V, WP = 0 V/VCC   100 µA VOH High Level Output Voltage I OH = −400 µA 2.4   V VOL Low Level Output Voltage I OL = 2.1 mA   0.4 V IOL ( BY/RY ) Output Current of BY/RY pin V OL = 0.4 V  8  mA

AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER MIN MAX UNIT NOTES tCLS CLE Setup Time 0  ns tCLH CLE Hold Time 10  ns tCS CE Setup Time 0  ns tCH CE Hold Time 10  ns tWP Write Pulse Width 25  ns tALS ALE Setup Time 0  ns tALH ALE Hold Time 10  ns tDS Data Setup Time 20  ns tDH Data Hold Time 10  ns tWC Write Cycle Time 50  ns tWH WE High Hold Time 15  ns tWW WP High to WE Low 100  ns tRR Ready to RE Falling Edge 20  ns tRP Read Pulse Width 35  ns tRC Read Cycle Time 50  ns tREA RE Access Time (Serial Data Access)  35 ns tCEA CE Access Time (Serial Data Access)  45 ns tREAID RE Access Time (ID Read)  35 ns tOH Data Output Hold Time 10  ns tRHZ RE High to Output High Impedance  30 ns tCHZ CE High to Output High Impedance  20 ns tREH RE High Hold Time 15  ns tIR Output-High-impedance-to- RE Falling Edge 0  ns tRSTO RE Access Time (Status Read)  35 ns tCSTO CE Access Time (Status Read)  45 ns tRHW RE High to WE Low 0  ns tWHC WE High to CE Low 30  ns tWHR WE High to RE Low 30  ns tAR1 ALE Low to RE Low (ID Read) 100  ns tCR CE Low to RE Low (ID Read) 100  ns tR Memory Cell Array to Starting Address  25 µs tWB WE High to Busy  200 ns tAR2 ALE Low to RE Low (Read Cycle) 50  ns tRST Device Reset Time (Read/Program/Erase)  6/10/500 µs AC TEST CONDITIONS PARAMETER CONDITION Input level 2.4 V, 0.4 V Input pulse rise and fall time 3 ns Input comparison level 1.5 V, 1.5 V Output data comparison level 1.5 V, 1.5 V Output load CL (100 pF) + 1 TTL

PROGRAMMING AND ERASING CHARACTERISTICS (Ta ==== −−−−40° to 85°C, VCC ==== 2.7 V to 3.6 V) SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES tPROG Programming Time  200 to 300 1000 µs N Number of Programming Cycles on Same Page   3 (1) tBERASE Block Erasing Time  2 10 ms (1): Refer to Application Note (12) toward the end of this document.

Latch Timing Diagram for Command/Address/Data Command Input Cycle Timing Diagram CLE ALE CE RE WE Hold Time tDH Setup Time tDS I/O1 to I/O8 : VIH or VIL tCS tDH tDS tALS tALH tWP tCLS tCH tCLH : VIH or VIL CE CLE WE ALE I/O1 to I /O8

Address Input Cycle Timing Diagram Data Input Cycle Timing Diagram : VIH or VIL WE tWP tWP tWH tWP tALS tWC tDH tDS DIN0 DIN1 tCLH tCH ALE CLE CE I/O1 to I/O8 DIN 527 tDH tDS tDH tDS tCH tCS tCS tDH tDS : VIH or VIL tDH tDS tCLS CLE tALS tWP tALH tWH tWP tWH tWP A0 to A7 tDH tDS A9 to A16 A17 to A23 tCS tWC tCS CE WE ALE I/O1 to I/O8 tCH tCH

Serial Read Cycle Timing Diagram Status Read Cycle Timing Diagram tWHR WE tDH tDS tCLS tCLS tCS tCLH tCH tWP Status output 70H* tWHC tCSTO tIR tRSTO tRHZ tCHZ CE CLE RE BY/RY I/O1 to I /O8 : VIH or VIL tOH * 70H represents the hexadecimal number tREH tCHZ CE tRHZ tREA tRC tRR tRHZ tREA tRHZ tREA RE BY/RY I/O1 to I/O8 tOH tOH tOH tRP tRP tRP tCEA tCH

Read Cycle (1) Timing Diagram Read Cycle (1) Timing Diagram: When Interrupted by CE tCS tCLS tCLH tCH 00H A0 to A7 A9 to A16 A17toA23 DOUT N DOUT N + 1 tDH tDS tWC tALS tALH tALH tR tAR2 tRR tRC tREA tWB tCHZ WE CLE CE ALE RE BY/RY Column address DOUT N + 2 tRHZ : VIH or VIL I/O1 to I/O8 tDH tDS tDH tDS tDH tDS tOH * Read Operation using 00H Command N: 0 to 255 I/O1 to I/O8 tCS tCLS tCLH tCH 00H A0 to A7 A9 to A16 A17toA23 DOUT N DOUT N + 1 tDH tDS tWC tALS tALH tALH tR tAR2 tRR tRC tREA tWB WE CLE CE ALE RE BY/RY : VIH or VIL tDH tDS tDH tDS tDH tDS DOUT N + 2 Column address DOUT 527 * Read Operation using 00H Command N: 0 to 255

Read Cycle (2) Timing Diagram Read Cycle (3) Timing Diagram tCS tCLS tCLH tCH 50H A0 to A7 A9 to A16 A17toA23 DOUT tALS tALH tALH tAR2 tRC tREA tWB WE CLE CE ALE RE BY/RY Column address DOUT DOUT tR tRR tDH tDS 512 + M 512 + M + 1 I/O1 to I/O8 : VIH or VIL tDH tDS 527 * Read Operation using 50H Command N: 0 to15 tCS tCLS tCLH tCH 01H A0 to A7 A9 to A16 A17toA23 DOUT tALS tALH tALH tAR2 tRC tREA tWB WE CLE CE ALE RE BY/RY Column address DOUT DOUT tR tRR tDH tDS 256 + M 256 + M + 1 I/O1 to I/O8 : VIH or VIL tDH tDS 527 * Read Operation using 01H Command N: 0 to 255

Auto-Program Operation Timing Diagram Auto Block Erase Timing Diagram 60H A17toA23 WE CLE CE ALE RE BY/RY : VIH or VIL tCS tCLS tCLH tCLS A9 to A16 tDS tDH tALS : Do not input data while data is being output. tALH D0H 70H tWB tBERASE Busy Status Read command Erase Start command Auto Block Erase Setup command I/O1 to I/O8 Status output 80H A9 to A16 A17toA23 tDH WE CLE CE ALE RE BY/RY tPROG : VIH or VIL tCS tCLS tCLH tCH tCS tCLS A0 to A7 DIN0 Status output DIN

527 DIN1

: Do not input data while data is being output. I/O1 to I/O8 tDS tDH

ID Read Operation Timing Diagram : VIH or VIL Device code tAR1 WE I/O1 to I /O8 tDH tDS tCLS tCS tCLS tCH 90H Maker code CE CLE RE tCS tCH tALH tALS tALH tCR 00 98H 73H tREAID Address input ALE tREAID

The device is a serial access memory which utilizes time-sharing input of address information. The device pin-outs are configured as shown in Figure 1. Command Latch Enable: CLE The CLE input signal is used to control loading of the operation mode command into the internal command register. The command is latched into the command register from the I/O port on the rising edge of the WE signal while CLE is High. Address Latch Enable: ALE The ALE signal is used to control loading of either address information or input data into the internal address/data register. Address information is latched on the rising edge of WE if ALE is High. Input data is latched if ALE is Low. Chip Enable: The device goes into a low-power Standby mode when CE goes High during a wait state. The CE signal is ignored when device is in Busy state ( BY/RY = L), such as during a Program or Erase or Read operation, and will not enter Standby mode even if the CE input goes High.. Write Enable: The WE signal is used to control the acquisition of data from the I/O port. Read Enable: The RE signal controls serial data output. Data is available t REA after the falling edge of RE . The internal column address counter is also incremented (Address = Address + l) on this falling edge. I/O Port: I/O1 to 8 The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from the device. Write Protect: The WP signal is used to protect the device from accidental programming or erasing. The internal voltage regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off sequence when input signals are invalid. Ready/Busy: The BY/RY output signal is used to indicate the operating condition of the device. The BY/RY signal is in Busy state ( BY/RY = L) during the Program, Erase and Read operations and will return to Ready state ( BY/RY = H) after completion of the operation. The output buffer for this signal is an open drain. 1 2 3 4 5 6 7 8 A NC NC B NC NC C NU CLE NU NU NU NU D NU ALE NU NU NU NU E WP WE NU NU NU GND F NU NU NU NU NU NU G NU NU NU NU BY/RY NU H CE I/O1 I/O3 NU NU NU J RE NU NU V CC I/O8 I/O7 K V SS I/O2 I/O4 I/O6 I/O5 NC L NC NC M NC NC CE WE RE WP BY/RY Figure1. Pinout

The Program operation works on page units while the Erase operation works on block units. consecutive clock cycles, as shown in Table 1. Table 1. Addressing *: A8 is automatically set to Low or High by a 00H command or a 01H command. *: I/O8 must be set to Low in the third cycle. CE , WE , RE and WP signals, as shown in Table 2. Table 2. Logic table Figure 2. Schematic Cell Layout

Table 3. Command table (HEX) Table 4 shows the operation states for Read mode. Table 4. Read mode operation states

timing details and the block diagram. Figure 3. Read mode (1) operation

527 A data transfer operation from the cell array to the registe r

Busy state during this transfer period. After the transfer period the device returns to Ready state. from the start pointer designated in the address input cycle. after column address 256, use Read mode (2). Figure 4. Read mode (2) operation

16-byte redundancy area of the page. The start pointer is therefore set to a value between byte 512 and byte 527. Figure 5. Read mode (3) operation redundant memory cells, while A4~A7 are ignored.

RE clock after a 70H command input. The resulting information is outlined in Table 5. Table 5. Status output table An application example with multiple devices is shown in Figure 6. diagram, the Status Read function can be used to determine the status of each individual device. Figure 6. Status Read timing application example

the address and data have been input. The sequence of command, address and data input is shown below.

70 I/O

completion of the operation. Figure 7. Auto Page Program operation page on the rising edge of WE following input of the “10H” command.

60 D0 70

The Reset mode stops all operations. For example, in the case of a Program or Erase operation the internally generated voltage is discharged to 0 volts and the device enters Wait state. The response to an “FFH” Reset command input during the various device operations is as follows: When a Reset (FFH) command is input during programming When a Reset (FFH) command is input during erasing When a Reset (FFH) command is input during Read operation When a Status Read command (70H) is input after a Reset When two or more Reset commands are input in succession Figure 12. BY/RY FF FF (3) (2) (1) The second command is invalid, but the third command is valid.FF FF FF Internal VPP 80 10 FF 00 BY/RY tRST (max 10 µs) Figure 8. Internal erase voltage D0 FF 00 BY/RY tRST (max 500 µs) Figure 9.

00 FF 00

tRST (max 6 µs) Figure 10. Figure 11. FF 70 BY/RY I/O status: Pass/Fail → Pass Ready/Busy → Ready FF 70 BY/RY I/O status: Ready/Busy → Busy

The TC581282A contains ID codes which identify the device type and the manufacturer. Table 6. ID Codes read out by ID read command 90H Figure 13. ID Read timing For the specifications of the access times tREAID, tCR and tAR1 refer to the AC Characteristics.

(9) BY/RY : termination for the Ready/Busy pin ( BY/RY ) A pull-up resistor needs to be used for termination because the BY/RY buffer consists of an open drain circuit. This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value. VCC VCC Device VSS R BY/RY CL tf Ready

3.0 V VCC

1.0 V tr 3.0 V

1.0 VBusy

1.5 µs 1.0 µs 0.5 µs 0 1 KΩ 4 KΩ3 KΩ2 KΩ 15 ns 10 ns 5 ns tf tr R tr tf VCC = 3.3 V Ta = 25°C CL = 100 pF Figure 21.

(10) Note regarding the WP signal The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming Disable Programming Enable Erasing Disable Erasing WP tWW (100 ns min) 80 10 WE BY/RY DIN WP tWW (100 ns min) 60 D0 WE BY/RY DIN WP tWW (100 ns min) 80 10 WE BY/RY DIN WP tWW (100 ns min) 60 D0 WE BY/RY DIN

(12) Several programming cycles on the same page (Partial Page Program) A page can be divided into up to 3 segments. Each segment can be programmed individually as follows: Data Pattern 3 Data Pattern 1 All 1s Figure 24. 1st programming 2nd programming 3rd programming Result Data Pattern 1 Data Pattern 3 Data Pattern 2 All 1s Data Pattern 2 All 1s Note: The input data for unprogrammed or previously programmed page segments must be “1” (i.e. the inputs for all page bytes outside the segment which is to be programmed should be set to all “1”). All 1s

(14) Failure phenomena for Program and Erase operations The device may fail during a Program or Erase operation. The following possible failure modes should be considered when implementing a highly reliable system. FAILURE MODE DETECTION AND COUNTERMEASURE SEQUENCE Block Erase Failure Status Read after Erase → Block Replacement Page Programming Failure Status Read after Program → Block Replacement (1) Block Verify after Program → Retry Single Bit Programming Failure 1 → 0 (2) ECC

• ECC: Error Correction Code
• Block Replacement Program Erase When an error occurs in an Erase operation, prevent future accesses to this bad block (again by creating a table within the system or by using another appropriate scheme). When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, prevent further system accesses to Block A (b y creating a bad block table or by using a n another appropriate scheme). Block A Block B Error occurs Buffer memory Figure 28.

Unit : mm Weight: g (typ.)