TC57256D-70 | DigiCamel IC Datasheet

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TC57256D-85 ETC1 | Alldatasheet

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ie oe Se 7) Ca7H2s5eD-70 = ee ee es :7H956D-8: 24 32,768 WORD x 8 BIT CMOS UV ERASABLE AND ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY

DESCRIPTION

The TCSYH256D is a 32,768 word x 8 bit CMOS ultraviolet light erasable and electrically programmable read only memory. For read operation, the TCS7H256D's access time is 70ns, and the TCS7H256D operates from a single 5-volt power supply and has low power standby mode which reduces the power dissipation without increasing access time. The standby mode is achieved by applying a TTL-high level signal to the CE input. Advanced CMOS technology reduces the maximum active current to 50mA/14.2MHz and stand- by current to 100uA. For program operation, the programming is achieved by using the high speed programming mode. For program operation, the programming is achieved by . using high speed programming mode. ‘TC57H256D is fabricated with the CMOS technology a and the N-channel silicon double layer gate MOS technology. = FEATURES + Full static operation + Peripheral circuit: CMOS + High speed programming mode + Memory cell : N+MOS + Inputs and outputs TIL compatible [-70 [-85 | + Pin compatible with ROM TC53257P, 'TMM23256P, aresi vi 79M27256AD and 1C57256AD cc ES + Standard 28 pin DIP cerdip package [tacc | 70ns] 85ns| + Single 5V power supply BLOCK DIAGRAM PIN CONNECTION] (TOP VIEW) Vgp GND Vcc 00 O1 02 08 O4 05 06 07 Vpp qt 28 Vp tEO a7ds 26fais cE asda 25 DAS A0 6 asgs5 24 pas Alo COLUMN a4ge 23D All 4300 2 DECODER a3q7 22 DOE 404 2 a2gs 21a10 ASO 3 alg 2 pce A6 0 aod 10 1907 Tod 8 ROW BMEORY CELL ood 18 B06 90, 2 as oi giz 17 Bos A190 © 3 DECODER 32,7 68x8bits 0213 16 Dos ANS GnpDg M4 15 P03 A130 Aldo PIN NAMES: MODE SELECTION Aadcous Topate —|[—— Fin | CE] OEY FLT oo 95 00% 07 [Outputs (Inputs) pee ent Q) | (28) 1023, 15029! | CE —|chip Enable Input a [Data Out | 5 : Tarz foutput Deselect | * |x | High Impedance |\\°1¥° [OE [Output Enable Input Progran Supply tandby [a [= | [High Impedance |Standby| Voltage Program| & OH |izsvY ev [Data In Veo Supply Voltage ||Program Inhibit High Impedance |Active Veo 2) [_cnp [Ground —=—S—S—Ssd * H or L 1): HIGH SPEED PROGRAM MODE I 2); HIGH SPEED PROGRAM MODE It A25

TC57H256D—70 TC57H256D-85 ER" A.C. CHARACTERISTICS fae rence fee So | aga [nsarons bocess Tine | OT [= fs foe | A Heo [oe se ovepur valid yO | OT | [tori cE co ovepot in ighz [Oem | 0 | 30 fo [30 [os | [tora [oe co output to wighe | Cem | o [30 | o | 30 [as | {cor —octpue Data Wold Tine [ev [5 | - | s [= [| A.C. TEST CONDITIONS om + Output Load : 1 TTL Gate and C,=100pF + Input Pulse Rise and Fall Times: 10ns Max. + Input Pulse Levels + 0.45V% 2.40 + Timing Measurement Reference Level: Inputs 0.8V and 2.2V, Outputs 0.8V and 2.0V CAPACITANCE ¥*(Ta=25°C, f=1MHz) [snot _[paraveren | west ovorniow [ wan. [ wv | wax. [oe | [ern —[fapae cepacivance | vneov | - | « | 6 [or | [our [outrue caracteance | vowreov_ - [8 [i [oF | * This parameter is periodically sampled and is not 100% tested. TIMING WAVEFORMS A0~Ald j tou, = ce 7, % LLL ‘DPI _ toe 17 * LUM tacc tpr2 | rp Oa KTP A-27

TC57H256D—70 TC57H256D-85 D.C. RECOMMENDED OPERATING CONDITIONS [samo | _resweren [ws [a [ako] [via [Tapoe High Woitage ip 2.2 | - | von | v | [wre [input tow Voltage [03 | - | oe fv | [veo |Woc Paver Supply voltage | 3.73| &0 | 6.25 | v [ver [vor Fover Supply Voltage [2.0 Juz.5 [13.0 |v] [swear | _ramweren [west emvorrion [win | P_[ wox. [ Om] [tur [fopue Gorrent | Yaw0~vor | - | - [#10 | wa | [Vor Jouspue Wish voieage | Tog -f0Qa [eat - | - [v | [You —Joutput tow voltage | tous2.imn | - | - [oa | v | [ee |vec Suppiy currene | +t = ‘| - | «| = | [tapi ver Stppty current | wpiscov [== so ft] [sewso: [_ranaweren [vest conprrion [ wan. [ 1¥e. | wax | Wit] [ess [Address setup Tine | 2 | | = [oe | [ eat [address Wold Tine | i 2 Po | [fees [GE Seep Tie oP oe | [foe [ee Rota Time PP ie | [foes [oe setup tine S| i pe | [tos [oace Setup tise S| i 2p [fox [asta woud Time P| [ees |igp Seewp tine SPP [ Fes “|vce Setup tine | id 2 | fe | [feu [rnsesai progean Poise wiaeh | CErvyy, ObVyg 0.05 | a [05 | ww | [ font lovernrogran Pulse width [voce [2.85 | 9 pa.75 |e | [Poe JOE co Ouepoe vatid ‘| vyq |= |= dao] [fore [ot co cuepue in waged [evry [= = 90 J A.C. TEST CONDITIONS + Output Load : 1 TTL Gate and Cy(100pF) + Input Pulse Rise and Fall Times : 1Ons Max. + Input Pulse Levels : 0.45VV2.4V + Timing Measurement Reference Level: Input 0.8V and 2.2V, Output 0.8V and 2.0V Note 1: The length of the overprogram pulse may vary as a function of the counter value X. A-28

TIMING WAVEFORMS (PROGRAM) HIGH SPEED PROGRAM MODE I (Vcc=6V+0.25V, Vpp=12.5V+0.5V) HIGH SPEED PROGRAM MODE Il (Vcc=6.25V+0.25V, Vpp=12.5V+0.5V) tas —— ne ERK KR RSREED = = OPW, raserererenererttst SP /) con) EEE sees | toes, DEP | 4 : ple wt Coovsnae 4 Vpp - : on ee Vee tyes PROGRAM PROGRAM VERIFY Note 1. Vcc must be applied simultaneously or before Vpp and cut off simultaneously or after Vpp. 2. Removing the device from socket and setting the device in socket with Vpp"12.5V(12.75V) may cause permanent damage to the device. 3. The Vpp supply voltage is permitted up to 14V for program operation. So the voltage over 14V should not be applied to the Vpp terminal. When the switching pulse voltage is applied to the Vpp terminal, the overshoot voltage of its pulse should not be exceeded 14V. A-30

The TC57H256D's erasure is achieved by applying shortwave ultraviolet light which has a wavelength of 2537A (Angstroms) to the chip through the transparent window. ‘The integrated dose (ultraviolet light intensity (w/em#] 4x1 exposure time (sec.]) for erasure should be a minimum of 15 (w-sec/cm?). When the Toshiba sterilizing lamp GL-15 is used and the device is exposed at a dis- tance of lem from the lamp surface, the erasure will be achieved within 60 minutes. And using commercial lamps whose ultraviolet light intensity is a 12000 [uw/cm?] will reduce the exposure time to about 20 minutes. (In this case, the integrated does is 12000 [uw/em?] x (20x60) [sec] = 15 [w-sec/cm*].) The TC57H256D's erasure begins to occur when exposed to light with wavelength shorter than 4OOOR. The sunlight and the fluorescent lamps will include 3000 ~40G0A wave~ length components. Therefore when used under such lighting for extended periods of ; time, the opaque seals-Toshiba EPROM Protect Seal AC901-are available. i OPERATION INFORMATION . The TC57H256D's six operation modes are listed in the following table. Mode selection can be achived by applying TTL level signal to all inputs. PIN NAMES (NUMBER) | CE | DE | Vpp | Vcc 00 “07 (Ta=0 70°C) Output Deselect | * | ux | Sv | SV | High Impedance Standby [a | « | High Impedance | Standby

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ress) ND : (1a=2525°C) Program tahibic | a | w_|'*"°>\\| 5) [High Impedance | Active Note: H; Vyq3 L; Vpps *s Vin or Vins 1): HIGH SPEED PROGRAM MODE I, 2): HIGH SPEED PROGRAM MODE I READ MODE The TC57H256D has two control functions. The chip enable (CE) controls the operation power and should be used for device selection. The output enable (OE) control the output buffers, independent of device selection. Assuming that CE=OE=VzL, the output data is valid at the outputs after address access time from stabilizing of all addresses. The CE to output valid (tcg) is equal to the address access time (tacc) + Assuming that CE=Vz_ and all addresses are valid, the output data is valid at the outputs after tog from the falling edge of OE. OUTPUT DESELECT MODE] Assuming that CE=Vyq or OE=Vzy, the outputs will be in a high impedance state. So two or more TC57H256D's can be connected together on a common bus line. When CE is decoded for device selection, all deselected devices are in low power standby mode. ASI

The TC57H256D has a low power standby mode controlled by the CE signal. By applying a high level to the CE input, the TCS7H256D is placed in the standby mode which reduce the operating current to 100uA by applying MOS-high level (Vcc) and then the outputs are in a high impedance state, independent of the O£ inputs. PROGRAM MODE Initially, when received by customers, all bits of the TC57H256D are in the "1" state which is erased state. Therefore the program operation is to introduce "O's" data into the desired bit locations by electrically programming. _ The TCS7H256D is in the programming mode when the Vpp input is at 12.5V and CE is at TIL-Low under OE=Vrq- The TCS7H256D can be programmed any location at any time either individually, sequentially, or at random. PROGRAM VERIFY MODE The verify mode is to check that desired data is correctly programmed on the programmed bits. _ The verify: is accomplished with OE at Vzy. PROGRAM INHIBIT MODE Under the condition that the program voltage (+12.5V or 12.75V) is applied to Vpp terminal, a high level CE input inhibits the TC57H256D from being programmed. Programming of two or more TC57H256D's in parallel with different data is easily accomplished. That is, all inputs except for CE and OE may be commonly connected, and a TTL low level program pulse is applied to the CE of the desired device only and TTL high level signal is applied to the other devices. HIGH SPEED PROGRAM MODE I The program time can be greatly decreased by using this high speed programming mode. The device is set up in the high speed programming mode when the programming voltage (+12.5V) is applied to the Vpp terminal with Vcc=6V. The programming is achieved by applying a single TTL low level lms pulse to the CE input after addresses and data are stable. Then the programmed data is verified by using Progam Verify Mode. If the programmed data is not correct, another program pulse of Ims is applied and then the programmed data is verified. This should be repeated until the program operates correctly (max. 25 times). After correctly programming the selected address, the additional program pulse with width of 3 times more than that needed for initial programming is applied. When programming has been completed, the data in all addresses should be verified with Voc=Vpp=5V, A-32

ADDRESS = START ADDRESS NO 4 ADDRESS= OVERPROGRAM 3X PULSES OF 1 msec NEXT ADDRESS OR ONE PULSE OF 3X msec DURATION So YES Veo =3.0¥ Vpp = 5.0V READ NG Aut BYTE C rain) OK A-33,

TC57H256D—70 NN HIGH SPEED PROGRAM MODE I The device is set up in the high speed programming mode when the programming voltage (+12.75V) is applied to the Vpp terminal with V¢cn6.25V. The programming is achieved by applying a single TTL low level 0.1ms pulse the CE input after addresses and data.are stable. Then the programmed data is verified by using Program Verify Mode. If the programmed data is not correct, another program pulse of 0.lms is applied and then programmed data is verified. This should be repeated until the program operates correctly (max. 25 times). When programming has been completed, the data in all addresses should be verified with Voc=Vpp=5V. A34

TC57H256D-—70 TC57H256D-85 co HIGH SPEED PROGRAM MODE I FLOW CHART Voc = 6.2540.25V Vpp =12.75£0.25¥ = START ADDRESS aie ADDRESS = NEXT ADDRESS Yoo = 5¥ Vpp = 5V Ok Car) ASS

Electric signature mode allows to read out a code from TCS7H256D which identifies its manufacturer and device type. The programming equipment may read out manufacturer coce and device code from TC57H256D by using this mode before program operation and automatically set program voltage (Vpp) and algorithm. Electric Signature mode is set up when 12V is applied to address line A9 and the rest of address lines are set to V,;, in read operation. Date output in this con- dition is manufacturer code. Device code is identified when address AO is set to Vzq- These two codes possess an odd parity with the parity bit of MSB (07). The following table shows electric signature of TCS7H256D. AO 07 06 05 04 03 02 o1 00 HEX. fice oie fete fa Pefolel= fel: fs] Notes: A9=12V+0.5V AlvA8, ALOVAL4, CE, OE=Vyz, A336

‘Unit : mm aonlr 8 @7.A1TYP shits ART aa 1Le0P,| i H | 13401 | case o1 2 * er ean A-37

Product Information

TC57256D-70 specifications and overview.

Summary

32,768 WORD x 8 BIT UV ERASABLE AND ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY

Description

32,768 WORD x 8 BIT UV ERASABLE AND ELECTRICALLY PROGRAMMABLE READ ONLY MEMORY

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