TC551001BFTL

TC551001BPL_V01 TOSHIBA | Alldatasheet

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TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT INTEGRATED CIRCUIT 7C551001 BPL/BFL/BFTL/BTRL- 70 7TC551001 BPL/ BFL/ BFTL/BTRL- 85 TOSHIBA 551001 BPL/ BFL/BFTL/BTRL- 10 TECHNICAL DATA SILICON GATE CMOS 131,072-WORD BY 8-BIT STATIC RAM

DESCRIPTION

The TC551001BPL/BFL/BFTL/BTRL is a 1,048,576-bit static random access memory (SRAM) organized as 131,072 words by 8 bits. Fabricated using Toshiba’s CMOS Silicon gate process technology, this device operates from a single 5 V + 10% power supply. Advanced circuit technology provides both high speed and low power at an operating current of 5 mA/MHz (typ) and a minimum cycle time of 70 ns. It is automatically placed in low-power mode at 2 A standby current (typ) when chip enable (CE1) is asserted high or (CE2) is asserted low. There are three control inputs. CE1 and CE2 are used to select the device and for data retention control, and output enable (OE) provides fast memory access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. The TC551001BPL/BFL/ BFTL/BTRL is available in a standard plastic 32-pin dual-in-line package (DIP), plastic 32-pin small-outline package (SOP) and norma] and reverse pinout plastic 32-pin thin-small-outline package (TSOP).

FEATURES

© Low-power dissipation © Access Times (maximum): Operating: 27.5 mW/MHz (typical) . nr © Standby current of 100 A (maximum) P70] to © Single power supply voltage of 5 V + 10% [Access Time | _—70ns_ | 85ns_ | 100ns__ | © Power down features using CEI and CE2. [CET Access Time | 70ns | 85ns_ | 100ns | © Data retention supply voltage of 2 to 5.5 V [Ez Access Time | 70ns_ | 85ms_ | 100ns_ | @ Direct TTL compatibility for all inputs and LOE_Access Time | __35ns_[_a5ns_ [50 ns_ outputs ® Packages: DIP32-P-600 (BPL) (Weight: 4.45 g typ) SOP32-P-525 (BFL) (Weight: 1.04 g typ) TSOP32-P-0820(BFTL) (Weight: 0.34 g typ) TSOP32-P-0820A (BTRL) (Weight: 0.34 g typ) PIN ASSIGNMENT (TOP VIEW) © 32 PIN DIP & SOP © 32_ PIN TSOP nei 3210) Vop (Normal pinout) (Reverse pinout) ately 2 318) als IAAT TTT Ata 3 3010 cEe2 16 1 1 16 Ad 4 2900 Rw avs 280 a13 a6Q6 270 as asQ7 260 ao as 2500 ait a3Q9 240 OF a2 M10 2300 Ato aiqi 2210 CEI ao 12 21) vos vol 13 20K) vo7 vo2Q)14 1910 vo6 vo3Q 15 181) vos 75 17 32] 32 17| GnOrtts vos HNL OOOH PIN NAMES ECA ES ENED ET in Name Ji] As [As [Ava] RW] CED] Asoo] NC [Ave] Ave| Ara] Ay [As] As] Aal [oF [ouput enabie WF sino ]7] 18] 19] 20] 21 [22 | 25 | 26 [25 [26 | 27 | 28 [29 [30] 31] 32] Pinniame as [Ass [Ao v0 702]v03|no|v04v03|706]r07|v08 een] | Gnd [Ground © The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TC551001BPL—1 TOSHIBA CORPORATION for any Infringements of intelectual property or other righ of the thied partes which may result from is we ~ "No cen 's granted by implication or otherwise under ony inelectcal property or other rights of TOSHIBA CORORATION others to) 1996 - 09 - 02 @ These TOSHHA products are intended for se in general commercial applications (efice equipment, communication equipment, measuring ‘Sure ckraondnary nigh ay andr rele, and n'Squpment which may ioe Ie twrestening ofa aplston, Wes Pat TOSHIBA CORPORATION ‘ot limited to such uses a8 atoms energy contol alane of spaceship instrumentation, arate signals, medal Instrumentation, combustion Control, all types of sefety dovces, ete TOSMIBA cannot aecept and hereby dacaims laity for any damage ahlen may occu Ia cave the ‘TOSHIBA products are used in such equipment oc applications without prior consultation sith TOSHIBA

INTEGRATED CIRCUIT TC551001 BPL/BFL/BFTL/BTRL- 70

7551001 BPL / BFL /BFTL/BTRL- 85

TOSHIBA 7C551001 BPL/BFL/BFTL/BTRL- 10 TECHNICAL DATA BLOCK DIAGRAM CE ge EL] tw As oye is MEMORY CELL © GND Als B= ae 3c ARRAY Rigo 4) |< |/<91) 1024 x 128 x 8 Algo 3s ae au (1048576) f Al6° te ocr z ry ay E s oor zsl| § | pe vos HHT Iss R R BUFFER 4 ADATAZ AZ AAAS AB OE © pe we TR} CEI — ce CE2 o-f>0 OPERATION MODE ed a Pwie ew tT Outputs Disabled a stand ee rte andby Pox PT ign 2 tos Note: x = don’tcare. H = logic high. L = logic low. ABSOLUTE MAXIMUM RATINGS |r| Power Dissipation | tomes | lw Soldering Temperature (105) * — 3.0 Vwhen measured at a pulse width of 50 ns ** SOP TC551001BPL—2 1996 - 09-02 TOSHIBA CORPORATION

INTEGRATED CIRCUIT TC551001 BPL/BFL/BFTL/BTRL- 70 TC551001 BPL/BFL/BFTL/BTRL- 85 TOSHIBA 7C551001 BPL/BFL/BFTL/BTRL- 10 TECHNICAL DATA DC RECOMMENDED OPERATING CONDITIONS (Ta = 0° to 70°C) [smear [ mee me po | Input Low Voltage | -o [| - [os | Data Retention Supply Voltage Pozo | = | ss | * 3.0 when measured at a pulse width of 50 ns DC CHARACTERISTICS (Ta = 0° to 70°C, Vpp = 5V + 10%) SYMBOL PARAMETER TEST CONDITION | rain [re | max | UNIT [a [ost stage cwret [Yns eviews ———S~dC (iY do | | J ton [output High current [von=2ev f= | T= | ma | Output Low Current [Vou = 04 [so | = | = | ma | \\ Output Leakege Current CET = Viy or CE2 = Vi, or RW = Vi. or +10 to tpl 9 OE = Vin, Vour = OV to Vpp oe un CET = Vi. and CE2 = Viq 70 and RW = Vin, lppor Teycle} mA lour = OmA 1 20 Other Inputs = ViwVit ws Operating Current — CE1 = 0.2V and CE2 = Vpp - 0.2V. I RAV = Vp - 0.2V, Teycle| mA poz lour = OmA ¥ Other Inputs = Vpp - 0.2W/0.2V tas leet=viworcez=vu | | = fa | ma | Ipps2 Standby Current CET = Vpp - 0.2V or CE2 = 0.2V 7 WA (Note) Vop = 2.0 to 5.5V,Ta = 0° to 70°C Note: In standby mode with CET 2 Vpp — 0.2 V, these limits are assured for the condition CE2 2 Vpp - 0.2 V or CE2 S 0.2V. CAPACITANCE (Ta = 25°C, f = 1 MHz) SYMBOL PARAMETER TEST CONDITION Vin = GND [oo |. [cour [output capacitance Yours endC—C—C—*é‘dSC‘(z CL Note: This parameter is periodically sampled and is not 100% tested. TC551001BPL—3 1996 - 09 - 02 TOSHIBA CORPORATION

INTEGRATED CIRCUIT | sesseptaptee: fore TOSHIBA 7551001 BPL/BFL/BFTL/BTRL- 10 TECHNICAL DATA AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = 0° to 70°C, Vpp = 5V + 10%) READ CYCLE syM@ot PARAMETER unit [min | max | min [max | min] max | a PS [tor | chip erabe C2) accen tine +f =| 70 | =| | | | | tcce [Gp erable (C2) Aces Tine |= | 0s [tox | omputenatte Aces tine Ts pe | [toe | chip eoble tow to Oumutaaive fo | - [wf - | w [-_| [ocr | Over erabe tow to Ouput ave | s | =| 5 | =| s | - | [too | chip Enable Hight Oupuronz | - | = | - | | - | = | [tooo | Output Enable High to Output High? | =| 25 | = | 90 | - | 25 | [ios | opt bata Hold time SSCs? | - | vo] - | | -_| WRITE CYCLE syMB0t PARAMETER unr [min | max | min | max | min] max | [ec [wiecetme i TPT - [of [oe [ We Pate wes we [tow | hip Erie to end twee +f | = fs | - | | | [ts | Adtesseuptine Sid | fo PP [ton [ We teow tine SSS | pe [toon | RW tow to OuputHighe? id = | | fo | [toow [WwW Hgh we Ouptacive | 3 | - fs >- >=] -_ [ts [owt seuptine SSS | oP [| vata oid tine SSS oP Po | Po | AC TEST CONDITIONS Output load: 100 pF + one TTL gate Input pulse level: 0.6 V, 2.4 V Timing measurements: 1.5 V Reference level: 1.5 V tr, tr: 5ns TC551001BPL—4 1996 - 09 - 02 TOSHIBA CORPORATION

INTEGRATED CIRCUIT 7551001 BPL/BFL/BFTL/BTRL- 70 TOSHIBA Tess1001 BPL/BEL/BFTL/BTRL. 10 TECHNICAL DATA TIMING DIAGRAMS tee ADDRESS i WRITE CYCLE 1 (R/W CONTROLLED) (See Note 4) Dour Wj, (See Note 2) Yl My (See Note 3) Yj

INTEGRATED CIRCUIT | _re3s1go1 pt art/ern. ar 70 TOSHIBA TEee1001 BPL/BEL/ BETL/BTRL. 10 TECHNICAL DATA WRITE CYCLE 2 (GE1 CONTROLLED) (See Note 4) WRITE CYCLE 3 (CE2 CONTROLLED) (See Note 4) MEIIECYOUES(CE2CONTHOUUED Gree ow Yee nore 9 TIN on WT, Gee Note 3)

INTEGRATED CIRCUIT TC551001 BPL/ BFL/BFTL/BTRL- 70 7TC551001 BPL/ BFL/ BFTL/BTRL- 85 TOSHIBA TC551001 BPL/BFL/BFTL/BTRL- 10 TECHNICAL DATA Note: (1) R/W remains HIGH for the read cycle. (2) If CET goes LOW (or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs will remain at high impedance, (3) If CEI goes HIGH (or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will remain at high impedance. (4) If OE is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. DATA RETENTION CHARACTERISTICS (Ta = 0° to 70°C) ee a los standby Curent mesov] - | - [ J, Puoesav| [=| or oie wane meio nie ne | |= | =| Pe | monte Es P| CEi CONTROLLED DATA RETENTION MODE (See Note 1) Voo Voo DATA RETENTION MOD 45V -omSafarnnn ha ----- a Viq 777 _ Vop - 0.2V CEH toor tg N — TC551001BPL—7 1996 - 09 - 02 TOSHIBA CORPORATION

INTEGRATED CIRCUIT 551001 BPL/BFL/BFTL/BTRL- 70 7TC551001 BPL/ BFL/ BFTL/BTRL- 85 TOSHIBA 7551001 BPL/BFL/BFTL/BTRL- 10 TECHNICAL DATA CE2 CONTROLLED DATA RETENTION MODE (See Note 3) Yoo Vpp DATA RETENTION MODE - a ny oo ce Yor r « MW K YMA GND: — alll lO — Note: (1) In CEI controlled data retention mode, minimum standby current mode is entered when CE2 = 0.2 V or CE2 = Vpp — 0.2 V. (2) When CE1 is operating at the Vin level (2.2 V), the operating current is given by Ipps1 during the transition of Vpp from 4.5 to 2.4 V. (3) In CE2 controlled data retention mode, minimum standby current mode is entered when CE2 = 0.2V. TC551001BPL—8 1996 - 09 - 02 TOSHIBA CORPORATION

INTEGRATED CIRCUT | rum muendarnemt 2 TOSHIBA 7C551001 BPL/BFL/BFTL/BTRL- 10 TECHNICAL DATA PACKAGE DIMENSIONS (DIP32-P-600) Units in mm bh 32 7 T poo g | 3 Si ) : a & 1 16 —f 42.5 max 42.0+0.2 NX ” 3,3 fs Fy WOOO es Shen E Fy —s 3 a 1.9510 14404 || 05201 pom Weight: 4.45 g (typ) TC551001BPL—9 1996-09-02 TOSHIBA CORPORATION

INTEGRATED CIRCUIT | sessag aan art m2 TOSHIBA 7C551001 BPL/BFL/BFTL/BTRL- 10 TECHNICAL DATA PACKAGE DIMENSIONS (SOP32-P-525) Units in mm 32 17 OHOGaoenangaoggg HAAARHAA ARH HHHHH a | al 2 = | = || = ‘WAAR AHAEREHEAGHEE GOUT EBEGBESE q 6 1 16 21.1MAX “ 20.610.2 a | a] 2 3 CAAA sh. & | Baa) § = — S 0.820.2 Weight: 1.04g (typ) TC551001BPL—10 1996-09-02 TOSHIBA CORPORATION

INTEGRATED CIROUT | sepusensencernem 7 TOSHIBA 7C551001 BPL/BFL/BFTL/BTRL- 10 TECHNICAL DATA PACKAGE DIMENSIONS (TSOP32-P-0820) Units in mm S iB] Ww

1 Es 32 a oy

= = 6 = = EB & 2 =| =——I ° = oe E 2 = 16 & — te 7 © teste ia 1,040.1 0.10.05 2 f SS 8 ifs é 0.520.1 Weight: 0.34 g (typ) TC551001BPL—11 1996-09-02 TOSHIBA CORPORATION

INTEGRATED CIRCUIT | sei aan een am TOSHIBA 7C551001 BPL/BFL/BFTL/BTRL- 10 TECHNICAL DATA PACKAGE DIMENSIONS (TSOP32-P-0820A) Units in mm x ta] cs 32 cy m1 & tp = i oS = = EE 2/5] |S is = =—— oo) NM) | oy = S| = ve — B 16 2 | teaton z 1.040.4 0.1+0.05 ay ee bd f Sr e ME 0.540.1 Weight: 0.34 g (typ) TC551001BPL— 12* 1996-09-02 TOSHIBA CORPORATION