TC551001APL TOSHIBA | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 8

Technical content

131,072 WORD x 8 BIT STATIC RAM

Description

The TC551001APL is a 1,048,576 bit CMOS static random access memory organized as 131,072 words by 8 bits and operated froma single 5V power supply. Advanced circuit techniques provide both high speed and low power features with an operating cur- rent of SMA/MHz (typ.) and a minimum cycle time of 70ns. When CET is a logical high, or CE2 is low, the device is placed ina low power standby mode in which the standby current is 2uA typically. The TC551001APL has three control inputs. Chip enabie inputs (CE1, CE2) allow for device selection and data retention control, while an outout enable input (OE) provides fast memory access. The TC551001APL is suitable for use in microprocessor systems where high speed, low power, and battery backup are required. The TC551001APL-(L7) has an operating temperature range of -20 ~ 70°C so itis suitable for use in low temperature applications The TC551001APL is offered in a standard dual-in-line 32-pin plastic package, a small outline plastic Package, and a thin small outline plastic package (forward type, reverse type). Features Pin Connection (Top View) * Low power dissipation: 27.5mW/MH2 (typ.) © 32 PIN DIP_& SOP © 32 PIN TSOP : See rurent YOQUA (max) ney 321) Vop (forward type) (reverse type) gle SV Power Supply aie 2 319 ars SIMIAN ANNAN * Access time (max.) aud 3 300) cez ‘TCS51001APL/AFL/AFTL/ATRL Aid 4 292) Rw = a7ds 280) a13 Tout) | -86(tT) | 1007) ac 6 270) as Sde0 ban [CET Access Time | 70ns | eins | 1005 | 43g 24) OE [CE2 Access Time | 7Ons | ans | 1000s | a2 C10 2B ato [OE Access Time |“ 36ns_ | 45n5 | vai 38 OE Access Time ‘35ns ‘== [Sons * | di 21H 08 * Power down feature: CE, CE2 oi 13 200 1/07 * Data retention supply voltage: 2.0 ~ 5.5V 10214 196) 1/06 * Wide operating ternperature: 20 ~ 70°C Wost}1s 186) 1705 Gn} 16 VA vos TOON TOTO * Inputs and outputs TTL compatible * Package TCSS51001APL — : DIP32-P-600 TC551001AFL. SOP32-P-525 TCSS1001AFTL : TSOP32-P-0820 Pin Names TC5S1001ATRL : TSOP32-P-0820A [Row | Readwrite Control input | [OE | Output Enabie input | CEI, cea [pweo. |i [etsit«{[s ter Tete Tol uf eye] [is [i | [ PINNAME | Ar | Ap | Ae | Ar [RW] CE2 | Ars | Voo [NO [Ave | Aus | Ave | Ar | Ae | As | Ay | | Pwo. | a7 [18 | 19 | 20 | 21 | ee | as | as [25 | 28 | a7 | 20 | 20 | 20 [a1 | ae | [PINNAME [As [Ae | Ar | Ao | vor | vo2 | vos | ano | vo4 | vos | vos | vo7 | vos | CET | Ar | OE | TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. A-83 M@™ 9097248 O02b226 777 a

TC551001APL/AFL/AFTL/ATRL-70/85/10(LT) Static RAM chanelle asl eats Block Diagram ce aze tod fi i se Us ifs Ni Aes |leslle MEMORY CELL _ Aljo—18«| |8e]/8S ARRAY Alze Sel esl{sS]] 512x64x32 alge BSUSEUISL (1048576) ~ Ales—Sapjee|iea s a led a | les — 2 COLUMN ADDRESS R ht 65 COLUMN ADDRESS Pe] ° jou REGISTER vor eT | COLUMN ADDRESS BUFFER 4 ADATAZ AI ASASAE AIO BE 7p ee we TE) TET o (> cE CE2 o-f>o Operating Mode . | — PIN [Reg | ETH | Ot | OH | Dour | tooo | {write a Output Deselect a | PR High 2 tos _| “Hor | Maximum Ratings [ srmBot | Tem raving =| UNIT ' Voo | [Wie [Input and Output Vohage | |_ Pp _| Power Diesipation | [Terra [Storage Temperature | 85-150 |e | | * -2.0V with a puise width of 50ns, | La A-84 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. @™ 9097248 0026229 403 a

Static RAM 1551001 APLIAFL/AFTL/ATRL-70/85/10(LT) a Ee EN ANMATRL-70/85/10(LT) DC Recommended Operating Conditions Power Supply Voltage 45 | 50 | 55 | ip Low Vota [os] tos | DC Characteristics (Ta = -20 ~ 70°C, Vpp = 5V+10%) CET = Vy, or CE2 = Vy, or RW = Vy, or ut Le Current a t wt 41.0 A [ox | Opi ow Curent a TET = Vi, and CE2 = Viy Min, [= | - | 7 | and RW = Via, four = OMA feyte | us Other Inputs = ViVi Operating Current ORT = O.2V and | Min [= | = | o CE2 = Vop -0.2V \\ RW = Vp - 0.20 ‘2002 lout = OmA, Other Inputs = Vop - 0.2V/0.2V 'DDS2 =e 5° - Note (1): ICET 2 Vpp - 0.2V, the specified limits are guaranteed under the condition CE2 2 Vpp - 0.2V or CE2 < 0.2V, Capacitance" (Ta = 25°C, f = 1MHz) [ svmeot | PARAMETER TEST CONDITION | max. | unit Input Capacitance Vin = GND 10 F | “This parameter is periodically sampled and is not 100% tested. TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. A-85 MM 9097248 0026230 325 mM a

10551001 APL/AFLIAFTL/ATRL-70/85/10(LT) Static RAM

TCSSIOOIAPLIAFLIAFTLIATRL-7O/B5/10(LT) Static RAM AC Characteristics (Ta = -20 ~ 70°C, Vpp = 5V+10%) Read Cycle _. TC5STOOTAPLIAFL/AFTUATRL PARAMETER ~-70(kT) gst) | -10(LT) uNIT [Tine [ReadGyiotme S| ST Tm | = | too | [taco [AdsressAccesstime | | 7 | =f 8 | 00 | [too [CE2AccessTime | | | = | 8 T= | 800 | [toe [OuiputenabietoOuputinvaid | — ‘| a6 [ - | 4s [= | 80 | [tooe | Grip Enable GET, cea) toOuputintowzZ {5 | - | § | = | 8 | = toce [OuiputEnabietoOupatintowZ [| 0 | - | o | = | o | = | too [Chip Enable GET, CEA OupuinHighz | — | 25 | - [a | = | 38 | ‘ooo [OulputEnable to Oupatinrighz | | ee | | Ts | tou _[ Output Data Hold Time | Write Cycle ; TC5S1001APLIAFLIAFTLIATAL SYMBOL PARAMETER ~-7O(UT) eT) | -10(tT) | [tne [Wiiecyieine Of = | om T= | too | [we [WriePusewit | | = | oo [= | oo | [tow [ChipSeteciontoendotwite | eo | - | 7 | = | a | - | } [tus [Adsress Souptime S| Of ~ | Oo | = | oO | [tn [Wate Recoverytime S| | - (| oT = To | | [toow [RWio Ouiputinviohz | | os | | 0 T= | 8 | [tow [RWtoOuputintwz | 0 | - | 2 | = | of | [tos [DataSeuptine S| 0 | 8 P| [tow [OateHowtime TT | eT Pc AG Test Conditions _ 2.6V0.4V Input Pulse Rise and Fall Time 5ns 15V 1.5V TTTLGate and G.= 10°F | 4-86 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. me 5057248 002623) 26) a ee

sito an reson arciarvarruarmi rato.) Me 9097248 oo2b 232 178 mm =—Tenecomrenenren “sr

TC551001 APLIAFL/AFTL/ATRL-70/85/10(LT) Static RAM twe MMMM My WEY Write Cycle 3) (CE2 Controlled Write) twe ” WW EWU Wella | | “30 97248 O02be23 3 O34 -_— nis

Static RAM TC551001 APL/AFL/AFTL/ATRL-70/85/10(LT) eee eee One weewsaaaaer Notes: 1. RWis high for read cycles. 2. If the CET low transition or CE2 high transition occurs coincident with or after the R/W low transition, outputs remain in a high impedance state. 3. If the CET high transition or CE2 low transition occurs coincident with or prior to the R/W high transition, outputs remain in a high impedance state. 4, If OE is high during a write cycle, the outputs are in a high impedance state during this period. 5. The /O may be in the output state during this time; therefore input signals of opposite phase must not be applied. ~ TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. A-89 m™ 9097248 0026234 T70 mm Neen

TC551001 APL/AFL/AFTL/ATRL-70/85/10(LT) Static RAM arrest Data Retention Characteristics (Ta = -20 ~ 70°C) Ee [Vou [Bala eterion SuppiVotase Se | | ouesov = f= | Ci toon _| Chip Deselect to Data Retention Mode foo | - | = | rs | EA Controlled Data Retention Mode“! | Yoo Yoo DATA RETENTION MOD : 7A nA Voo* 0.2V i<ai con ” |. | CE2 Controlled Data Retention Mode © Voo Voo DATA RETENTION MODE . a ne, a Vn CE2 . veree ~\\___I. 0. —_—_ Notes: 1. In the CET controlled data retention mode, minimum standby current is achieved under the condition CE2 s 0.2V or CE2 2 Vop - 0.2V. : 2. If the Vj, of CET is 2.4V in operation, during the period that the Vpp voltage is going down from 4.5V to 2.6V, lpps+ ! current flows. } 3. In the CE2 controlled data retention mode, minimum standby current is achieved under the condition CE2 < 0.2V. A-90 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. M@9097248 o02b235 107 .