TC510COI

Microchip Technology

Precision Analog Front Ends with Dual Slope ADC 2008

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Precision (up to 17 bits) A/D Converter “Front End”
3-Pin Control Interface to Microprocessor
Flexible: User Can Trade-off Conversion Speed for Resolution
Single-Supply Operation (TC510/TC514)
4 Input, Differential Analog MUX (TC514)
Automatic Input Voltage Polarity Detection
Low Power Dissipation: - (TC500/TC500A): 10 mW - (TC510/TC514): 18 mW
Wide Analog Input Range: - ±4.2V (TC500A/TC510)
Directly Accepts Bipolar and Differential Input Signals Applications:
Precision Analog Signal Processor
Precision Sensor Interface
High Accuracy DC Measurements General Description: TheTC500/A/510/514 family are precision analog front ends that implement dual slope A/D converters having a maximum resolution of 17 bits plus sign. As a minimum, each device contains the integrator, zero crossing comparator and processor interface logic. The TC500 is the base (16-bit max) device and requires both positive and negative power supplies. The TC500A is identical to the TC500 with the exception that it has improved linearity, allowing it to operate to a maximum resolution of 17 bits. The TC510 adds an on- board negative power supply converter for single- supply operation. The TC514 adds both a negative power supply converter and a 4-input differential analog multiplexer. Each device has the same processor control interface consisting of 3 wires: control inputs (A and B) and zero- crossing comparator output (CMPTR). The processor manipulates A, B to sequence the TC5XX through four phases of conversion: au to-zero, integrate, de- integrate and integrator zero. During the auto-zero phase, offset voltages in the TC5XX are corrected by a closed loop feedback mechanism. The input voltage is applied to the integrator during the integrate phase. This causes an integrator output dv/dt directly proportional to the magnitude of the input voltage. The higher the input voltage, the greater the magnitude of the voltage stored on the inte grator during this phase. At the start of the de-in tegrate phase, an external voltage reference is applied to the integrator and, at the same time, the external host processor starts its on- board timer. The processor maintains this state until a transition occurs on the CMPTR output, at which time the processor halts its timer. The resulting timer count is the converted analog data. Integrator zero (the final phase of conversion) removes any residue remaining in the integrator in preparation for the next conversion. The TC500/A/510/514 offer high resolution (up to 17 bits), superior 50/60 Hz noise rejection, low-power operation, minimum I/O connections, low input bias currents and lower cost compared to other converter technologies having similar conversion speeds. Precision Analog Front Ends with Dual Slope ADC

DS21428E-page 2 © 2008 Microchip Technology Inc. Package Types Typical Application CMPTR OUT A DGND B VDD VIN+ VIN– VREF+ BUF VSS CINT ACOM VREF− CREF+ CREF– CAZ TC500/ TC500A 16-Pin PDIP/SOIC/CERDIP VOUT– 1 CAP– DGND A B C REF – CINT CAZ BUF ACOM CH4– CH3– CH2– TC514 CREF+ VREF – VREF+ VDD OSC CMPTR OUT CAP+ CH1– N/C CH1+ CH2+ CH3+ CH4+ 28-Pin PDIP/SOIC 24-Pin PDIP/SOIC TC510 CAP– DGND A B VDD OSC CMPTR OUT VIN+ VIN– N/C N/C CAP+ CREF– CINT CAZ BUF ACOM N/C N/C N/C VOUT– CREF+ VREF– VREF+ Level Shift Control Logic Analog Switch Control Signals ACOM VREF+ BUF CAZ Buffer IntegratorSWR SWIZ CMPTR 1 CMPTR 2 CMPTR Output DGND Control Logic SW1 TC500 TC500A TC510 TC514 CREF CREF+ SWR CREF- CAZ RINT CINT CINT SWRI- SWRI- SWRI+ SWRI- SWZ SWI SWZ VSS OSC Phase Decoding Logic Polarity Detection DC-TO-DC Converter (TC510 & TC514) A B 0 0 Zero Integrator Output 0 1 Auto-Zero 1 0 Signal Integrate 1 1 De-integrateVREF- VOUT- COUT- 1.0 μF 1.0 μF VSS SWI BA A0 A1 DIF. MUX (TC514) CH1+ CH2+ CH3+ CH4+ CH1- CH2- CH3- CH4- CAP- CAP+ (TC500 TC500A) Converter Sate

1.0 ELECTRICAL

Absolute Maximum Ratings† TC510/TC514 Positive Supply Voltage TC500/TC500A Supply Voltage TC500/TC500A Positive Supply Voltage TC500/TC500A Negative Supply Voltage Voltage on OSC: Ambient Operating Temperature Range: † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS = ±5V. CAZ = CREF = 0.47 μF. Parameters Sym TA = +25°C T A = 0°C to 70°C Units Conditions Analog Resolution 60 — — — — — μV Note 1 Zero-scale Error with Auto-zero Phase — — 0.003 — 0.003 0.009 TC500A TC500A Best-Case Straight Line Linearity NL — 0.003 0.008 — — — % F.S. TC500/TC510/TC514, Note 1, Note 2 Zero-scale Temp. Coefficient ZSTC ——— —1 2 μV/°C Over Operating Temperature Range Full-scale Symmetry Error (Rollover Error) SYE — 0.01 — — 0.03 — % F.S. Note 1 Full-scale Temperature Coefficient FSTC — — — — 10 — ppm/°C Over Operating Temperature Range; External Reference TC = 0 ppm/°C Input Current I IN —6— —— — p A V IN = 0V Common Mode Voltage Range VCMR VSS + 1.5 — V DD – 1.5 V SS + 1.5 — V DD – 1.5 V Integrator Output Swing VSS + 0.9 — V DD – 0.9 V SS + 0.9 — V SS + 0.9 V Analog Input Signal Range VSS + 1.5 — V DD – 1.5 V SS + 1.5 — V SS + 1.5 V ACOM = GND = 0V Note 1: Integrate time ≥ 66 ms, auto-zero time ≥ 66 ms, VINT (peak) ≈ 4V. 2: End point linearity at ±1/4, ±1/2, ±3/4 F.S. after full-scale adjustment. 3: Rollover error is related to CINT, CREF, CAZ characteristics.

DS21428E-page 4 © 2008 Microchip Technology Inc. Voltage Reference Range VREF VSS +1 — V DD – 1 V SS +1 — V DD – 1 V V REF- VREF+ Digital Comparator Logic 1, Output High VOH 4— — 4 — — V I SOURCE = 400 μA Comparator Logic 0, Output Low VOL — — 0.4 — — 0.4 V I SINK = 2.1 mA Logic 1, Input High Voltage Logic 0, Input Low Voltage VIL —— 1 — — 1 V Logic Input Current I L —— — — 0 . 3 μA Logic ‘ 1’ or ‘0’ Comparator Delay t D —2 — — 3— μs Multiplexer (TC514 Only) Maximum Input Voltage Drain/Source ON Resistance RDSON —61 0 — — — k Ω VDD = 5V Power (TC510/TC514 Only) Supply Current I S — 1.8 2.4 — — 3.5 mA V DD = 5V, A = 1, B = 1 Power Dissipation P D —1 8— — — —m W V DD = 5V Positive Supply Operating Voltage Range V DD 4.5 — 5.5 4.5 — 5.5 V Operating Source Resistance ROUT — 60 85 — — 100 Ω IOUT = 10 mA Oscillator Frequency — 100 — — — — kHz Note 1 Maximum Current Out IOUT —— - 1 0 — — - 1 0m A V DD = 5V Power (TC500/TC500A Only) Supply Current I S — 1 1.5 — — 2.5 mA V S = ±5V, A = B = 1 Power Dissipation P D —1 0— — — —m W V DD = 5V, VSS = -5V Positive Supply Operating Range VDD 4.5 — 7.5 4.5 — 7.5 V Negative Supply Operating Range DC CHARACTERISTICS (CONTINUED) = ±5V. CAZ = CREF = 0.47 μF. Parameters Sym TA = +25°C T A = 0°C to 70°C Units Conditions Note 1: Integrate time ≥ 66 ms, auto-zero time ≥ 66 ms, VINT (peak) ≈ 4V. 2: End point linearity at ±1/4, ±1/2, ±3/4 F.S. after full-scale adjustment. 3: Rollover error is related to CINT, CREF, CAZ characteristics.

2.0 TYPICAL PERFORMANCE CURVES

FIGURE 2-1: Output Voltage vs. Load Current. FIGURE 2-2: Output Ripple vs. Load Current. FIGURE 2-3: Oscillator Frequency vs. Capacitance. FIGURE 2-4: Output Voltage vs. Output Current. FIGURE 2-5: Output Source Resistance vs. Temperature. FIGURE 2-6: Oscillator Frequency vs. Temperature. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purpose s only. The performance characteristics listed herein are not tested or guaranteed. In so me graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Load Current (mA) 0 1 02 03 04 0 50 60 70 80 Output Voltage (V) TA = +25°C V+ = 5V Slope 60Ω Load Current (mA) 0 3 45612 78 9 1 0 100 125 150 175 200Output Ripple (mV PK-PK) V+ = 5V, TA = +25°C Osc. Freq. = 100 kHz CAP = 1 µF CAP = 10 µF Oscillator Capacitance (pF) 100 11 0 100 1000 Oscillator Frequency (kHz) TA = +25°C V+ = 5V Output Current (mA) 06 8 1 0 421 4 1 6 1 8 12 20 -8 Output Voltage (V) TA = +25°C Temperature (°C) 100 -50 02 5-25 50 75 100 Output Source Resistance (Ω) V+ = 5V IOUT = 10 mA Temperature (°C) 125 150 100 -50 02 5-25 50 75 125100 Oscillator Frequency (kHz) V+ = 5V

3.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE TC500, TC500A TC510 TC514 Symbol Function CERDIP, PDIP , SOIC PDIP, SOIC PDIP , SOIC 12 2 C INT Integrator output. Integrator capacitor connection. 2 Not Used Not Used V SS Negative power supply input (TC500/TC500A only). 33 3 C AZ Auto-zero input. The auto-zero capacitor connection. 4 4 4 BUF Buffer output. The Integrator capacitor connection. 5 5 5 ACOM This pin is grounded in most applications. It is recommended that ACOM and the input common pin (Ve n- or CHn-) be within the analog Common Mode Range (CMR). 66 6 C REF- Input. Negative reference capacitor connection. 77 7 C REF+ Input. Positive reference capacitor connection. 88 8 V REF- Input. External voltage reference (-) connection. 99 9 V REF+ Input. External voltage reference (+) connection. 10 15 Not Used V IN- Negative analog input. 11 16 Not Used V IN+ Positive analog input. 12 18 22 A Input. Converter phase control MSB. (See input B.) 13 17 21 B Input. Converter phase control LSB. The states of A, B place the TC5XX in one of four required phases. A conversion is complete when all four phases have been executed: Phase control input pins: AB = 00: Integrator zero 01: Auto-zero 10: Integrate 11: De-integrate 14 19 23 CMPTR OUT Zero crossing comparator output. CMPTR is high during the integration phase when a positive input voltage is being integrated and is low when a negative input voltage is being integrated. A high- to-low transition on CMPTR signals the processor that the De- integrate phase is completed. CMPTR is undefined during the auto- zero phase. It should be monitored to time the integrator zero phase. 15 23 27 DGND Input. Digital ground. 16 21 25 V DD Input. Power supply positive connection. — 22 26 CAP+ Input. Negative power supply converter capacitor (+) connection. — 24 28 CAP- Input. Negative power supply converter capacitor (-) connection. —1 1 V OUT- Output. Negative power supply converter output and reservoir capacitor connection. This output can be used to power other devices in the circuit requiring a negative bias voltage. — 20 24 OSC Oscillator control input. The negative power supply converter normally runs at a frequency of 100 kHz. The converter oscillator frequency can be slowed down (to reduce quiescent current) by connecting an external capacitor between this pin and V DD (see Section 2.0 “Typical Performance Curves”). — — 18 CH1+ Positive analog input pin. MUX channel 1. — — 13 CH1- Negative analog input pin. MUX channel 1. — — 17 CH2+ Positive analog input pin. MUX channel 2. — — 12 CH2- Negative analog input pin. MUX channel 2. — — 16 CH3+ Positive analog input pin. MUX channel 3. — — 11 CH3- Negative analog input pin. MUX channel 3. — — 15 CH4+ Positive analog input pin. MUX channel 4. — — 10 CH4- Negative analog input pin. MUX channel 4 — — 20 A0 Multiplexer input channel select input LSB (see A1).

DS21428E-page 8 © 2008 Microchip Technology Inc. — — 19 A1 Multiplexer input channel select input MSB. Phase control input pins: A1, A0 = 00 = Channel 1 01 = Channel 2 10 = Channel 3 11 = Channel 4 TABLE 3-1: PIN FUNCTION TABLE (CONTINUED) TC500, TC500A TC510 TC514 Symbol Function CERDIP, PDIP , SOIC PDIP, SOIC PDIP , SOIC

4.0 DETAILED DESCRIPTION

4.1 Dual Slope Conversion Principles

Actual data conversion is accomplished in two phases: input signal integration and reference voltage de-integration. The integrator output is initialized to 0V prior to the start of integration. During integration, analog switch S connects V IN to the integrator input where it is maintained for a fi xed time period (T INT). The application of VIN causes the integrator output to depart 0V at a rate determined by the magnitude of VIN and a direction determined by the polarity of V IN. The de- integration phase is initiated immediately at the expiration of T INT. During de-integration, S1 connects a reference voltage (having a polarity opposite that of VIN) to the integrator input. At the same time, an external precision timer is started. The de-integration phase is maintained until the comparator output changes state, indicating the integrator has returned to its starting point of 0V. When this occurs, the precision timer is stopped. The de- integration time period (T DEINT), as measured by the precision timer, is directly proportional to the magnitude of the applied input voltage (see Figure 4-3). A simple mathematical equation relates the input signal, reference voltage and integration time: EQUATION 4-1: For a constant VIN: EQUATION 4-2: The dual slope converter accuracy is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. An inherent benefit is noise immunity. Input noise spikes are integrated (averaged to zero) during the integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high noise environments. Integrating converters provide inherent noise rejection with at least a 20dB/dec ade attenuation rate. Interference signals with frequencies at integral multiples of the integration period are, theoretically, completely removed, since the average value of a sine wave of frequency (1/T) averaged over a period (T) is zero. Integrating converters oft en establish the integration period to reject 50/60 Hz line frequency interference signals. The ability to reject such signals is shown by a normal mode rejection plot (Figure 4-1). Normal mode rejection is limited in practice to 50 to 65 dB, since the line frequency can deviate by a few tenths of a percent (Figure 4-2). FIGURE 4-1: Integrating Converter Normal Mode Rejection. FIGURE 4-2: Line Frequency Deviation. Where: VREF = Reference Voltage TINT = Signal Integration time (fixed) tDEINT = Reference Voltage Integration time (variable) RINT CINT TINT VREF CDEINT RINT CINT VIN VREF TDEINT TINT 0.1/T 1/T 10/T Input Frequency Normal Mode Rejection (dB) T = Measurment Period 0.01 0.1 1.0 Normal Mode Rejeciton (dB) t = 0.1 sec Line Frequency Deviation from 60 Hz (%) Normal Mode = 20 LOG Rejection DEV = Deviation from 60 Hz t = Integration Period SIN 60 t (1 – )p p DEV 100 DEV 10060 t (1 – )

DS21428E-page 10 © 2008 Microchip Technology Inc. FIGURE 4-3: Basic Dual Slope Converter. Phase Control Comparator Integrator Output Integrator CINT Analog Input (VIN) Switch DriverRef Voltage Control LogicPolarity Control I/O Timer Counter ROM RAM Microcomputer AB CMPTR Out VSUPPLY TINT TC510 VINT VIN ≈ VREF VIN ≈ 1/2 VREF TDEINT RINT VINT–

5.0 TC500/A/510/514 CONVERTER

The TC500/A/510/514 incorpor ates an auto-zero and Integrator phase in addition to the input signal Integrate and reference De-integrat e phases. The addition of these phases reduce system errors, calibration steps and shorten overrange recovery time. A typical measurement cycle uses all four phases in the following order: 1. Auto-zero. 2. Input signal integration. 3. Reference de-integration. 4. Integrator output zero. The internal analog switch status for each of these phases is summarized in Table 5-1. This table references the Typical Application. TABLE 5-1: INTERNAL ANALOG GATE STATUS

5.1 Auto-zero Phase (AZ)

During this phase, errors due to buffer, integrator and comparator offset voltages are nulled out by charging C AZ (auto-zero capacitor) wi th a compensating error voltage. The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to analog common. The reference capacitor is charged to the reference voltage potential through SW R. A feedback loop, closed around the integrator and comparat or, charges the capacitor (CAZ) with a voltage to compensate for buffer amplifier, integrator and comparator offset voltages.

5.2 Analog Input Signal Integration

Phase (INT) The TC5XX integrates the differential voltage between the VIN+ and VIN– inputs. The differential voltage must be within the device’s Common mode range VCMR. The input signal polarity is normally checked via software at the end of this phase: CMPTR = 1 for positive polarity; CMPTR = 0 for negative polarity.

5.3 Reference Voltage De-integration

Phase (DINT) The previously charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero. An externally-provided, precision timer is used to measure the duration of this phase. The resulting time measurement is proportional to the magnitude of the applied input voltage.

5.4 Integrator Output Zero Phase (IZ)

This phase ensures the integrator output is at 0V when the auto-zero phase is ente red, and that only system offset voltages are compensated. This phase is used at the end of the reference vo ltage de-integration phase and MUST be used for ALL TC5XX applications having resolutions of 12-bits or more. If this phase is not used, the value of the auto-zero capacitor (C AZ) must be about 2 to 3 times the value of the integration capacitor (CINT) to reduce the effects of charge sharing. The integrator output zero phase should be programmed to operate until the output of the comparator returns high. The overall timing system is shown in Figure 5-1. Conversion Phase SW I SWR+S W R-S W Z SWR SW1 SWIZ Auto-zero (A = 0, B = 1) — — — Closed Closed Closed — Input Signal Integration (A = 1, B = 0) Closed — — — — — — Reference Voltage De-integration (A =1, B = 1) — Closed — — — Closed — Integrator Output Zero (A = 0, B = 0) — — — — Closed Closed Closed * Assumes a positive polarity input signal. SW– RI would be closed for a negative input signal.

DS21428E-page 12 © 2008 Microchip Technology Inc. FIGURE 5-1: Typical Dual Slope A/D Converter System Timing. Auto-zero Integrate Full-scale Input Reference De-integrate Overshoot Integrator Output Zero Converter Status TTIME Integrator Voltage VINT Comparator Output AB Inputs Controller Operation Notes: Comparator Delay Begin Conversion with Auto-Zero Phase (Positive Input Shown) Sample Input Polarity The length of this phase is chosen almost arbitrarily but needs to be long enough to null out worst case errors (see text). Minimizing Overshoot will Minimize I.O.Z. Time Ready for Next Conversion (Auto-Zero is Idle State) Time Input Integration Phase Capture De-integration Time Integrator Output Zero Phase Complete Undefined A = 0 B = 1 A = 1

0 For Negative Input

1 For Positive Input

B = 0 B = 1 B = 0 A = 1 A = 0 Typically = TINT TINT A B Comparator Delay + Processor Latency

6.0 ANALOG SECTION

6.1 Differential Inputs (V IN+, VIN–)

The TC5XX operates with differential voltages within the input amplifier Common mode range. The amplifier Common mode range extends from 1.5V below positive supply to 1.5V above negative supply. Within this Common mode voltage range, Common mode rejection is typically 80 dB. Full accuracy is maintained, however, when the inputs are no less than 1.5V from either supply. The integrator output also follows the Common mode voltage. The integrator output must not be allowed to saturate. A worst-case condition exists, for example, when a large, positive Common mode voltage, with a near full-scale negative diff erential input voltage, is applied. The negative input signal drives the integrator positive when most of its swing has been used up by the positive Common mode voltage. For these critical applications, the integrator swing can be reduced. The integrator output can swing within 0.9V of either supply without loss of linearity.

6.2 Analog Common

Analog common is used as V IN return during system zero and reference de-integrate. If VIN– is different from analog common, a Common mode voltage exists in the system. This signal is rejected by the excellent CMR of the converter. In most applications, VIN– will be set at a fixed known voltage (i.e., power supply common). A Common mode voltage will exist when V IN– is not connected to analog common.

6.3 Differential Reference

(VREF+, VREF–) The reference voltage can be anywhere within 1V of the power supply voltage of the converter. Rollover error is caused by the reference capacitor losing or gaining charge due to stray capacitance on its nodes. The difference in reference for (+) or (-) input voltages will cause a rollover error. This error can be minimized by using a large reference capacitor in comparison to the stray capacitance.

6.4 Phase Control Inputs (A, B)

The A, B unlatched logic inputs select the TC5XX operating phase. The A, B inputs are normally driven by a microprocessor I/O port or external logic.

6.5 Comparator Output

By monitoring the comparator output during the fixed signal integrate time, the input signal polarity can be determined by the microprocessor controlling the conversion. The comparator output is high for positive signals and low for negative signals during the signal integrate phase (see Figure 6-1). During the reference de-integrate phase, the comparator output will make a high-to-low transition as the integrator output ramp crosses zero. The transition is used to signal the processor that the conversion is complete. The internal comparator delay is 2 μs, typically. Figure 6-1 shows the comparator output for large positive and negative signal inputs. For signal inputs at or near zero volts, however, the integrator swing is very small. If Common mode noise is present, the comparator can switch se veral times during the beginning of the signal integrate period. To ensure that the polarity reading is correct, the comparator output should be read and stored at the end of the signal integrate phase. The comparator output is undefined during the auto- zero phase and is used to time the integrator output zero phase. (See Section 8.6 “Integrator Output Zero Phase”). FIGURE 6-1: Comparator Output. Integrator Output Zero Crossing Comparator Output ReferenceSignal Integrate Integrator Output Zero Crossing Comparator Output Reference Deintegrate Signal Integrate B. Negative Input SignalA. Positive Input Signal De-integrate

7.0 TYPICAL APPLICATIONS

7.1 Component Value Selection

The procedure outlined below allows the user to arrive at values for the following TC5XX design variables: 1. Integration Phase Timing. 2. Integrator Timing Components (R INT, CINT). 3. Auto-zero and Reference Capacitors. 4. Voltage Reference.

7.2 Select Integration Time

Integration time must be pi cked as a multiple of the period of the line frequency. For example, TINT times of 33 ms, 66 ms and 132 ms maximize 60 Hz line rejection.

7.3 DINT and IZ Phase Timing

The duration of the DINT phase is a function of the amount of voltage stored on the integrator during T INT and the value of VREF. The DINT phase must be initiated immediately following INT and terminated when an integrator output zero-crossing is detected. In general, the maximum number of counts chosen for DINT is twice that of INT (with V REF chosen at VIN(MAX) /2).

7.4 Calculate Integrating Resistor

(RINT) The desired full-scale input voltage and amplifier output current capability determine the value of R INT. The buffer and integrator amplifiers each have a full-scale current of 20 μA. The value of RINT is, therefore, directly calculated in the following equation: EQUATION 7-1:

7.5 Select Reference (C REF) and Auto-

zero (CAZ) Capacitors CREF and CAZ must be low leakage capacitors (such as polypropylene). The slower the conversion rate, the larger the value C REF must be. Recommended capacitors for C REF and C AZ are shown in Table 7-1. Larger values for C AZ and C REF may also be used to limit rollover errors. TABLE 7-1: C REF AND CAZ SELECTION

7.6 Calculate Integrating Capacitor

(CINT) The integrating capacitor must be selected to maximize integrator output voltage swing. The integrator output voltage swing is defined as the absolute value of V DD Using the 20 μA buffer maximum output current, the value of the integrating capacitor is calculated using the following equation. EQUATION 7-2: It is critical that the integrating capacitor has a very low dielectric absorption. Polypropylene capacitors are an example of one such dialectic. Polyester and poly- bicarbonate capacitors may also be used in less critical applications. Table 7-2 summarizes recommended capacitors for C INT. TABLE 7-2: RECOMMENDED CAPACITOR FOR CINT

7.7 Calculate V REF

The reference de-integration voltage is calculated using the following equation: EQUATION 7-3: Where: VIN(MAX) = Maximum input voltage (full count voltage) RINT = Integrating Resistor (in M Ω) For loop stability, RINT should be ≥ 50 kΩ RINT in MΩ() VIN MAX() Conversions Per Second Typical Value of CREF, CAZ (μF) Suggested* Part Number >7 0.1 SMR5 104K50J01L4 2 to 7 0.22 SMR5 224K50J02L4 2 or less 0.47 SMR5 474K50J04L4 * Manufactured by Evox Rifa, Inc. Value Suggested Part Number*

0.1 SMR5 104K50J01L4

0.22 SMR5 224K50J02L4

0.33 SMR5 334K50J03L4

0.47 SMR5 474K50J04L4

Manufactured by Evox Rifa, Inc. Where: TINT = Integration Period VS =I V DDI or IVSSI, whichever is less (TC500/A) VS =I V DDI (TC510, TC514) CINT TINT() 20 10 6–×() VREF VS 0.9–() CINT() RINT()

8.0 DESIGN CONSIDERATIONS

8.1 Noise

The threshold noise (N TH) is the algebraic sum of the integrator and comparator noise and is typically 30 μV. Figure 8-1 illustrates how the value of the reference voltage can affect the final count. Such errors can be reduced by increased integr ation times, in the same way that 50/60 Hz noise is rejected. The signal-to- noise ratio is related to the integration time (T INT) and the integration time constant (RINT, CINT) as follows: EQUATION 8-1:

8.2 System Timing

To obtain maximum performance from the TC5XX, the overshoot at the end of th e de-integration phase must be minimized. Also, the integrator output zero phase must be terminated as soon as the comparator output returns high (see Figure 5-1). Figure 5-1 shows the overall timing for a typical system in which a TC5XX is interfaced to a microcontroller. The microcontroller drives the A, B inputs with I/O lines and monitors the comparator output (CMPTR) using an I/O line or dedicated timer capture control pin. It may be necessary to monitor the state of the CMPTR output in addition to having it control a timer directly for the Reference de-integration phase (this is further explained below.) The timing diagram in Figure 5-1 is not to scale, as the timing in a real system depends on many system parameters and component value selections. There are four critical timing events (as shown in Figure 5-1): sampling the input polarity, capturing the de-integration time, minimizing overshoot and properly executing the integrator output zero phase.

8.3 Auto-zero Phase

The length of this phase is usually set to be equal to the input signal integration time. This decision is virtually arbitrary since the magnitudes of the various system errors are not known. Setting the auto-zero time equal to the Input Integrate time should be more than adequate to null out system errors. The system may remain in this phase indefinitely (i.e., auto-zero is the appropriate Idle state for a TC5XX device).

8.4 Input Signal Integrate Phase

The length of this phase is constant from one conversion to the next and depends on system parameters and component value selections. The calculation of T INT is shown elsewhere in this data sheet. At some point near the end of this phase, the microcontroller should sample CMPTR to determine the input signal polarity. This value is, in effect, the Sign Bit for the overall conversion result. Optimally, CMPTR should be sampled just before this phase is terminated by changing AB from 10 to 11. The consideration here is that, during the initial stage of input integration when the integrator voltage is low, the comparator may be affected by noise and its output unreliable. Once integration is well underway, the comparator will be in a defined state.

8.5 Reference De-integration

The length of this phase must be precisely measured from the transition of AB from 10 to 11 to the falling- edge of CMPTR. The comp arator delay contributes some error in timing this phase. The typical delay is specified to be 2 μs. This should be considered in the context of the length of a single count when determining overall system performance and possible single count errors. Additionally, overshoot will result in charge accumulating on the integrator once its output crosses zero. This charge must be nulled during the integrator output zero phase. FIGURE 8-1: Noise Threshold. S/N (dB) 20 log VIN 30 10 6–× ⎛⎞= Low VREF Normal VREF High VREF S NTH S NTH 30 µV S NTH Slope (S) = NTH = Noise ThresholdVREF RINT CINT

8.6 Integrator Output Zero Phase

The comparator delay and the controller’s response latency may result in overshoot, causing charge buildup on the integrator at the end of a conversion. This charge must be removed or performance will degrade. The integrator output zero phase should be activated (AB = 00) until CMPTR goes high. It is absolutely critical that this phase be terminated immediately so that overshoot is not allowed to occur in the opposite direction. At this point, it can be assured that the integrator is near zero. Auto-zero should be entered (AB = 01) and the TC5XX held in this state until the next cycle is begun (see Figure 8-2). FIGURE 8-2: Overshoot.

8.7 Using the TC510/TC514

8.7.1 NEGATIVE SUPPLY VOLTAGE

CONVERTER (TC510, TC514) A capacitive charge pump is employed to invert the voltage on V DD for negative bias within the TC510/ TC514. This voltage is also available on the VOUT– pin to provide negative bias elsewhere in the system. Two external capacitors are required to perform the conversion. Timing is generated by an internal state machine driven from an on-board oscillator. During the first phase, capacitor CF is switched across the power supply and charged to VS+. This charge is transferred to capacitor COUT– during the second phase. The oscillator normally runs at 100 kHz to ensure minimum output ripple. This frequency can be reduced by placing a capacitor from OSC to V DD. The relationship between the capacitor value is shown in Section 2.0 “Typical Performance Curves”.

8.7.2 ANALOG INPU T MULTIPLEXER

(TC514) The TC514 is equipped with a four-input differential analog multiplexer. Input channels are selected using select inputs (A1, A0). These are high-true control signals (i.e., channel 0 is selected when (A1, A0 = 00). Integrator Output Comparator Output Comp Integrate Phase De-integrate Phase Integrator Zero Phase Zero Crossing Overshoot

9.0 DESIGN EXAMPLES

Refer to Figures 9-1 to 9-4. EQUATION 9-1: Given: Required Resolution: 16 bits (65,536 counts). Maximum VIN: ±2V Power Supply Voltage: +5V

60 Hz System

Step 1. Pick integration time (tINT) as a multiple of the line frequency: 1/60 Hz = 16.6 ms. Use 4x line frequency. = 66 ms Step 2. Calculate RINT: RINT = VIN(MAX) /20 μA 2 /20 μA = 100 kΩ Step 3. Calculate CINT for maximum (4V) integrator output swing. CINT = (tINT) (20 x 10 –6) / (VS - 0.9) = 0.32 μF (use closest value: 0.33 μF) Note: Microchip recommended capacitor: Evox Rifa p/n: 5MR5 334K50J03L4. Step 4. Choose CREF and CAZ based on conversion rate. Conversions/sec: = 1/(T AZ + TINT + 2 TINT + 2 ms) = 1/(66 ms +66 ms +132 ms +2 ms) = 3.7 conversions/sec From which C AZ = CREF = 0.22 μF (see Table 7-1) Note: Microchip recommended capacitor: Evox Rifa p/n: 5MR5 224K50J02L4 Step 5. Calculate VREF: VREF VS 0.9–() CINT() RINT() 2 66 10 3–×()

1.025 V()=

© 2008 Microchip Technology Inc. DS21428E-page 21 TC500/A/510/514 FIGURE 9-3: TC510 To IBM® Compatible Printer Port. PC Printer Port PORT 0378 Hex Input +5V 10 kΩ 10 kΩ 100 kΩ 100 kΩ 1 μF 1 μF121 2 3 CAP- 1910 DGND VOUT-VDD A B CINT CAZ BUF ACOM TC510 CREF+ VIN+ CAP+ CMPTR 0.22 μF 0.22 μF 0.01 μF 0.01 μF 1 μF 0.33 μF MCP1525CREF- VREF+ VREF- VIN-

DS21428E-page 22 © 2008 Microchip Technology Inc. FIGURE 9-4: TC514 To IBM® Compatible Printer Port. IBM® Printer Port Port 0378 Hex +5V 10 kΩ 100 kΩ 1 μF 1 μF125 2 3 CAP– 2310 DGND VOUTVDD A B CREF+ TC514 BUF 0.22 μF 10 kΩ 10 kΩ 0.22 μF 0.01 μF 0.33 μF CH1+ Input 1 + 18 – 13 Input 2 + 17 – 12 Input 3 + 16 – 11 Input 4 + 15 – 10 CAP+ CREF- VREF+ VREF- CAZ CINT ACOM CH1– CH2+ CH2– CH3+ CH3– CH4+ CH4– CMPTR Analog Mux Control Logic MCP1525

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

16-Lead PDIP (300 mil) (TC500/TC500A) Example: 16-Lead SOIC (300 mil) (TC500/TC500A) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN XXXXXXXXXXX YYWWNNN TC500CPE ^^ 0818256 XXXXXXXXXXX Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part nu mber cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 16-Lead CERDIP (300 mil) (TC500/TC500A) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN TC500AIJE 0818256 XXXXXXXXXXX 0818256 TC500ACOE ^^

DS21428E-page 24 © 2008 Microchip Technology Inc. Package Marking Information (Continued) 28-Lead PDIP (300 mil) (TC514) Example: 28-Lead SOIC (300 mil) (TC514) Example: XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN TC514CPJ ^^ 0818256 XXXXXXXXXXXXXXXXXXXX YYWWNNN XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX 0818256 TC514COI ^^ 24-Lead PDIP (300 mil) (TC510) Example: 24-Lead SOIC (300 mil) (TC510) Example: XXXXXXXXXXXXXXXXXX YYWWNNN XXXXXXXXXXXXXXXXXX 0818256 TC510COG ^^ YYWWNNN XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX 0818256 TC510CPF

Updated Section 10.0 “Packaging Informa- tion”. Revision D (January 2006)
Undocumented changes. Revision C (January 2004)
Undocumented changes. Revision B (May 2002)
Undocumented changes. Revision A (March 2001)
Initial release of this document.

© 2008 Microchip Technology Inc. DS21428E-page 35 TC500/A/510/514 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX PackageTemperature Range Device Device TC500 16 Bit Analog Processor TC500A 16 Bit Analog Processor TC510 Precision Analog Front End TC514 Precision Analog Front End Temperature Range C = 0°C to +70°C (Commercial) I = 25°C to +85°C (Industrial) Package JE = Ceramic Dual In-line, (300 mil Body), 16-lead PE = Plastic DIP , (300 mil Body), 16-lead OE = Plastic SOIC, (300 mil Body), 16-lead OE713 = Plastic SOIC, (300 mil Body), 16-lead (Tape and Reel) PF = Plastic DIP , (300 mil Body), 24-lead OG = Plastic SOIC, (300 mil Body), 24-lead OG713 = Plastic SOIC, (300 mil Body), 24-lead (Tape and Reel) PJ = Plastic DIP , (300 mil Body), 28-lead OI = Plastic SOIC, (300 mil Body), 28-lead OI713 = Plastic SOIC, (300 mil Body), 28-lead (Tape and Reel) Examples: a) TC500ACOE: Commercial Temp., 16LD SOIC package. b) TC500ACOE713: Commercial Temp., 16LD SOIC package, Tape and Reel. c) TC500ACPE: Commercial Temp., 16LD PDIP package. d) TC500AIJE: Industrial Temp., 16LD CERDIP package. a) TC500COE: Commercial Temp., 16LD SOIC package. b) TC500COE713: Commercial Temp., 16LD SOIC package, Tape and Reel. c) TC500CPE: Commercial Temp., 16LD PDIP package. d) TC500IJE: Industrial Temp., 16LD CERDIP package. a) TC510COG: Commercial Temp., 24LD PDIP package. b) TC510COG713: Commercial Temp., 24LD PDIP package, Tape and Reel. c) TC510CPF: Commercial Temp., 24LD PDIP package. a) TC514COI: Commercial Temp., 28LD PDIP package. b) TC514COI713: Commercial Temp., 28LD PDIP package, Tape and Reel. c) TC514CPJ: Commercial Temp., 28LD PDIP package.

© 2008 Microchip Technology Inc. DS21428E-page 37 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application me ets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY , PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE . Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting fr om such use. No licenses are conveyed, implicitly or ot herwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC 32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices:

Microchip products meet the specification cont ained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal meth ods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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Product Information

TC510COI specifications and overview.

Summary

Precision Analog Front Ends with Dual Slope ADC 2008

Description

Precision Analog Front Ends with Dual Slope ADC 2008

Source title TC510COI Datasheet(PDF) - Microchip Technology

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