TC500_06 MICROCHIP | Alldatasheet

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© 2006 Microchip Technology Inc. DS21428D-page 1 TC500/A/510/514 Features:

  • Precision (up to 17 bits) A/D Converter “Front End”
  • 3-Pin Control Interface to Microprocessor
  • Flexible: User Can Trade-off Conversion Speed for Resolution
  • Single-Supply Operation (TC510/TC514)
  • 4 Input, Differential Analog MUX (TC514)
  • Automatic Input Voltage Polarity Detection
  • Low Power Dissipation: - (TC500/TC500A): 10 mW - (TC510/TC514): 18 mW
  • Wide Analog Input Range: - ±4.2V (TC500A/TC510)
  • Directly Accepts Bipolar and Differential Input Signals Applications:
  • Precision Analog Signal Processor
  • Precision Sensor Interface
  • High Accuracy DC Measurements General Description: TheTC500/A/510/514 family are precision analog front ends that implement dual slope A/D converters having a maximum resolution of 17 bits plus sign. As a minimum, each device contains the integrator, zero crossing comparator and processor interface logic. The TC500 is the base (16-bit max) device and requires both positive and negative power supplies. The TC500A is identical to the TC500 with the exception that it has improved linearity, allowing it to operate to a maximum resolution of 17 bits. The TC510 adds an on- board negative power supply converter for single- supply operation. The TC514 adds both a negative power supply converter and a 4-input differential analog multiplexer. Each device has the same processor control interface consisting of 3 wires: control inputs (A and B) and zero- crossing comparator output (CMPTR). The processor manipulates A, B to sequence the TC5XX through four phases of conversion: auto-zero, integrate, de-inte- grate and integrator zero. During the auto-zero phase, offset voltages in the TC5XX are corrected by a closed loop feedback mechanism. The input voltage is applied to the integrator during the integrate phase. This causes an integrator output dv/dt directly proportional to the magnitude of the input voltage. The higher the input voltage, the greater the magnitude of the voltage stored on the integrator during this phase. At the start of the de-integrate phase, an external voltage reference is applied to the integrator and, at the same time, the external host processor starts its on-board timer. The processor maintains this state until a transition occurs on the CMPTR output, at which time the processor halts its timer. The resulting timer count is the converted analog data. Integrator zero (the final phase of conversion) removes any residue remaining in the integrator in preparation for the next conversion. The TC500/A/510/514 offer high resolution (up to 17 bits), superior 50/60 Hz noise rejection, low-power operation, minimum I/O connections, low input bias currents and lower cost compared to other converter technologies having similar conversion speeds. Precision Analog Front Ends

© 2006 Microchip Technology Inc. Package Types Typical Application CMPTR OUT A DGND B VDD VIN+ VIN– VREF+ BUF VSS CINT ACOM VREF− CREF+ CREF– CAZ TC500/ TC500A 16-Pin PDIP/SOIC/CERDIP VOUT– CAP– DGND A B CREF– CINT CAZ BUF ACOM CH4– CH3– CH2– TC514 CREF+ VREF– VREF+ VDD OSC CMPTR OUT CAP+ CH1– N/C CH1+ CH2+ CH3+ CH4+ 28-Pin PDIP/SOIC 24-Pin PDIP/SOIC TC510 CAP– DGND A B VDD OSC CMPTR OUT VIN+ VIN– N/C N/C CAP+ CREF– CINT CAZ BUF ACOM N/C N/C N/C VOUT– CREF+ VREF– VREF+ Level Shift Control Logic Analog Switch Control Signals ACOM VREF+ BUF CAZ Buffer Integrator SWR SWIZ CMPTR 1 CMPTR 2 CMPTR Output DGND Control Logic SW1 TC500 TC500A TC510 TC514 CREF CREF+ SWR CREF- CAZ RINT CINT CINT SWRI- SWRI- SWRI+ SWRI- SWZ SWI SWZ VSS OSC Phase Decoding Logic Polarity Detection DC-TO-DC Converter (TC510 & TC514) A B Zero Integrator Output Auto-Zero Signal Integrate De-integrate VREF- VOUT- COUT- 1.0 μF 1.0 μF VSS SWI B A DIF. MUX (TC514) CH1+ CH2+ CH3+ CH4+ CH1- CH2- CH3- CH4- CAP- CAP+ (TC500 TC500A) Converter Sate

© 2006 Microchip Technology Inc. DS21428D-page 3 TC500/A/510/514 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† TC510/TC514 Positive Supply Voltage TC500/TC500A Supply Voltage TC500/TC500A Positive Supply Voltage TC500/TC500A Negative Supply Voltage Voltage on OSC: Ambient Operating Temperature Range: † Stresses above those listed under “Absolute Maxi- mum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS = ±5V. CAZ = CREF = 0.47 μF. Parameters Sym TA = +25°C TA = 0°C to 70°C Units Conditions Min. Typ. Max. Min. Typ. Max. Analog Resolution μV Note 1 Zero-scale Error with Auto-zero Phase ZSE 0.005 0.005 0.012 % F.S. TC500/TC510/TC514 0.003 0.003 0.009 TC500A End Point Linearity ENL 0.005 0.015 0.015 0.060 % F.S. TC500/TC510/TC514 0.010 0.010 0.045 % F.S. Note 1, Note 2, TC500A Best-Case Straight Line Linearity NL 0.003 0.008 % F.S. TC500/TC510/TC514, Note 1, Note 2 0.005 % F.S. TC500A Zero-scale Temp. Coefficient ZSTC μV/°C Over Operating Temperature Range Full-scale Symmetry Error (Rollover Error) SYE 0.01 0.03 % F.S. Note 1 Full-scale Temperature Coefficient FSTC ppm/°C Over Operating Temperature Range; External Reference TC = 0 ppm/°C Input Current IIN pA VIN = 0V Common Mode Voltage Range VCMR VSS + 1.5 VDD – 1.5 VSS + 1.5 VDD – 1.5 V Integrator Output Swing VSS + 0.9 VDD – 0.9 VSS + 0.9 VSS + 0.9 V Analog Input Signal Range VSS + 1.5 VDD – 1.5 VSS + 1.5 VSS + 1.5 V ACOM = GND = 0V Note Integrate time ≥ 66 msec, auto-zero time ≥ 66 msec, VINT (peak) ≈ 4V. End point linearity at ±1/4, ±1/2, ±3/4 F.S. after full-scale adjustment. Rollover error is related to CINT, CREF, CAZ characteristics.

© 2006 Microchip Technology Inc. Voltage Reference Range VREF VSS +1 VDD – 1 VSS +1 VDD – 1 V VREF- VREF+ Digital Comparator Logic 1, Output High VOH V ISOURCE = 400 μA Comparator Logic 0, Output Low VOL 0.4 0.4 V ISINK = 2.1 mA Logic 1, Input High Voltage VIH 3.5 3.5 V Logic 0, Input Low Voltage VIL V Logic Input Current IL 0.3 μA Logic ‘1’ or ‘0’ Comparator Delay tD μsec Multiplexer (TC514 Only) Maximum Input Voltage -2.5 2.5 -2.5 2.5 V VDD = 5V Drain/Source ON Resistance RDSON kΩ VDD = 5V Power (TC510/TC514 Only) Supply Current IS 1.8 2.4 3.5 mA VDD = 5V, A = 1, B = 1 Power Dissipation PD mW VDD = 5V Positive Supply Operating Voltage Range VDD 4.5 5.5 4.5 5.5 V Operating Source Resistance ROUT 100 Ω IOUT = 10 mA Oscillator Frequency 100 kHz Note 1 Maximum Current Out IOUT -10 -10 mA VDD = 5V Power (TC500/TC500A Only) Supply Current IS 1.5 2.5 mA VS = ±5V, A = B = 1 Power Dissipation PD mW VDD = 5V, VSS = -5V Positive Supply Operating Range VDD 4.5 7.5 4.5 7.5 V Negative Supply Operating Range VSS -4.5 -7.5 - 4.5 -7.5 V DC CHARACTERISTICS (CONTINUED) = ±5V. CAZ = CREF = 0.47 μF. Parameters Sym TA = +25°C TA = 0°C to 70°C Units Conditions Min. Typ. Max. Min. Typ. Max. Note Integrate time ≥ 66 msec, auto-zero time ≥ 66 msec, VINT (peak) ≈ 4V. End point linearity at ±1/4, ±1/2, ±3/4 F.S. after full-scale adjustment. Rollover error is related to CINT, CREF, CAZ characteristics.

© 2006 Microchip Technology Inc. 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin No. Symbol Function TC500, TC500A TC510 TC514 CINT Integrator output. Integrator capacitor connection. Not Used Not Used VSS Negative power supply input (TC500/TC500A only). CAZ Auto-zero input. The auto-zero capacitor connection. BUF Buffer output. The Integrator capacitor connection. ACOM This pin is grounded in most applications. It is recommended that ACOM and the input common pin (Ven- or CHn-) be within the analog Common Mode Range (CMR). CREF- Input. Negative reference capacitor connection. CREF+ Input. Positive reference capacitor connection. VREF- Input. External voltage reference (-) connection. VREF+ Input. External voltage reference (+) connection. Not Used VIN- Negative analog input. Not Used VIN+ Positive analog input. A Input. Converter phase control MSB. (See input B.) B Input. Converter phase control LSB. The states of A, B place the TC5XX in one of four required phases. A conversion is complete when all four phases have been executed: Phase control input pins: AB = 00: Integrator zero 01: Auto-zero 10: Integrate 11: De-integrate CMPTR OUT Zero crossing comparator output. CMPTR is high during the integration phase when a positive input voltage is being integrated and is low when a negative input voltage is being integrated. A high-to-low transition on CMPTR signals the processor that the De-integrate phase is completed. CMPTR is undefined during the auto-zero phase. It should be monitored to time the integrator zero phase. DGND Input. Digital ground. VDD Input. Power supply positive connection. CAP+ Input. Negative power supply converter capacitor (+) connection. CAP- Input. Negative power supply converter capacitor (-) connection. VOUT- Output. Negative power supply converter output and reservoir capacitor connection. This output can be used to power other devices in the circuit requiring a negative bias voltage. OSC Oscillator control input. The negative power supply converter normally runs at a frequency of 100 kHz. The converter oscillator frequency can be slowed down (to reduce quiescent current) by connecting an external capacitor between this pin and VDD (see Section 2.0 “Typical Performance Curves”). CH1+ Positive analog input pin. MUX channel 1. CH1- Negative analog input pin. MUX channel 1. CH2+ Positive analog input pin. MUX channel 2. CH2- Negative analog input pin. MUX channel 2. CH3+ Positive analog input pin. MUX channel 3. CH3- Negative analog input pin. MUX channel 3. CH4+ Positive analog input pin. MUX channel 4. CH4- Negative analog input pin. MUX channel 4 Multiplexer input channel select input LSB (see A1). Multiplexer input channel select input MSB. Phase control input pins: A1, A0 = 00 = Channel 1 01 = Channel 2 10 = Channel 3 11 = Channel 4

© 2006 Microchip Technology Inc. FIGURE 4-3: Basic Dual Slope Converter. Phase Control Comparator Integrator Output Integrator CINT Analog Input (VIN) Switch Driver Ref Voltage Control Logic Polarity Control I/O Timer Counter ROM RAM Microcomputer A B CMPTR Out VSUPPLY TINT TC510 VINT VIN ≈ VREF VIN ≈ 1/2 VREF TDEINT RINT VINT

© 2006 Microchip Technology Inc. DS21428D-page 9 TC500/A/510/514 5.0 TC500/A/510/514 CONVERTER OPERATION The TC500/A/510/514 incorporates an auto-zero and Integrator phase in addition to the input signal Integrate and reference De-integrate phases. The addition of these phases reduce system errors, calibration steps and shorten overrange recovery time. A typical measurement cycle uses all four phases in the following order: Auto-zero. Input signal integration. Reference de-integration. Integrator output zero. The internal analog switch status for each of these phases is summarized in Table 5-1. This table references the Typical Application. TABLE 5-1: INTERNAL ANALOG GATE STATUS 5.1 Auto-zero Phase (AZ) During this phase, errors due to buffer, integrator and comparator offset voltages are nulled out by charging CAZ (auto-zero capacitor) with a compensating error voltage. The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to analog common. The reference capacitor is charged to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the capacitor (CAZ) with a voltage to compensate for buffer amplifier, integrator and comparator offset voltages. 5.2 Analog Input Signal Integration Phase (INT) The TC5XX integrates the differential voltage between the VIN+ and VIN– inputs. The differential voltage must be within the device’s Common mode range VCMR. The input signal polarity is normally checked via software at the end of this phase: CMPTR = 1 for positive polarity; CMPTR = 0 for negative polarity. 5.3 Reference Voltage De-integration Phase (DINT) The previously charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero. An externally-provided, precision timer is used to measure the duration of this phase. The resulting time measurement is proportional to the magnitude of the applied input voltage. 5.4 Integrator Output Zero Phase (IZ) This phase ensures the integrator output is at 0V when the auto-zero phase is entered, and that only system offset voltages are compensated. This phase is used at the end of the reference voltage de-integration phase and MUST be used for ALL TC5XX applications having resolutions of 12-bits or more. If this phase is not used, the value of the auto-zero capacitor (CAZ) must be about 2 to 3 times the value of the integration capacitor (CINT) to reduce the effects of charge sharing. The inte- grator output zero phase should be programmed to operate until the output of the comparator returns high. The overall timing system is shown in Figure 5-1. Conversion Phase SWI SWR+ SWR- SWZ SWR SW1 SWIZ Auto-zero (A = 0, B = 1) Closed Closed Closed Input Signal Integration (A = 1, B = 0) Closed Reference Voltage De-integration (A =1, B = 1) Closed Closed Integrator Output Zero (A = 0, B = 0) Closed Closed Closed * Assumes a positive polarity input signal. SW– RI would be closed for a negative input signal.

© 2006 Microchip Technology Inc. FIGURE 5-1: Typical Dual Slope A/D Converter System Timing. Auto-zero Integrate Full-scale Input Reference De-integrate Overshoot Integrator Output Zero Converter Status TTIME Integrator Voltage VINT Comparator Output AB Inputs Controller Operation Notes: Comparator Delay Begin Conversion with Auto-Zero Phase (Positive Input Shown) Sample Input Polarity The length of this phase is chosen almost arbitrarily but needs to be long enough to null out worst case errors (see text). Minimizing Overshoot will Minimize I.O.Z. Time Ready for Next Conversion (Auto-Zero is Idle State) Time Input Integration Phase Capture De-integration Time Integrator Output Zero Phase Complete Undefined A = 0 B = 1 A = 1

0 For Negative Input

1 For Positive Input

B = 0 B = 1 B = 0 A = 1 A = 0 Typically = TINT TINT A B Comparator Delay + Processor Latency

© 2006 Microchip Technology Inc. 7.0 TYPICAL APPLICATIONS 7.1 Component Value Selection The procedure outlined below allows the user to arrive at values for the following TC5XX design variables: Integration Phase Timing. Integrator Timing Components (RINT, CINT). Auto-zero and Reference Capacitors. Voltage Reference. 7.2 Select Integration Time Integration time must be picked as a multiple of the period of the line frequency. For example, TINT times of 33 msec, 66 msec and 132 msec maximize 60 Hz line rejection. 7.3 DINT and IZ Phase Timing The duration of the DINT phase is a function of the amount of voltage stored on the integrator during TINT and the value of VREF. The DINT phase must be initiated immediately following INT and terminated when an inte- grator output zero-crossing is detected. In general, the maximum number of counts chosen for DINT is twice that of INT (with VREF chosen at VIN(MAX) /2). 7.4 Calculate Integrating Resistor (RINT) The desired full-scale input voltage and amplifier output current capability determine the value of RINT. The buffer and integrator amplifiers each have a full-scale current of 20 μA. The value of RINT is, therefore, directly calculated in the following equation: EQUATION 7-1: 7.5 Select Reference (CREF) and Auto- zero (CAZ) Capacitors CREF and CAZ must be low leakage capacitors (such as polypropylene). The slower the conversion rate, the larger the value CREF must be. Recommended capacitors for CREF and CAZ are shown in Table 7-1. Larger values for CAZ and CREF may also be used to limit rollover errors. TABLE 7-1: CREF AND CAZ SELECTION 7.6 Calculate Integrating Capacitor (CINT) The integrating capacitor must be selected to maximize integrator output voltage swing. The integrator output voltage swing is defined as the absolute value of VDD Using the 20 μA buffer maximum output current, the value of the integrating capacitor is calculated using the following equation. EQUATION 7-2: It is critical that the integrating capacitor has a very low dielectric absorption. Polypropylene capacitors are an example of one such dialectic. Polyester and poly- bicarbonate capacitors may also be used in less critical applications. Table 7-2 summarizes recommended capacitors for CINT. TABLE 7-2: RECOMMENDED CAPACITOR FOR CINT 7.7 Calculate VREF The reference de-integration voltage is calculated using the following equation: EQUATION 7-3: Where: VIN(MAX) = Maximum input voltage (full count voltage) RINT = Integrating Resistor (in MΩ) For loop stability, RINT should be ≥ 50 kΩ. RINT in MΩ VIN MAX Conversions Per Second Typical Value of CREF, CAZ (μF) Suggested* Part Number 0.1 SMR5 104K50J01L4 2 to 7 0.22 SMR5 224K50J02L4 2 or less 0.47 SMR5 474K50J04L4 * Manufactured by Evox Rifa, Inc. Value Suggested Part Number* 0.1 SMR5 104K50J01L4 0.22 SMR5 224K50J02L4 0.33 SMR5 334K50J03L4 0.47 SMR5 474K50J04L4 * Manufactured by Evox Rifa, Inc. Where: TINT = Integration Period VS = IVDDI or IVSSI, whichever is less (TC500/A) VS = IVDDI (TC510, TC514) CINT TINT ) 20 10 6 VS 0.9 VREF VS 0.9 ) CINT ) RINT

2 RINT

© 2006 Microchip Technology Inc. DS21428D-page 15 TC500/A/510/514 9.0 DESIGN EXAMPLES Refer to Figures 9-1 to 9-4. EQUATION 9-1: Given: Required Resolution: 16 bits (65,536 counts). Maximum VIN: ±2V Power Supply Voltage: +5V

60 Hz System

Step 1. Pick integration time (tINT) as a multiple of the line frequency: 1/60 Hz = 16.6 msec. Use 4x line frequency. = 66 msec Step 2. Calculate RINT: RINT = VIN(MAX) /20 μA 2 /20 μA = 100 kΩ Step 3. Calculate CINT for maximum (4V) integrator output swing. CINT = (tINT) (20 x 10 –6) / (VS - 0.9) = 0.32 μF (use closest value: 0.33 μF) Note: Microchip recommended capacitor: Evox Rifa p/n: 5MR5 334K50J03L4. Step 4. Choose CREF and CAZ based on conversion rate. Conversions/sec: = 1/(TAZ + TINT + 2 TINT + 2 msec) = 1/(66 msec +66 msec +132 msec +2 msec) = 3.7 conversions/sec From which CAZ = CREF = 0.22 μF (see Table 7-1) Note: Microchip recommended capacitor: Evox Rifa p/n: 5MR5 224K50J02L4 Step 5. Calculate VREF: VREF VS 0.9 ) CINT ) RINT

2 TINT

4.1 ) 0.33 1 6 ) 105 2 0.66 1.025

© 2006 Microchip Technology Inc. DS21428D-page 17 TC500/A/510/514 FIGURE 9-3: TC510 To IBM® Compatible Printer Port. PC Printer Port PORT 0378 Hex Input +5V 10 kΩ 10 kΩ 100 kΩ 100 kΩ 1 μF 1 μF CAP- DGND VOUT- VDD A B CINT CAZ BUF ACOM TC510 CREF+ VIN+ CAP+ CMPTR 0.22 μF 0.22 μF 0.01 μF 0.01 μF 1 μF 0.33 μF MCP1525 CREF- VREF+ VREF- VIN-

© 2006 Microchip Technology Inc. FIGURE 9-4: TC514 To IBM® Compatible Printer Port. IBM® Printer Port Port 0378 Hex +5V 10 kΩ 100 kΩ 1 μF 1 μF CAP– DGND VOUT VDD A B CREF+ TC514 BUF 0.22 μF 10 kΩ 10 kΩ 0.22 μF 0.01 μF 0.33 μF CH1+ Input 1 Input 2 Input 3 Input 4 CAP+ CREF- VREF+ VREF- CAZ CINT ACOM CH1– CH2+ CH2– CH3+ CH3– CH4+ CH4– CMPTR Analog Mux Control Logic MCP1525

© 2006 Microchip Technology Inc. DS21428D-page 19 TC500/A/510/514 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 16-Lead PDIP (300 mil) Example: 16-Lead SOIC (300 mil) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN XXXXXXXXXXXXX YYWWNNN TC500CPE 0441256 XXXXXXXXXXXXX TC500ACOE 0441256 Legend: XX...X Customer specific information* YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for cus- tomer specific information. Standard marking consists of Microchip part number, year code, week code, traceability code. For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. 16-Lead CERDIP (300 mil) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN TC500AIJE 0441256

© 2006 Microchip Technology Inc. Package Marking Information (Continued) 28-Lead PDIP (300 mil) Example: 28-Lead SOIC (300 mil) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN TC514CPJ 0441256 XXXXXXXXXXXXX YYWWNNN XXXXXXXXXXXXX XXXXXXXXXXXXX 0441256 TC514COI 24-Lead PDIP (300 mil) Example: 24-Lead SOIC (300 mil) Example: YYWWNNN XXXXXXXXXXXXX 0441256 TC510CPF XXXXXXXXXXXXX YYWWNNN XXXXXXXXXXXXX 0441256 TC510COG

© 2006 Microchip Technology Inc. DS21428D-page 21 TC500/A/510/514 16-Lead Ceramic Dual In-line (JE) – 300 mil (CERDIP) 10.41 9.14 8.25 .410 .360 .325 eB Overall Row Spacing 0.53 0.46 0.38 .021 .018 .015 B Lower Lead Width 1.65 1.40 1.14 .065 .055 .045 Upper Lead Width 0.36 0.30 0.20 .014 .012 .008 c Lead Thickness 5.08 4.14 3.18 .200 .163 .125 L Tip to Seating Plane 19.81 19.30 19.10 .780 .760 .752 D Overall Length 7.52 7.32 7.11 .296 .288 .280 Ceramic Pkg. Width 8.25 7.75 7.37 .325 .305 .290 E Shoulder to Shoulder Width 1.02 0.76 0.38 .040 .030 .015 Standoff § 5.08 4.57 4.06 .200 .180 .160 A Top to Seating Plane 2.54 .100 p Pitch n Number of Pins MAX NOM MIN MAX NOM MIN Dimension Limits MILLIMETERS INCHES* Units JEDEC Equivalent: MS-030 Drawing No. C04-003 *Controlling Parameter D n c eB E p L B A

© 2006 Microchip Technology Inc. 16-Lead Plastic Dual In-line (PE) – 300 mil (PDIP) D n c β eB E α p L B A β Mold Draft Angle Bottom α Mold Draft Angle Top 10.92 9.40 7.87 .430 .370 .310 eB Overall Row Spacing 0.56 0.46 .036 .022 .018 .014 B Lower Lead Width 1.78 1.46 1.14 .070 .058 .045 Upper Lead Width 0.38 0.29 0.20 .015 .012 .008 c Lead Thickness 3.43 3.30 3.18 .135 .130 .125 L Tip to Seating Plane 19.30 19.05 18.80 .760 .750 .740 D Overall Length 6.60 6.35 6.10 .260 .250 .240 Molded Package Width 8.26 7.94 7.62 .325 .313 .300 E Shoulder to Shoulder Width 0.38 .015 Base to Seating Plane 3.68 3.30 2.92 .145 .130 .115 Molded Package Thickness 4.32 3.94 3.56 .170 .155 .140 A Top to Seating Plane 2.54 .100 p Pitch n Number of Pins MAX NOM MIN MAX NOM MIN Dimension Limits MILLIMETERS INCHES* Units Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Notes: JEDEC Equivalent: MS-001 Revised 07-21-05 * Controlling Parameter Drawing No. C04-017

© 2006 Microchip Technology Inc. DS21428D-page 23 TC500/A/510/514 16-Lead Plastic Small Outline (OE) – Wide, 300 mil (SOIC) Foot Angle φ β Mold Draft Angle Bottom α Mold Draft Angle Top 0.51 0.42 0.36 .020 .017 .014 B Lead Width 0.33 0.28 0.23 .013 .011 .009 c Lead Thickness 1.27 0.84 0.41 .050 .033 .016 L Foot Length 0.74 0.50 0.25 .029 .020 .010 h Chamfer Distance 10.49 10.30 10.10 .413 .406 .398 D Overall Length 7.59 7.49 7.39 .299 .295 .291 Molded Package Width 10.67 10.34 10.01 .420 .407 .394 E Overall Width 0.30 0.20 0.10 .012 .008 .004 Standoff 2.39 2.31 2.24 .094 .091 .088 Molded Package Thickness 2.64 2.50 2.36 .104 .099 .093 A Overall Height 1.27 .050 p Pitch n Number of Pins MAX NOM MIN MAX NOM MIN Dimension Limits MILLIMETERS INCHES* Units L β c φ h 45° D p n B E α A * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-102 § Significant Characteristic

© 2006 Microchip Technology Inc. 24-Lead Skinny Plastic Dual In-line (PF) – 300 mil (PDIP) D n c eB E β α p L B A β Mold Draft Angle Bottom α Mold Draft Angle Top 10.92 9.40 7.87 .430 .370 .310 eB Overall Row Spacing 0.56 0.46 0.36 .022 .018 .014 B Lower Lead Width 1.52 1.33 1.14 .060 .053 .045 Upper Lead Width 0.38 0.29 0.20 .015 .012 .008 c Lead Thickness 3.30 3.18 3.05 .130 .125 .120 L Tip to Seating Plane 31.88 31.75 31.62 1.255 1.250 1.245 D Overall Length 6.60 6.35 6.10 .260 .250 .240 Molded Package Width 8.26 7.87 7.49 .325 .310 .295 E Shoulder to Shoulder Width 0.38 .015 Base to Seating Plane 3.68 3.30 2.92 .145 .130 .115 Molded Package Thickness 4.06 3.81 3.56 .160 .150 .140 A Top to Seating Plane 2.54 .100 p Pitch n Number of Pins MAX NOM MIN MAX NOM MIN Dimension Limits MILLIMETERS INCHES* Units Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Notes: JEDEC Equivalent: MS-001 AF Drawing No. C04-043 * Controlling Parameter Revised 09-14-05

© 2006 Microchip Technology Inc. DS21428D-page 25 TC500/A/510/514 24-Lead Plastic Small Outline (OG) – Wide, 300 mil (SOIC) D e n B E L c β h φ α A h Foot Angle φ 15° 15° β Mold Draft Angle Bottom 15° 15° α Mold Draft Angle Top 0.51 0.31 .020 .012 B Lead Width 0.33 0.20 .013 .008 c Lead Thickness 1.27 0.40 .050 .016 L Foot Length 0.75 0.25 .030 .010 h Chamfer Distance

15.40 BSC

.607 BSC D Overall Length

7.50 BSC

.295 BSC Molded Package Width

10.30 BSC

.406 BSC E Overall Width 0.30 0.10 .012 .004 Standoff 2.55 2.05 .100 .081 Molded Package Thickness 2.65 2.35 .104 .093 A Overall Height

1.27 BSC

.050 BSC e Pitch n Number of Pins MAX NOM MIN MAX NOM MIN Dimension Limits MILLIMETERS* INCHES Units Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Notes: JEDEC Equivalent: MS-013 AD Revised 07-19-05 * Controlling Parameter per JEDEC MS-103 Revision C. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M Drawing No. C04-025

© 2006 Microchip Technology Inc. 28-Lead Skinny Plastic Dual In-line (PJ) – 300 mil (PDIP) β Mold Draft Angle Bottom α Mold Draft Angle Top 10.92 8.89 8.13 .430 .350 .320 eB Overall Row Spacing 0.56 0.48 0.41 .022 .019 .016 B Lower Lead Width 1.65 1.33 1.02 .065 .053 .040 Upper Lead Width 0.38 0.29 0.20 .015 .012 .008 c Lead Thickness 3.43 3.30 3.18 .135 .130 .125 L Tip to Seating Plane 35.18 34.67 34.16 1.385 1.365 1.345 D Overall Length 7.49 7.24 6.99 .295 .285 .275 Molded Package Width 8.26 7.87 7.62 .325 .310 .300 E Shoulder to Shoulder Width 0.38 .015 Base to Seating Plane 3.43 3.30 3.18 .135 .130 .125 Molded Package Thickness 4.06 3.81 3.56 .160 .150 .140 A Top to Seating Plane 2.54 .100 p Pitch n Number of Pins MAX NOM MIN MAX NOM MIN Dimension Limits MILLIMETERS INCHES* Units D n c eB β E α p L B A Notes: JEDEC Equivalent: MO-095 Drawing No. C04-070 * Controlling Parameter Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. § Significant Characteristic

© 2006 Microchip Technology Inc. DS21428D-page 27 TC500/A/510/514 28-Lead Plastic Small Outline (OI) – Wide, 300 mil (SOIC) Foot Angle Top φ β Mold Draft Angle Bottom α Mold Draft Angle Top 0.51 0.42 0.36 .020 .017 .014 B Lead Width 0.33 0.28 0.23 .013 .011 .009 c Lead Thickness 1.27 0.84 0.41 .050 .033 .016 L Foot Length 0.74 0.50 0.25 .029 .020 .010 h Chamfer Distance 18.08 17.87 17.65 .712 .704 .695 D Overall Length 7.59 7.49 7.32 .299 .295 .288 Molded Package Width 10.67 10.34 10.01 .420 .407 .394 E Overall Width 0.30 0.20 0.10 .012 .008 .004 Standoff 2.39 2.31 2.24 .094 .091 .088 Molded Package Thickness 2.64 2.50 2.36 .104 .099 .093 A Overall Height 1.27 .050 p Pitch n Number of Pins MAX NOM MIN MAX NOM MIN Dimension Limits MILLIMETERS INCHES* Units D p n B E L c β 45° h φ α A * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052 § Significant Characteristic

© 2006 Microchip Technology Inc. 10.2 Product Tape and Reel Specifications Component Taping Orientation for 16-Pin SOIC (Wide) Devices W Pin 1 User Direction of Feed Standard Reel Component Orientation for 713 Suffix Device P Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 16-Pin SOIC (W) 16 mm 12 mm 1000 13 in Carrier Tape, Number of Components Per Reel and Reel Size Component Taping Orientation for 24-Pin SOIC (Wide) Devices Pin 1 User Direction of Feed Standard Reel Component Orientation for 713 Suffix Device W P Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 24-Pin SOIC (W) 24 mm 12 mm 1000 13 in Carrier Tape, Number of Components Per Reel and Reel Size

© 2006 Microchip Technology Inc. DS21428D-page 29 TC500/A/510/514 Product Tape and Reel Specifications (Continued) Component Taping Orientation for 28-Pin SOIC (Wide) Devices Pin 1 User Direction of Feed Standard Reel Component Orientation for 713 Suffix Device W P Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 28-Pin SOIC (W) 24 mm 12 mm 1000 13 in Carrier Tape, Number of Components Per Reel and Reel Size

© 2006 Microchip Technology Inc. NOTES:

© 2006 Microchip Technology Inc. DS21428D-page 31 TC500/A/510/514 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Sales and Support PART NO. X /XX Package Temperature Range Device Device TC500

16 Bit Analog Processor

TC500A 16 Bit Analog Processor TC510 Precision Analog Front End TC514 Precision Analog Front End Temperature Range C 0°C to +70°C (Commercial) I -25°C to +85°C (Industrial) Package: JE = Ceramic Dual In-line, (300 mil Body), 16-lead PE = Plastic DIP, (300 mil Body), 16-lead OE = Plastic SOIC, (300 mil Body), 16-lead OE713 = Plastic SOIC, (300 mil Body), 16-lead (Tape and Reel) PF = Plastic DIP, (300 mil Body), 24-lead OG = Plastic SOIC, (300 mil Body), 24-lead OG713 = Plastic SOIC, (300 mil Body), 24-lead (Tape and Reel) PJ = Plastic DIP, (300 mil Body), 28-lead OI = Plastic SOIC, (300 mil Body), 28-lead OI713 = Plastic SOIC, (300 mil Body), 28-lead (Tape and Reel) Examples: TC500ACOE: Commercial Temp., 16LD SOIC package. TC500ACOE713: Commercial Temp., 16LD SOIC package, Tape and Reel. TC500ACPE: Commercial Temp., 16LD PDIP package. TC500AIJE: Industrial Temp., 16LD CERDIP package. TC500COE: Commercial Temp., 16LD SOIC package. TC500COE713: Commercial Temp., 16LD SOIC package, Tape and Reel. TC500CPE: Commercial Temp., 16LD PDIP package. TC500IJE: Industrial Temp., 16LD CERDIP package. TC510COG: Commercial Temp., 24LD PDIP package. TC510COG713: Commercial Temp., 24LD PDIP package, Tape and Reel. TC510CPF: Commercial Temp., 24LD PDIP package. TC514COI: Commercial Temp., 28LD PDIP package. TC514COI713: Commercial Temp., 28LD PDIP package, Tape and Reel. TC514CPJ: Commercial Temp., 28LD PDIP package. Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

© 2006 Microchip Technology Inc. NOTES:

© 2006 Microchip Technology Inc. DS21428D-page 33 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and Zena are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

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