TC5090AP | DigiCamel IC Datasheet

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C’MOS DIGITAL INTEGRATED CIRCUIT T = SILICON MONOLITHIC — TCS5O90AP PENTAPHASIC INTEGRATION 8-BIT A/D CONVERTER [The TC5090AP is a pentaphase integration 8-bit A/D converter of high precision and low power consumption, which is mounted in 2 compact 16-pin standard package. IThe 8-bit output data can be taken out in the form of time-shared higher order 4 bits and lower order 4 bits| lon four 3-state data outputs. This output system is designed specifically considering interface to 4-bit CPU. a8 The features of low power consumption and compact a outline are applicable to battery-driven small-sized instruments. DIF 16(3D16A-P) " TREATURES: . » High precision PEL LSB MAX. yo + Low power consumption: 10mWv(Typ.) @(¢2D°2) 4) + Single power supply : Vpp=Stl.sv *OSC=?MHz PIN ASSIGNHERT + High-speed conversion: 2mS(Max.) @fosc=1.5MHz + Reference clock oscillation circuit contained (CR oscillation) . 3-state output with output latch . TTL/CMOS compatible digital Input/Output + Offset automatic correction APPLICATIONS: . Various control instruments (for temperature, humidity, pressure, etc.) . Home electric appliances : Electric wiring apparatuses Rens; ek vo : Battery-driven instruments neen [2 ask wo ams aL para 5 sto Je 15L pata 2 itz Js sel ara 2 ABSOLUTE MAXIMUM RATINGS rity te ab para o y : IDC Supply Voltage Vpp__ | Vss-0.5~Vgs+8 sae Sf o8ery Input Voltage Vin | Vsg-0.5 ~Vppt0.5 age (TOP VIEW) Output Voltage Vss-0.5~Vppt0.5 Operating Temperature| _ . Ronee Topr -40~85 c Storage Temperature ° Range Tetg -65~150 Cc . 577

Fon | SYMBOL NAME & FUNCTION [Fo SYMBOL NAME & FUNCTION (Read Enable) osc in| 1/0 for reference clock Data read signal. oscillation. Clock oscillation as can be made by means of external] 1 "HM: outpee O~3 can be registance. Clock can be sup- up i plied from outside through IL": The output above is at P high innodence. 10 |osc our] input of OSC IN. (Read Select) Input to select the higher [11 |paTao _. order 4 bits or the lower ip Tostat (3-state Parallel Data Outputs) output. 13 |DATA2| The data 0 is LSB, and the "gl: Output of the higher ~ data 3 is MSB. order 4 bits. "L": Output of the lower 14 {DATA 3 | order 4 bits. a (Analog Input) (End of Conversion) 3 | ATN | analog input terminals. Conversion ending signal. EOC goes to "L" level at the Input voltage range is Vpp ~Vss- fall of STC, and returns to 15 | BOC | "H" level at the end of (Start Conversion) conversion. 4 | sre | Conversion starting signal. Conversion starts at the fall- ing edge. 5 | INT 1 | (integrator Input, Integrator —|— Junction, Integrator Output) (Power Supply) external resistor Ry and ae |v, the external capacitor Cy. pp Vs (Ground) Normally OV 579

(1) System Description (Pentaphasic Integration) The operation of the TCSO90AP is composed of the correction cycle and the conversion cycle as shown Fection eyel in the timing chart. While the rection period | rection cycles power is switched on, the repeti- tion of correction cycle and con- Correction cycle} PHASE 0,1 version cycle enables the TC5090AP at make A/D conversion under the optimum conditions at all times. <Sre of > YES. ‘The operation flowchart is shown in PHASE 0,1, (a) Initial correction period The internal state of this LSI is ~ reasonably unsettled at the time Fig. 1 Operation Flowchart when the power is switched on; therefore, the initial correction cycle is requires before stable converting operation becomes possible. The correction cycle automatically corrects conversion error caused by offset voltage of the integrator or the like, and is composed of the period (PHASE 0) for which Vpp is integrated and the period (PHASE 1) for which Vgs is integrated. Since system correction is performed in steps at the end of this PHASE I, 64 correction cycles (64 * 1024* Togc) are required as the initial correction period. (Tosc denotes one clock cycle.) 580

(b) Conversion cycle If the initial corection cycle period is completed, normal conver- sion becomes possible. When STC input is given, (although the correction cycle in PHASE 0 or PHASE I is in operation at this time), the correc- tion operation stops, and the conversion cycle starts. In other words, even if STC input is given, this LSI performs the same operation as the correction cycle until PHASE I is completed; but it does not perform the correction at the time of completion of PHASE I, and shifts to PHASE II. Therefore, attention should be given to the fact that PHASE I prior to PHASE II does not act as correction cycle. When STC input is given, the LSI integrates analog input in PHASE III through PHASE I and PHASE IL, performing digital conversion in PHASE IV. When the LSI completes digital con- version in PHASE IV, the output is turned to the new data and the LSI returns to the correction cycle. * (ec) Correction cycle When the next STC input is given between completion of arbitrary conversion cycle (at the time of completion of PHASE IV) and completion of one correction cycle (1024-Tosc), no correction is substantially made. Therefore, in case the STC input is consecutively given, another STC should be given after the lapse of one correction cycle at the earliest from completion of PHASE IV, When the STC input is given during conversion (while EOC is at “L" level), the STC cannot be accepted. 581

(4) Constant of integration The Ry and Cy composing the integrator should be selected to satisfy the following equation. 103 = ~ . 203, RyCr = (0.92.5) » Fo [8] Attention should be paid to the fact that, when the external R oscillation is used, fosc has £30% variations in regard to the typ. value in Fig. 5 due to variations in sample and temperature characteristic. In other words, if the typ. value in Fig. 5 is denoted by £R-TYP, the Ry and Cy should be selected according to the following equation. mr . ER-TyP (2) Output Data Mode TRUTH TABLE : DIGITAL OUTPUTS aes Sa = N ANALOG INPUT DATA | DATA] DATA] DATA | DATA ] DATA] DATA [DATA 0 1) 2}3 {0 1 {2 3 L Don't care High Impedance ov Lisp 1 | | ceceseaeneeeeeeaes Straight Binary FSF LSB ov "FS"—> LSB L ja) |au la H [effi stectis [ete lw [ele pepe [el La [res Fuse < [x fete |e je [ute fo] Note : Vsg = OV 1 LSB = Vpp/256 582

8-bit digital data is output on four data lines after having been divided into the higher order 4 bits and the lower order 4 bits, Either the higher order bits or the lower order bits can be selected by RSEL. (3) System Clock Oscillation Circuit For oscillating reference clock the oscillation circuit is composed of external resistors as shown in Fig. 2. osc osc osc osc IN our IN our or o——_ RE External Clock Fig.2 Clock Supplying Methods (4) Timings for STC-EOC and EOC-DATA o Time (tg) from the fall of stc STC to the fall of EOC. EOC 1 3 tse=7Tosc ¥ 7 Tose . tse tes © Time (tpg) from the out of DATA DATA output to the rise of EOC ‘DE tpE = $ Tosc Fig.3 Timing chart of STC/EOC o Min. time (tpg) from the rise of EOC to the accpetance of another STC. 1 3 tes = 7 Tosc © 7 Tosc 583

(5) Timings for STC Input and RSEL/RENB Input i Uk i chro= STC signal is taken in synchro: ste nously with the internal clock; there~ re fore, if TOSC denotes one clock cycle RSEL RENB a of OSC terminal, the pulse width of erminal, the pu °. te Thoth more than (2+Tggc) is required. Either RSEL input or RENB input Fig.4 Timing chart of is required to be set to "H" level at Control Input the falling time of STC by reason of internal structure. Further, the hold time of (Togc + 50ns) or more after the falling time of STC at least for "H" level time of RSEL or REMB is required. NOTE : tw>2-Tosc, thold> Tos¢ + 50ns 584

RECOMMENDED OPERATING CONDITIONS (Vss= Ov) Trem sewpon [ww |v. | ona, | oni Supply Voltage Note: Refer to Fuction Description (1) for determing the values of RI and Cr, respectively, ELECTRICAL CHARACTERISTICS (Vss= OV) TTEM Son conptzions |"? OnTT (mika [na Input High Voltage | Von! vrneVsg,vpp | > |4995 | 4.95 |5.00 4.95 ’ |Tour|<1pa | jutput Low Voltage | VOL.) \\ivevss, pp | 5 5 output High Current! Toq | VOR=4-0V 4 | 5 -1.2| - |-1-0 2.0! - |o.7 Vin=Vss» pp VoL=0.4V * loutput Low C t | } 24a] - +0) 4.0 | - : Put Low Current | TOL | yivevgs,vpp | > | 2*4 | 2-01 4-0 re pores Hien velteee ve a | ai . T v [Input Low Voltage | Vzz LS | - \\0.8 - - [0-8 Output Disable | Ipa Vor=6.5V | ssl - wosl - be alo 5 Current IpL | VoL=0V " 10. tio . Irn | Vrne6.5V _ _ -5 Input Current tn | vr=ov 6.5 jf 41077140. 3 +1 jou An} Switch Off- 26.50 ln a} alog Suiteh une 6.5| - |40.3| - [a1075|40.3 #1 Leak Current ViL=0V Operating Con- IDD | gos = . sumption Current |(opr)| OS°~ } MHz 2.0) 3 * Applicable to digital input/output. Not applicable to analog input/output and OSCIN/OSCouT- 585

Ipp(opr.) Test Circuit Switching Time Test Circuit aroF :0 t o.1ue a Rp=1ke 116 9 6 ih}. as Olen ! pH: upe———+7— : 5 pur 15 9 pur —s 2 ? mT 5 BE 6 1 oot {| 6 15 | RL=1ke 1500pF 500pF oPPT 7 12.4.8 Ft; yg Lb oy =50pr Rf is adjusted as fosc = 1MHz. SWITCHING CHARACTERISTICS TEST WAVEFORMS 1. tpLH, tpHL (RSEL-DATA) 2. ZL, tzH, tz, tzL 20ns_ —_20ns, 20ns —-20ns | ID 90%. RSEL | 7 \\ ibe RENB 62% 998 18% DATAQ~3, 0% 99%, 90% 4 fiz DATAg.3 Lon ‘pL tpHl, tzu _| lene DATA, N97 03 50% DATA, 90% | 10% tpaL | | tLe t —_ tZu fLZ 3. ty (STC) 20ng_ _20ns loos STC | 905 10% tw 587

STANDARD CHARACTERISTICS CHARTS Fig. 1 Yop - lbD(opr) Fig. 2 Ipp(opr) - fosc g 3[feq25°c HATA g ~[tazsec oT TTT 7 @ |fosc=1 MHz @ R oscillation East(n osciiiacionp+-| 1 Vt TT E 2ol ve. oe Ts Sq fave. HH» A--H — | LA 38, PETE TTT | a rail seLT TTT TITTY rrr eg | J te i} PEEP |S a A Ba pe ee

2 ETTTTT TTT rrr 2 4p

fot LTT TIT ii tt iit) |: roi 20 1 2 3 4 5 6 7 2 Nook 300k 500k 14 2M é Supply Voltage Vpp (V. ° Clock Frequency f£0SC (Hz) Fig. 3 P-channel Output Buffer Drain Fig. 4 N-channel Output Buffer Drain Current Characteristics Current Characteristics Drain to Source Potential Difference VDS(V: 1 Hao Vos = 5V ~6 5-4-3 2-10 HH OA A ° i) a Ta = 25°C Vos = -5v HA q pe A ue meso ETL T TTT TV, 3) |e coee ey ee EEE EV, 3) |? Eee . ja a [TITTLE oa ¢ OAT Try yer A, ef (2 Coe eee LPP ry, ¢ Eg [PPP Pee rr ef) fe Jee Heer 8} Js PRA 4 PPE re) 8 ARR REE EE He ts i o TEEPE Pry rr He EH AEH HA 6 Drain to Source Potential Difference VDS(V) Fig.5 _ sR -_fosc Fig. 6 fosc_- Vpp

3 Ee 4 von - sv 3 xt Re = 20k0 HA-t EA

= ES ta =25° 5 ot ra -25ec TTT ti yey Behe jf] Pa =25%6 g | Taresve Ty [| | | oa || TH. } TYR. Cr] Po > LIT Le [| pT (pevaaauaeue7auen 2 ee AC 2 ea £ TTT TPP Tria Py See fe L eg fe 3 aI a LUM TATE N = Cerrr ry rrr rr g Slk 3k 10k 30k 50k 100k $ 0 1 2 3 4 5 6 7 oa External Resistor Rf[(®] co Supply Voltage _Vpp_(V. 588

Fig. 7 tpd - VDD (PENB-DATA) Fig. 8 tpd - VDD (RSEL (L*H)-DATA) a qa-25°c TYP. p++ +++ 4 es Cer a @ 500 ERR B 500] S REESE A Pielk NSS] ty 2500 esoprp = ~ x00] CPSs So COREE Bo cusopr PTT a (te. || AAT TT § § : NA to LNT) |e LLU LL PASS | 2100 mS 2 100 oS OW ESEESEERRSERES [5 SSSSSS SS See Ton] 3 s SOC Cee ee es = se oo a SEEELEER SE | | SEES 2 oe SLEEP Co s TTT Trt TTT S LITT TT TTP Tyre eo LTT} 8 LL ET 2 10 ® 10 ¢ 0 1 2 3 4 5 6 7 Py 0 1 2 3 4 5 6 7 a Supply Voltage VpD(V) & Supply Voltage VDD(V) Fig. 9 tpd - VpD(RSEL(H >L)-DATA) Fig.10 Ry-Cr - fosc ~ Ta = 25°C a a ee ee ee | ~ CePA aR— ta = cL F MN ~ S BS — S00), FE SSReE] [Se EEE SE ima Bin POSS | oe ETP ae NU Xo 7 » tpHL 2 N)|

2100 Sis NN

ae. ee a P) Fe = SSS 310 eS > =——sse=seee=== 2 GSR ENS 3° EERE SERRE EEE SN Soo PE [i TT & (oi Fo ee ree | oe 3 5 aL TTT) fe dil A g 0 1 2 3 4 5 6 2 105 106 a Supply Voltage Vpp(V) & Clock Frequency f0SC (Hz) (Note) The characteristics at Fig. 10 have been prepared for reference at the time of determination of an integrator time constant, according to the equation of 103 for determing Ry-Cy. (Rr: Cr = (0.92.5) = [See]}) ose In case of the determination of Ry and Cy, the product, or the value, of Ry and Cy is required to be within the range of MIN. to MAX. as shown in Fig. 10 after due consideration of dispersion. 589

Product Information

TC5090AP specifications and overview.

Summary

CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

Description

CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

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