TC5036

TC5036AP TOSHIBA | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 5

Technical content

——— C?MOS DIGITAL INTEGRATED CIRCUIT TC5036AP TC5048AP == SILICON MONOLITHIC } ES TC5O36AP TC5048AP 17-STAGE HIGH SPEED FREQUENCY DIVIDER TC5036AP and TC5SO48AP are 17-stage ripple carry binary counters equipped with inverters for crystal oscillators. _— If ¢ input is opened (¢="L"), the inverted output of __ 9th stage appears on FC terminal. If input is set — to "KH", 9 stages from 9th stage through 17th stage can 16 be also independently used having FC terminal as the clock input. 2 Outputs can be derived arbitrarily from stages 4, 12, DIP16(SD164-P) 13, 14, 15, 16 and 17 of TC5036AP and stages 4, 5, 6, 7, 14, 16 and 17 of TCSO48AP. Both devicies are improved to have 50% duty Q4 output as same as others by changing the divider stage of TC5036P and TC5048P to static type counter. PIN ASSIGNMENT ABSOLUTE MAXIMUM RATINGS pososear CHRACTERISTIC SYMBOL RATING UNIT Vpp1_ | Vsg1-0.5 v Vgg1 +10 apg. 16 fivpD1 Dc Supply Voltage SSL Sst v xrlle asfvove Vgg1-0.5¥ Vppi+0.5 x 7 Tenn Suy on 5 asys 1a Reser Input Voltage IN _| Ussi™®-° * Vopz v aiz fs isfy _ 9) FCT Vin [gs1-0.5* Vpprt0-5 asgs seheis Output Voltage Vout | ¥ssi-0-5 Vppit0.5 Oo 1a fiars IDC Input Current +10 vase 7 10 aie Power Dissipation [®> | 300 vesi fs afro Storage Temperature “5A 3, a Tete 65150 C (10P VIEW) ead Temp./Time 260°C + 10 sec 705048AP TRUTH TABLE atl vehvoo: INPUTS FUNCTION wae ropvone RESET] xt [9] FO] (See Timing Chart) aes 14 Begser l« [nl OPEN FQa=fxr/2 ase as fer H aa FL | «| sear" raven acs vehaie £Qn=Fxr/2" ri pare tachi say vesel7 a0 flor Qn fxr ny 5% ef FL) 8 [SU tea vests ofc * Don't Care (ToP VIEW) 505

TC5036AP, TC5048AP SSE Ee BLOCK DIAGRAM Be Ypp1 92% 9&9 Oy P Vppe° Rr] A A A A Vesa a i i R # ras Vsse © oFo S82 be x % RESET © ez] fe R R R R R EI Ue THI. v 7 . T - 7 _T xT -~ THI. 7 } a a a a a g io a a 7 he 5 84 Ss Ge a: sen TIMING CHART xT(in) RESBT(1N) i SS es oe és Pe EA (g="H” RESET = "L") i i i 506

TC5036AP, TC5048AP RECOMMENDED OPERATING CONDITIONS (Vsg1=Vg52"0V) j 3 [ - J 2 | supply Voltage Yop2 | 3 [ - | vom | v ELECTRICAL CHARACTERISTICS (Vssi=Vss2"0V, Vpp1=Vpp2) cuaracreristic | sywwow Toot ore [asec asec [ifn | ea ac ave, [wR P| High Level Von | Hour! tua loutput Voltage VineVpp» Vss 4.95 4.95] 5.00 4.95 — en — v Low Level our |<lua vi ‘out | <lu . loutput Voltage OL | vin=Ypp» Ves 5 0.00 0.05 ~1| Q ~TVgy=4.6V liigh Lever | Ou’ 5 0.51] -1.0] 0.42 Output Vin=Ypp> Vss loutput Tou FC, Vou=4-6V current — 5 |o.025 4 -0.015 xT Vin=Ypp> Yss Q Voi=0.4V Low Level 5 | 0.61 0.51} 1.5 0.42 oureur | VIN=Vpp» Vss Output Fe, | % [Vo,=0.40 Current — 5 |o.10 0.08] 0.25 xT Vin=Ypp» Yss igh Level : Vour=0.5V, 4.5V Input Voltage Vie iggg] ana 5 |3.5 | - |3.5 |2.75 3.5 — v Low Level v Vour=0-5v, 4.50] Input Voltage t Hrour[ dua 1.5 2.25) 1.5 1.5 High Level Input ——- Current Tin |Vzy=8V 8 0.2 10-5] 0.2 1.0 . (except XT, $) Low Level Input Current In, |Vy,=0V -0.2 1075|-0.2 1.0] BA (except XT, $) Quiescent 1 - * Device Current DDL |Vin-Ypp» Yss 5 5 150 * All valid input combinations. 507

TC5036AP, TC5048AP ——— SWITCHING CHARACTERISTICS (Vpp1=Vpp2, Vssi=Vss2=0V, Ta=25°C, CL=S0pF) CHARACTERISTIC SYMBOL | TEST CONDITION [wep for. | ave. | sa UNIT [output Rise Time (q ourput) [Fru | Output Rise Time (Q OUTPUT) TLH 5 70 | 200 Output Fall Time (Q OUTPUT) Propagation Delay Time (FC-Q17) | tpLHstpiL, 5 | - | 420 | 900 Propagation Delay Time (RESET-Q) |tpHL (RESET) 5 - 100 | 200 Min. Pulse Width ty(RESET) | 5 | - 35 | 70 | ns | Max. Clock Frequency fou (xT) 5 | 10 | 20 Max. Clock Frequency fo (FC) 5 8 16 Max. Clock Fall Time Max. Clock Rise Time " (Fc) 5 | 20 Max. Clock Fall Time [ianut capacteance + tn fewer te «dt = Ys fp] Ippy TEST CIRCUIT § Vpp=ev sr @ ” or Yop1 Vppe Fe Vp or Vg O— RESET mens ‘ (9&8 ay Yssi_Vss2 Qe OMe 43 Me 5 ie “a7 508

TC5036AP, TC5048AP a r ALTCHING TIME TEST WAVEFORMS | 1. fg, QT), trins trate tpiuy pHL 90% xT 508 50% 10% og _/| | wn |: 90% | Tos ae 808 50% 10% | 0% i ‘pit | th 7 Te ‘pLi | 30 80% Qn | 10% {pL 2. fo_ (FC), ty (RESET), tpyy (RESET) zone -20n8 90% re ON Oe 50% 1o® 0 tw( RESET) Fare ad RESET sos | Kos 20% | \\nog vou, zone | | 20ne 0% = Q =56Q 50% 50% igre 30% ner 106 ied (p= "E") *pHL ‘pLH i] tpHL T PICAL APPLICATION RESET gf Vppa Yoni TESOEBAPLTCSOSEAP) 6G, Gg uy Gia xP RT_Vsez Yss1_% G2 Gs G16 Gs Se Gr FO Tr DIVIDER OUTPUTS t 509