TC4222CG-PBF

LTC4222 LINER | Alldatasheet

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Technical content

FEATURES

APPLICATIONS

DESCRIPTION

The L TC®4222 Hot Swap™ controller allows two power paths to be safely inserted and removed from a live back- plane. Using external N-channel pass transistors, board supply voltages and inrush currents are ramped up at an adjustable rate. An I 2C interface and onboard ADC allows for monitoring of current, voltage and fault status for each channel. The device features adjustable, analog, foldback current limit circuits and a Soft-Start circuit that sets the dI/dt of the inrush currents. An I 2C interface may confi gure the part to latch off or automatically restart after the L TC4222 detects a fault on either channel. The controller has additional features to interrupt the host when a fault has occurred, notify when output power is good, detect insertion of a load card and power-up either automatically upon insertion or wait for an I 2C command to turn on. L, L T , L TC and L TM are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 7330065.Advanced Mezzanine Card Application n Allows Safe Insertion Into a Live Backplane n 10-Bit ADC Monitors Currents and Voltages n I 2C/SMBus Interface n Wide Operating Voltage Range: 2.9V to 29V n dI/dt Controlled Soft-Start n High Side Drive for External N-Channel MOSFETs n No External Gate Capacitors Required n Input Overvoltage/Undervoltage Protection n Optional Latchoff or Auto-Retry After Faults n Alert Host After Faults n Inrush Current Limit with Foldback n Available in 32-Pin (5mm × 5mm) QFN and 36-Pin SSOP Packages n Live Board Insertion n Electronic Circuit Breakers n Computers, Servers n Platform Management UV1 V DD1 SENSE1– L TC4222 GATE1 INTVCC ADR2 ADR1NC ADR0 CONFIG SOURCE1 UV2 V DD2 12V 7.4A 3.3V 150mA AUXPGOOD 12PGOOD SENSE2– GATE2 SOURCE2 OV1 OV2 ALERT SCL SDA ON FB1 ADIN1 TIMER GPIO1 EN1 SS 10Ω 68nF 6mΩ Si7336ADP 10.2k 3.57k 10Ω

4222 TA01a

0.1μF 34k 1.02k 3.4k GND ALERT SCL ON SDA 12V ADIN2 FB2 GPIO2 EN20.1μF 10Ω 300mΩ Si1046R 4.99k 3.57k 10Ω 0.1μF 6.55k 1.02k 3.4k 3.3V PLUG-IN CARD BACKPLANE 1μF 10nF Start-Up Waveform with Sequencing VOUT2 10V/DIV VOUT1 10V/DIV GPIO PGOOD 10V/DIV VIN1/2 10V/DIV

4222 TA01b

+n + 0.3V (Notes 1, 2) 32 31 30 29 28 27 26 25 9 10 11 12 TOP VIEW UH PACKAGE 32-LEAD (5mm s 5mm) PLASTIC QFN 13 14 15 16 1SS CONFIG INTVCC GND ADR0 ADR1 ADR2 TIMER EN1 ADIN1 ON ALER T SCL SDA ADIN2 EN2 OV2 UV2 V DD2 SENSE2– GATE2 SOURCE2 FB2 GPIO2 OV1 UV1 V DD1 SENSE1– GATE1 SOURCE1 FB1 GPIO1 TJMAX = 125°C, θJA = 34°C/W EXPOSED PAD (PIN 33), PCB GND CONNECTION OPTIONAL TOP VIEW G PACKAGE 36-LEAD PLASTIC SSOP SENSE1 SENSE1+ VDD1 UV1 OV1 SS CONFIG INTVCC GND ADR0 ADR1 ADR2 TIMER OV2 UV2 V DD2 SENSE2+ SENSE2– GATE1 SOURCE1 FB1 GPIO1 EN1 ADIN1 ON1 ON2 ALERT SCL SDAI SDAO ADIN2 EN2 GPIO2 FB2 SOURCE2 GATE2 TJMAX = 125°C, θJA = 95°C/W PIN CONFIGURATION Output Voltages Operating Temperature Range Lead Temperature (Soldering, 10 sec)

ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 12V unless otherwise noted. LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE TC4222CG#PBF L TC4222IG#PBF L TC4222CUH#PBF L TC4222IUH#PBF L TC4222CG#TRPBF L TC4222IG#TRPBF L TC4222CUH#TRPBF L TC4222IUH#TRPBF L TC4222CG L TC4222IG L TC4222 L TC4222 36-Lead Plastic SSOP 36-Lead Plastic SSOP 32-Lead (5mm × 5mm) Plastic QFN 32-Lead (5mm × 5mm) Plastic QFN 0°C to 70°C –40°C to 85°C 0°C to 70°C –40°C to 85°C Consult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container . Consult L TC Marketing for information on non-standard lead based fi nish parts. For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear .com/tapeandreel/ SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Supplies V DDn Input Supply Range l 2.9 29 V IDD1 VDD1 Input Supply Current VDD1 = 12V l 0.85 1.2 mA IDD2 VDD2 Input Supply Current VDD2 = 12V , IINTVCC = 0mA l 34 m A VDDn(UVL) Input Supply Undervoltage Lockout VDD Rising l 2.34 2.43 2.53 V VDDn(HYST) Input Supply Undervoltage Lockout Hysteresis l 60 80 100 mV INTVCC Internal Regulator Voltage IINTVCC = 0mA l 3.15 3.3 3.45 V INTVCC(UVL) INTVCC Undervoltage Lockout INTVCC Rising l 2.55 2.64 2.73 V INTVCC(HYST) INTVCC Undervoltage Lockout Hysteresis l 35 50 65 mV Current Limit and Circuit Breaker (Both Channels) ΔV SENSE(TH) Circuit Breaker Threshold (VDD – VSENSE) l 47.5 48.75 52.5 51.25 mV mV ΔV SENSE Current Limit Voltage (VDD – VSENSE)V FB = 1.3V VFB = 0V Start-Up Timer Expired l l l 130 16.6 150 165 mV mV mV t D(OC) OC Fault Filter ΔVSENSE = 100mV l 10 20 30 μs ISENSE(IN) SENSE+/– Pin Input Current VSENSE = 12V l 02 0 4 0μ A Gate Drive ΔVGATE External N-Channel Gate Drive (VGATE – VSOURCE) (Note 3) VDD = 2.9V to 29V l 4.7 5.9 6.5 V IGATE(UP) External N-Channel Gate Pull-Up Current Gate On, V GATE = 0V l –8 –12 –18 μA IGATE(DN) External N-Channel Gate Pull-Down Current Gate Off, V GATE = 15V l 0.8 1 1.5 mA IGATE(LIM) Pull-Down Current from GATE to SOURCE During OC/UVLO V GATE = 15V , (VDD – VSENSE)n = 200mV l 450 mA tPHL(SENSE) (VDD – SENSE) High to GATE Low VDD – SENSE = 200mV , CGATE = 10nF l 0.5 1 μs VGS(POWERBAD) (GATE-SOURCE) Voltage for Power Bad Fault V SOURCE = 2.9V to 29V l 3.8 4.3 4.7 V Comparator Inputs VINPUT(TH) CONFIG, EN, FB, ON, OV and UV Input Threshold VIN Rising l 1.215 1.235 1.255 V ΔVCONFIG,EN,ON(HYST) CONFIG, EN, ON Hysteresis l 80 128 180 mV ΔVFB(HYST) FB Power Good Hysteresis l 2 7 20 mV

ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS ΔVOV(HYST) OV Hysteresis l 16 24 32 mV ΔVUV(HYST) UV Hysteresis l 60 90 110 mV I(IN) CONFIG, FB, ON, OV and UV Input Current V IN = 3V l 0± 1μ A IEN(UP) EN Pull-Up Current V EN = 0V l 51 0 2 0μ A VUV(RTH) UV Reset Threshold Voltage V UV Falling l 0.36 0.4 0.46 V ΔVUV(RHYST) UV Reset Threshold Hysteresis l 60 125 180 mV VGPIO(TH) GPIO Input Threshold V GPIO Rising l 0.8 1 1.2 V Other Pin Functions V GPIO(OL) GPIO Output Low Voltage I GPIO = 5mA, VDD2 = 2.9V l 0.25 0.4 V IGPIO(OH) GPIO Input Leakage Current V GPIO = 15V l 0± 1μ A ISOURCE SOURCE Input Current SOURCE = 15V l 70 115 170 μA tP(GATE) Input (ON, OV , UV , EN) to GATE Off Propagation Delay l 35μ s tD(GATE) GATE Turn-On Delay ON UV , OV , EN Overcurrent Auto-Retry l l l 4.2 100 125 6.7 μs ms s VTIMERL(TH) Timer Low Threshold l 0.18 0.2 0.22 V VTIMERH(TH) Timer High Threshold l 1.215 1.235 1.255 V ITIMER(UP) TIMER Pull-Up Current l 90 100 110 μA ITIMER(DOWN) TIMER Pull-Down Current for OC Auto-Retry l 1.6 2.15 2.6 μA ITIMER(UP/DOWN) TIMER Pin OC Auto-Retry Duty Cycle l 38 50 58 N/A ISS Soft-Start Ramp Pull-Up Current Ramping Waiting for GATE to Slew l l 7.5 0.5 0.75 12.5 0.95 μA μA ADC RES Resolution (No Missing Codes) l 10 Bits VFS Full-Scale Voltage (1023 • VLSB)( V DD – SENSE) SOURCE ADIN l l l 1.28 mV V V LSB LSB Step Size (V DD – SENSE) SOURCE ADIN l l l 62.5 31.25 1.25 μV mV mV V OS Offset Error (V DD – SENSE) SOURCE ADIN l l l LSB LSB LSB INL Integral Nonlinearity (Note 5) l ±0.5 LSB TUE Total Unadjusted Error/Full-Scale Error (V DD – SENSE) SOURCE ADIN l l l ±1.5 R ADIN ADIN Sampling Resistance V ADIN = 1.28V l 12 MΩ IADIN ADIN Input Current V ADIN = 1.28V l 0 ±0.1 μA Conversion Rate 15 Hz

ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 12V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS I2C Interface VADR(H) ADR0, ADR1, ADR2 Input High Voltage l INTVCC – 0.8 INTVCC – 0.4 INTVCC – 0.2 V IADR(IN,Z) ADR0, ADR1, ADR2 Hi-Z Input Current ADR0, ADR1, ADR2 = 0.8V , INTVCC – 0.8V l 50 – 5 μ A VADR(L) ADR0, ADR1, ADR2 Input Low Voltage l 0.2 0.4 0.8 V IADR(IN) ADR0, ADR1, ADR2 Input Current ADR0, ADR1, ADR2 = 0V , INTV CC l –80 80 μA VALERT(OL) ALERT Output Low Voltage I ALERT = 3mA l 0.2 0.4 V IALERT(OH) ALERT Input Current ALERT = INTVCC l ±1 μA VSDA,SCL(TH) SDA, SCL Input Threshold l 1.5 1.7 1.9 V ISDA,SCL(OH) SDA, SCL Input Current SCL, SDA = INTV CC l ±1 μA VSDA(OL) SDA Output Low Voltage I SDA = 3mA l 0.2 0.4 V I2C Interface Timing fSCL(MAX) SCL Clock Frequency Operates with f SCL ≤ fSCL(MAX) 400 1000 kHz tBUF(MIN) Bus Free Time Between Stop/Start Condition 0.12 1.3 μs tHD,STA(MIN) Hold Time After (Repeated) Start Condition 100 600 ns tSU,STA(MIN) Repeated Start Condition Set-Up Time 30 600 ns tSU,STO(MIN) Stop Condition Set-Up Time 140 600 ns tHD,DAT(MIN) Data Hold Time (Input) 30 100 ns tHD,DATO Data Hold Time (Output) 300 600 900 ns tSU,DAT(MIN) Data Set-Up Time 30 600 ns tSP Suppressed Spike Pulse Width 50 110 250 ns tRST Stuck-Bus Reset Time SCL or SDA Held Low 25 32 40 ms CX SCL, SDA Input Capacitance SDAI Tied to SDAO (Note 5) 10 pF Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All currents into pins are positive, all voltages are referenced to GND unless otherwise specifi ed. Note 3: An internal clamp limits the GATE pin to a minimum of 5V above SOURCE. Driving this pin to voltages beyond the clamp may damage the device. Note 4: Integral Nonlinearity is defi ned as the deviation of a code from a precise analog input voltage. Maximum specifi cations are limited by the LSB step size and the single shot measurement. Typical specifi cations are measured from 1/4, 1/2, 3/4 areas of the quantization band. Note 5: Guaranteed by design and not subject to test.

TYPICAL PERFORMANCE CHARACTERISTICS IDD1 vs VDD1 IDD2 vs VDD2 INTVCC vs VDD2 INTVCC vs ILOAD VTH(UV) vs Temperature V HYST(UV) vs Temperature TA = 25°C. VDDn = 12V unless otherwise noted. VDD1 (V) IDD1 (mA) 1.0 0.8 0.6 0.9 0.7 0.5 0.4 2010

4222 G01

VDD2 (V) IDD2 (mA) 4.0 3.0 3.5 2.5 2.0 2010

4222 G02

VDD2 (V) 2.5 INTVCC (V) 4.03.0

4222 G03

5.03.5 4.5 3.4 3.2 3.0 3.3 3.1 2.9 2.8 ILOAD (mA) INTVCC (V) 7.52.5

4222 G04

15.05.0 10.0 12.5 3.50 3.00 3.25 2.75 2.50 VDD2 = 2.9V VDD2 = 3.3V VDD2 = 5V VDD2 = 12V TEMPERATURE (°C) –50 VTH(UV) (V) 1.250 1.240 1.230 1.245 1.235 1.225 1.220 500

4222 G05

10025–25 75 TEMPERATURE (°C) –50 VHYST(UV) (mV) 100 500

4222 G06

10025–25 75

TYPICAL PERFORMANCE CHARACTERISTICS ΔVGATE vs Temperature ΔV GATE vs IGATE IGATE vs Temperature TA = 25°C. VDDn = 12V unless otherwise noted. TEMPERATURE (°C) –50 ΔVGATE (V) 6.1 6.0 5.8 5.6 5.9 5.7 5.5 5.4 500

4222 G10

10025–25 75 VDD2 = 2.9V VDD2 = 3.3V VDD2 = 5V VDD2 = 12V IGATE (A) ΔVGATE (V) 6.5 6.0 4.5 5.5 5.0 4.0 1046

4222 G11

VDD2 = 2.9V VDD2 = 3.3V VDD2 = 5V VDD2 = 12V TEMPERATURE (°C) –50 IGATE (μA) 12.0 11.9 11.7 11.8 11.6 11.5 500

4222 G12

10025–25 75 TEMPERATURE (°C) –50 ITIMER (μA) 110 100 105 500

4222 G07

10025–25 75 ITIMER vs Temperature Current Limit vs V FB VTH Circuit Breaker vs Temperature VFB (V) CURRENT LIMIT (mV) 1.00.4 0.6

4222 G08

1.40.80.2 1.2 TEMPERATURE (°C) –50 VTH CIRCUIT BREAKER (mV) 500

4222 G09

10025–25 75

TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C. VDDn = 12V unless otherwise noted. VSENSE (mV) TPHLVGATE (μs) 100 0.1

4222 G18

IGPIO (mA) VGPIO (V)

4222 G13

0.6 0.4 0.2 0.5 0.3 0.1 VOL(GPIO) vs IGPIO ADC Total Unadjusted Error vs CODE (ADIN1) ADC INL vs CODE (ADIN1) ADC DNL vs CODE (ADIN1) ADC Full-Scale Error vs Temperature T PHL VGATE vs VSENSE Overdrive TEMPERATURE (°C) –50 FULL-SCALE ERROR (LSB) 500

4222 G17

10025–25 75 CODE ERROR (%) 0.9 0.7 0.6 0.8 1.0 0.4 0.2 0.1 0.3 0.5 512256

4222 G14

INL (LSB) 0.5 –0.4 0.4 0.2 –0.2 0.3 0.1 –0.1 –0.3 –0.5 512256

4222 G15

DNL (LSB) 0.5 –0.4 0.4 0.2 –0.2 0.3 0.1 –0.1 –0.3 –0.5 512256

4222 G16

ADIN: ADC Input. A voltage between 0 and 1.28V applied to this pin is measured by the on-board ADC. Tie to ground if unused. ADR0, ADR1, ADR2: Serial Bus Address Inputs. Tying these pins to ground, open, or INTV CC confi gures one of 27 possible addresses. See Table 1 in Applications Information. ALERT: Fault Alert Output. Open drain logic output that is pulled to ground when a fault occurs to alert the host controller . A fault alert is enabled by setting the corre- sponding bit in the ALERT register as shown in Table 4. See Applications Information. Tie to ground if unused. CONFIG: Confi guration Input. Confi gures the part to control the two channels together or independently. When CONFIG is tied to GND both channels start up at the same time. A fault, EN or ON turn-off command on either channel will shut down both channels. When CONFIG is tied to INTV CC, either channel can start up independently. A fault, EN or ON turn-off command will result in the associated chan- nel turning off, while the other channel remains on. If one channel is commanded to turn on while another channel is in the turn-on sequence, the 4222 waits until the fi rst channel has fi nished its turn-on sequence before turning on the second channel. EN1, EN2: Enable Input. Ground this pin to indicate a board is present and enable the N-channel MOSFET to turn-on. When this pin is high, the MOSFET is not allowed to turn on. An internal 10μA current source pulls up this pin. T ransitions on this pin are recorded in the FAUL T register . A high-to-low transition activates the logic to read the state of the ON pin and clear faults. See Applications Information. EXPOSED PAD: (Pin 33, QFN Package) Exposed Pad. May be left open or connected to device ground. FB1, FB2: Foldback Current Limit and Power-Good Input. A resistive divider from the output is tied to this pin. When the voltage at this pin drops below 1.235V , power is not considered good. The power bad condition may result in the GPIO pin pulling low or going high impedance depending on the confi guration of CONTROL register bits 6 and 7. Also a power bad fault is logged when the FB pin is low, the L TC4222 has fi nished the startup cycle and the GATE pin is high. See Applications Information. The startup current limit folds back from 50mV sense voltage to 16.6mV as the FB voltage drops from 0.8V to 0.2V . Foldback is not active once the part leaves startup and the current limit is increased to 150mV . GATE1, GATE2: Gate Drive for External N-Channel MOSFET . An internal 12μA current source charges the gate of the MOSFET . No compensation capacitor is required on the GATE pin, but a resistor and capacitor network from this pin to ground may be used to set the turn-on output voltage slew rate. During turn-off there is a 1mA pull-down cur- rent. During a short circuit or under-voltage lockout (V DD or INTVCC), a 450mA pull-down current source between GATE and SOURCE is activated. GND: Device Ground. GPIO1, GPIO2: General Purpose Input/Output. Open drain logic output or logic input. Defaults to an output set to pull low to indicate power is not good. Confi gure according to Table 3. INTV CC: Low Voltage Supply Decoupling Output. Connect a 0.1μF capacitor from this pin to ground. ON: (QFN Package) On Control Input. Formed by internally tying the ON1 and ON2 lines together . ON1, ON2: (SSOP Package) On Control Inputs. A rising edge turns on the external N-channel FET and a falling edge turns it off. This pin also confi gures the state of the FET ON register bit (and hence the external FET) at power up. For example, if the ON pin is tied high, then the FET ON bit (Control bit 3 in Table 3) goes high 100ms after power-up. Likewise if the ON pin is tied low then the channel remains off after power-up until the FET ON bit is set high using the I 2C bus. A high-to-low transition on this pin clears the fault register for the related channel. The two ON pins are tied together internally on the QFN package. OV1, OV2: Overvoltage Comparator Input. Connect this pin to an external resistive divider from V DD. If the voltage at this pin rises above 1.235V , an overvoltage fault is detected and the GATE turns off. Tie to GND if unused.

SCL: Serial Bus Clock Input. Data at the SDA pin is shifted in or out on rising edges of SCL. This is a high impedance pin that is generally driven by an open collector output from a master controller . An external pull-up resistor or current source is required. SDAO: (SSOP Package) Serial Bus Data Output. Open- drain output for sending data back to the master control- ler or acknowledging a write operation. Normally tied to SDAI to form the SDA line. An external pull-up resistor or current source is required. Internally tied to SDAI in QFN package. SDAI: (SSOP Package) Serial Bus Data Input. A high im- pedance input for shifting in address, command or data bits. Normally tied to SDAO to form the SDA line. Internally tied to SDAO in QFN package. SDA: (QFN Package) Serial Bus Data Input/Output Line. Formed by internally tying the SDAO and SDAI lines together . An external pull-up resistor or current source is required. SENSE1 –, SENSE2–: Negative Current Sense Input. Con- nect this pin to the output of the current sense resistor . The current limit circuit controls the corresponding GATE pin voltage to limit the sense voltage between the SENSE + and SENSE– pins to the level set by the soft-start and foldback characteristic, with a maximum of 50mV during start-up and to 150mV independent of soft-start and foldback after the start-up timer has expired. A circuit breaker , enabled after start-up, trips when the sense voltage exceeds 50mV for 20μs. SENSE1 +, SENSE2 +: (SSOP Package) Positive Current Sense Input. Connect this pin to the input of the current sense resistor . It must be connected to the same trace as V DDn. Internally tied to VDDn in the QFN package. SOURCE1, SOURCE2: N-Channel MOSFET Source and ADC Input. Connect this pin to the source of the external N-Channel MOSFET switch for gate drive return. This pin also serves as the ADC input to monitor output voltage. The pin provides a return for the gate pull-down circuit. SS: Soft-Start Input. Sets the inrush current slew rate at startup. Connect a 68nF capacitor to provide 5mV/ms as the slew rate for the sense voltage in startup. This cor- responds to 1A/ms with a 5mΩ sense resistor . Note that a large Soft-Start capacitor and a small TIMER capacitor may result in a condition where the timer expires before the inrush current has started. Allow an additional 2nF of timer capacitance per 1nF of Soft-Start capacitor to ensure proper startup. TIMER: Startup Timer Input. Connect a capacitor between this pin and ground to set a 12.3ms/μF duration for startup, after which an overcurrent fault is logged if the inrush is still current limited. The duration of the off time is 600ms/μF when overcurrent auto-retry is enabled, resulting in a 1:50 duty cycle. An internal timer provides a 100ms startup time and 5s auto-retry time if this pin is tied to INTV CC. Allow an additional 2nF of timer capacitance per 1nF of Soft-Start (SS) capacitor to ensure proper startup. UV1, UV2: Undervoltage Comparator Input. Connect this pin to an external resistive divider from V DD. If the volt- age at this pin falls below 1.145V , an undervoltage fault is detected and the GATE turns off. Pulling this pin below 0.4V resets the fault register for that channel except for the UV fault bit. Tie to INTV CC if unused. VDD1, VDD2: Supply Voltage Input and Positive Current Sense Input. This pin has an undervoltage lockout threshold of 2.43V . In the QFN package this pin is also the positive current sense input.

1.235V UVS RESET COUPLE OVS VDD UVLO 0.4V 1.235V 1.235V INTVCC 2.43V I2C 5I2C ADDR UV RST 1.235V – 0.2V 0.6V PWRGD FET ON FAULT PG OV1 EN EN 1.235V – 0.2V TM2 UVLO2 UVLO1 FB OV EN 1.235V – VDD 10MA SDAI (SSOP) CONFIG SS SDAO (SSOP) SDA (QFN)

1 OF 27

2.64VVCC UVLO 4222 BD INTVCC TIMER GPIO INTVCC VDD2 100MA 2MA

10 BIT

3.3V GEN TM1 SOURCE GATE– CS CB SENSE+ (SSOP)SENSE– CHARGE PUMP AND GATE DRIVER FOLDBACK and DIDT 0mV TO 150mV GP ON ADR2 ADR1 ADR0 ONS 1.235V ON SOURCE1 VDDA – SENSE1 SOURCE2 VDDB – SENSE2 A/D CONVERTER SCL ALERT 50mV ADIN1 ADIN2 LOGIC SOFT-START

The L TC4222 is designed to turn two supply voltages on and off in a controlled manner , allowing boards to be safely inserted or removed from a live backplane. During normal operation, the charge pump and gate drivers turn on external N-channel MOSFET gates to pass power to the loads. The gate driver circuits use a charge pump that derives its power from the V DD1 or VDD2 pin, whichever is higher . Also included in the gate driver circuits are internal 6.5V GATE to SOURCE clamps to protect the oxide of logic level MOSFETs. During start-up the inrush currents are tightly controlled by using current limit foldback, soft start dI/dt limiting and output dI/dt limiting. The L TC4222 is capable of controlling both channels independently, or coupling control signals so that both channels start up and turn off together . The current sense (CS) amplifi ers monitor the load cur- rents using the difference between the SENSE+ (V DD for QFN) and SENSE– pin voltages. A CS amplifi er limits the current in the load by pulling back on the GATE-to-SOURCE voltage in an active control loop when the sense voltage exceeds the commanded value. The CS amplifi ers require 20μA input bias current from both the SENSE + and the SENSE– pins. A short circuit on an output to ground results in excessive power dissipation during active current limiting. To limit this power , the corresponding CS amplifi er regulates the voltage between the SENSE+ and SENSE– pins at 150mV . If an overcurrent condition persists, the internal circuit breaker (CB) registers a fault when the sense voltage exceeds 50mV for more than 20μs. This indicates to the logic that it is time to turn off the GATE to prevent overheating. At this point the TIMER capacitor starts to discharge with the 2μA current source until the voltage drops below 0.2V (comparator TM1) which tells the logic that the pass transistor has cooled and it is safe to turn on again if overcurrent auto-retry is enabled. If the TIMER pin is tied to INTV CC, the cool-down time defaults to 5 seconds using an internal system timer . The output voltages are monitored using the FB resistive divider and the Power Good (PG) comparators to determine when output voltages are acceptable for the loads. The power good conditions are signaled by the GPIO1 and GPIO2 pins using open-drain pull-down transistors. The GPIO pins may also be independently confi gured to signal power bad, or as general purpose inputs (GP comparators), or general purpose open drain outputs. The Functional Diagram shows the monitoring blocks of the L TC4222. The group of comparators on the left side includes the undervoltage (UV), overvoltage (OV), reset (RST), enable ( EN) and on (ON) comparators for chan- nel 1 or 2. These comparators determine if the external conditions are valid prior to turning on their correspond- ing GATE. The two undervoltage lockout circuits, UVLO1 and UVLO2, validate the input supplies and the internally generated 3.3V supply, INTV CC. UVLO2 also generates the power-up initialization to the logic circuits as INTVCC crosses this rising threshold. The CONFIG pin is used to select the desired startup be- havior of the L TC4222. When the CONFIG pin is low, both channels will start up and turn off simultaneously and a fault on either channel will result in both channels turning off, or prevent both channels from starting up. When the tSU, DAT tSU, STO tSU, STA tBUF tHD, STA tSP tSPtHD, DATO, tHD, DATI tHD, STA START CONDITION STOP CONDITION REPEATED START CONDITION START CONDITION

4222 TD01

CONFIG pin is high the two channels work completely in- dependently and ignore the behavior of the other channel. This allows for the channels to start up in sequence by connecting the GPIO (power good) output of one channel to the UV pin of the other channel. The two channels share the TIMER and SS (soft-start) pins that control startup behavior . If the CONFIG pin is high and one channel is enabled while the other channel is starting up, the L TC4222 will wait for the startup cycle to end before starting up the second channel to ensure that it gets a full timer cycle. The exception to this is the ON pins, which turn on the corresponding channel imme- diately. When both channels startup simultaneously, the inrush current for both channels is limited by whichever FB pin is lowest. Included in the L TC4222 is a 10-bit A/D signal. The 6-input multiplexer ahead of the A/D converter allows to select between the two ADIN pins, the two SOURCE pins and the two current sense devices. An I 2C interface is provided to read the A/D registers. It also allows the host to poll the device and determine if faults have occurred. If the ALERT line is confi gured as an interrupt, the host is enabled to respond to faults in real time. The SDA line is divided into an SDAI (input) and SDAO (output). This simplifi es applications using an optoisolator driven directly from the SDAO output. The I 2C device address is forwarded to the address decoder from the ADR0, ADR1 and ADR2 pins. These inputs have three states each that decode into a total of 27 device addresses. OPERATION APPLICATIONS INFORMATION A typical L TC4222 application is in a high availability system in which two positive voltage supplies are distributed to one or more cards. The device measures card voltages and currents and records past and present fault conditions for both channels. The system queries each L TC4222 over the I 2C periodically and reads status and measurement information. A basic L TC4222 application circuit is shown in Figure 1. The following sections cover turn-on, turn-off and acts upon various faults that the L TC4222 detects. External component selection is discussed in detail in the Design Example section. Turn-On Sequence The power supplies on a board are controlled by using external N-channel pass transistors (Q1 and Q2) placed in the power path. Note that resistor RSn provides current detection. Resistors R1n, R2n and R3n defi ne undervoltage and overvoltage levels for the two channels. R5n prevents high frequency oscillations in Qn and R6n. C1n forms an optional network that may be used to provide an output dV/dt limited start-up. Several conditions must be present before the external MOSFET for a given channel turns on. First the external supplies, V DDn, must exceed their 2.44V undervoltage lockout levels. Next the internally generated supply, INTVCC, must cross its 2.64V undervoltage threshold. This gener- ates a 60μs to 120μs power-on-reset pulse. During reset the fault registers are cleared and the control registers are set or cleared as described in the register section. After a power-on-reset pulse, the L TC4222 goes through the following turn-on sequence for one or both channels. First the UV and OV comparators indicate that input power is within the acceptable range, which is indicated by STATUS bits 0 to 1 in Table 5. Second, the EN pin is externally pulled low. Finally, all of these conditions must be satisfi ed for the duration of 100ms to ensure that any contact bounce during insertion has ended. Additionally, if the CONFIG pin is low all initial conditions for both channels must be met before the pair are allowed to turn on together . When these initial conditions are satisfi ed, the ON pin is checked and it’s state written to bit 3 in the CONTROL register (Table 3). If it is high, the external MOSFET is turned on. If the ON pin is low, the external MOSFET is turned on when the ON pin is brought high or if a serial bus turn-on command is sent by setting CONTROL bit 3. If the CONFIG pin is low, either both ON pins must be high or both CONTROL registers third bits must be set in order for the external MOSFETs to be turned on simultaneously.

Figure 1. Typical Application where a zero indicates that power is good.

Figure 2. Power-Up Waveform

4222 F02

associated GATE if their auto-retry bits are set to false. both GATEs if the CONFIG pin is low.

auto-retry bit (CONTROL register bit 2) has been set. 20μs the circuit breaker trips and the switch is turned off. foldback is not active after start-up. instead turns on the corresponding channel immediately. channel to restart after a 100ms delay. turns one channel off, both channels turn off. Figure 3. Short-Circuit Waveform

4222 F03

pin, if used, reaches its 200mV low threshold. is unnecessary when using the internal 100ms timer . bit 3. This turns the switch on if the ON pin is tied high. if either EN pin goes high both channels will turn off. Figure 4. The fi lter time is given by: Figure 4. Plug-In Card Insertion/Removal

4222 F04

present bit, STATUS bit 3, and power bad bit, FAUL T bit 3.

When any of the fault bits in a FAUL T register (see Table 4) are set, an optional bus alert is generated if the appropri- ate bit in the ALERT register has been set. This allows only selected faults to generate alerts. At power-up the default state is to not alert on faults and the ALERT pin is high. If an alert is enabled, the corresponding fault causes the ALERT pin to pull low. After the bus master controller broadcasts the Alert Response Address, the L TC4222 responds with its address on the SDA line and releases ALERT as shown in Table 7. If there is a collision between two L TC4222s responding with their addresses simultaneously, then the device with the lower address wins arbitration and responds fi rst. The ALERT line is also released if the device is addressed by the bus master if ALERT is pulled low due to an alert. Once the ALERT signal has been released for one fault, it is not pulled low again until the FAUL T register indicates a different fault has occurred or the original fault is cleared and it occurs again. Note that this means repeated or continuing faults do not generate alerts until the associ- ated FAUL T register bit has been cleared. Resetting Faults Faults are reset with any of the following conditions on a given channel. First, a serial bus command writing zeros to the FAUL T register bits 0 to 5 clears the associated faults. Second, FAUL T register bits 0 to 5 are cleared when the corresponding switch is turned off by the ON pin or STATUS bit 3 going from high to low, if the corresponding UV pin is brought below its 0.4V reset threshold for 2μs, or if INTV CC falls below its 2.64V undervoltage lockout threshold. Finally, when EN is brought from high to low, only corresponding FAUL T bits 0-3 and 5 are cleared, and bit 4, which indicates a EN change of state, is set. Note that faults that are still present, as indicated in the STATUS registers, cannot be cleared. The FAUL T registers are not cleared when auto-retrying. When auto-retry is disabled the existence of an overvoltage, undervoltage, or overcurrent fault keeps the switch off. As soon as the fault is cleared, the switch turns on. If auto-retry is enabled, then a high value in STATUS register bits 0 or 1 holds the switch off and the fault register is ignored. Subsequently, when STATUS register bits 0 and 1 are cleared by removal of the fault condition, the switch is allowed to turn on again. The L TC4222 will set FAUL T bit 2 and turn off in the event of an overcurrent fault, preventing it from remaining in an overcurrent condition. If confi gured to auto-retry, the L TC4222 will continually attempt to restart after cool-down cycles until it succeeds in starting up without generating an overcurrent fault. Note that if a switch is on after an auto-retry and the FAUL T bit has not been reset, clearing the corresponding auto-retry bit will turn the channel off. Data Converter The L TC4222 incorporates a 10-bit A/D converter that continuously scans six different voltages. The SOURCE pins have a 1/24 resistive divider to monitor a full scale voltage of 32V with 31.25mV resolution. The ADIN pins are monitored with a 1.28V full scale and 1.25mV resolution, and the voltage between the V DD and SENSE pins is moni- tored with a 64mV full scale and 62.5μV resolution. Results from each conversion are stored, left justifi ed, in registers as seen in Tables 7 and 8, and are updated 15 times per second. Setting ADC_CONTROL register bit 0 invokes a test mode that halts the data converter so that the data converter result registers may be written to and read from for software testing. The data converter also has a direct address mode that allows the user to take a specifi c measurement at a spe- cifi c time and hold that value for later readback. Direct address mode is entered by setting the Halt bit, bit 0, in the ADC_CONTROL register (see Table 9). Then when the channel address bits, ADC_CONTROL bits 1 to 3, are written to, the ADC will make a single measurement on the channel indicated by those bits, then stop. Setting the ADC Alert bit, ADC_CONTROL bit 4, will enable an interrupt when the data converter fi nishes the conversion, result- ing in the ALERT pin pulling low when the data is ready. Alternately, the ADC Busy bit, ADC_CONTROL bit 5, can be polled to check for the end of the conversion, after a direct address conversion the ADC Busy bit will go low. In normal mode ADC Busy is always high. Resetting the Halt bit returns the data converter to the scan mode.

Confi guring the GPIO Pins Table 3 describes the possible states of the GPIO pins using the CONTROL registers bits 6 and 7. At power-up, the default state is for a GPIO pin to go high impedance when power is good (FB pin greater than 1.235V). Other applications for a GPIO pin are to pull down when power is good, a general purpose output and a general purpose input. A simple application of the GPIO pin in the power good confi guration is to connect it to the UV pin of the other channel with the CONFIG pin high. This will result in the second channel being turned on after the fi rst channel has started up and signaled power-good. Current Limit Stability For many applications the L TC4222 current limit will be stable without additional components. However there are certain conditions where additional components may be needed to improve stability. The dominant pole of the cur- rent limit circuit is set by the capacitance and resistance at the gate of the external MOSFET , and larger gate capaci- tance makes the current limit loop more stable. Usually a total of 8nF gate to source capacitance is suffi cient for stability and is typically provided by inherent MOSFET C GS, however the stability of the loop is degraded by increasing R SENSE or by reducing the size of the resistor on a gate RC network if one is used, which may require additional gate to source capacitance. Board level short-circuit testing is highly recommended as board layout can also affect transient performance, for stability testing the worst case condition for current limit stability occurs when the output is shorted to ground after a normal startup. There are two possible parasitic oscillations when the MOSFET operates as a source follower when ramping at power-up or during current limiting. The fi rst type of oscillation occurs at high frequencies, typically above 1MHz. This high frequency oscillation is easily damped with R5 as shown in Figure 1. In some applications, one may fi nd that R5 helps in short-circuit transient recovery as well. However , too large of an R5 value will slow down the turn-off time. The recommended R5 range is between 5Ω and 500Ω. The second type of source follower oscillation occurs at frequencies between 200kHz and 800kHz due to the load capacitance being between 0.2μF and 9μF , the presence of R5 resistance, the absence of a drain bypass capacitor , a combination of bus wiring inductance and bus supply output impedance. To prevent this second type of oscillation avoid load capacitance below 10μF , alternately connect an external capacitor from the MOSFET gate to ground with a value greater than 1.5nF . Supply T ransients The L TC4222 is designed to ride through supply transients caused by load steps. If there is a shorted load and the parasitic inductance back to the supply is greater than 0.5μH, there is a chance that the supply collapses before the active current limit circuit brings down the GATE pin. If this occurs, the undervoltage monitors pull the corre- sponding GATE pin low. The undervoltage lockout circuit has a 2μs fi lter time after V DD drops below 2.35V . The UV pin reacts in 2μs to shut the GATE off, but it is recom- mended to add a fi lter capacitor C F to prevent unwanted shutdown caused by a transient. Eventually either the UV pin or undervoltage lockout responds to bring the current under control before the supply completely collapses. Supply T ransient Protection The L TC4222 is safe from damage with supply voltages up to 35V . However , spikes above 35V may damage the part. During a short-circuit condition, large changes in current fl owing through power supply traces may cause induc- tive voltage spikes which exceed 35V . To minimize such spikes, the power trace inductance should be minimized by using wider traces or heavier trace plating. Also, a snubber circuit dampens inductive voltage spikes. Build a snubber by using a 100Ω resistor in series with a 0.1μF capacitor between V DD and GND. A surge suppressor , Z1 in Figure 1, at the input can also prevent damage from voltage surges. Design Example As a design example, take the following specifi cations for channel 1: V IN = 12V , IMAX = 5A, IINRUSH = 1A, dI/dtINRUSH = 10A/ms, CL = 330μF , VUV(RISING) = 10.75V , VOV(FALLING) = 14.0V , VPWRGD(UP) = 11.6V , and I2C ADDRESS = 1000111. This completed design is shown in Figure 1.

Selection of the sense resistor , RS, is set by the overcurrent threshold of 50mV: R mV IS MAX ==50 00 1. Ω The MOSFET is sized to handle the power dissipation dur- ing inrush when output capacitor COUT is being charged. A method to determine power dissipation during inrush is based on the principle that: Energy in C L = Energy in Q1 This uses: Energy in C CV mFL ==1 2 03 3 1 222 (. ) ( ) or 0.024 joules. Calculate the time it takes to charge up COUT: t CVI I mF V ASTARTUP L DD INRUSH INRUSH == =• .•03 3 1 2 1 44ms The power dissipated in the MOSFET : P t WDISS STARTUP ==Energy in CL 6 The SOA (safe operating area) curves of candidate MOSFETs must be evaluated to ensure that the heat capacity of the package tolerates 6W for 4ms. The SOA curves of the Fairchild FDC653N provide for 2A at 12V (24W) for 10ms, satisfying this requirement. Since the FDC653N has less than 8nF of gate capacitance and we are using a GATE RC network, the short circuit stability of the current limit should be checked and improved by adding a capacitor from GATE to SOURCE if needed. The inrush current is set to 1A using C1: C CI I LG A T E INRUSH 1= • C mF μA A Cn F1 03 3 1 2 1 13 9== .• .or The inrush dI/dt is set to 10A/ms using CSS: C I R μA SS SS SENSE = ⎛ dl/dt A s

• . • 0 0429 1 10 0 00429 1 10000 0 01 43•
• . .Ω = nF choose 4.7nF For a start-up time of 4ms with a 2x safety margin we choose: C t C C ms TIMER STARTUP SS TIMER 2 2
• •12.3ms/μF 122.3ms/μF F+=47 2 06 8.• .nF μ Note the minimum value of CTIMER is 10nF . The UV and OV resistor string values can be solved in the following method. First pick R3 based on I STRING being 1.235V/R3 at the edge of the OV rising threshold. Then solve the following equations: R V V R UV OV OV OFF UV ON TH RISING TH FALL 23= () IING R R VR R UV RRUV ON TH RISING 32= +()
• ( ) In our case we choose R3 to be 3.4k to give a resistor string current below 100μA. Then solving the equations results in R2 = 1.16 kΩ and R1 = 34.6kΩ. The FB divider is solved by picking R8 and solving for R7, choosing 3.57k for R8 we get: R VR FB RPWRGD UP TH RISING 8= () Resulting in R7 = 30k A 0.1μF capacitor , CF, is placed on the UV pins to prevent supply glitches from turning off the GATE via UV or OV .

1. Address 4 is set by setting ADR2 low, ADR1 open and

values 10Ω and 15kΩ as discussed previously. through resistor R2) to GND also helps reject supply noise. Byte, Write Byte, Read Word and Write Word commands. for these commands are shown in Figures 6 to 11. address space under the PMBus specifi cation. by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. register bit 4 in the CONTROL register of channel 2 to zero. Address (0001 100) is the SMBus Alert Response Address. Figure 5. Recommended Layout

4222 F05

4222 F07

4222 F08

4222 F09

Figure 7. L TC4222 Serial Bus SDA Write Byte Protocol Figure 8. L TC4222 Serial Bus SDA Write Word Protocol Figure 9. L TC4222 Serial Bus SDA Read Byte Protocol Figure 6. Data T ransfer Over I2C or SMBus

4222 F06

address and releasing the ALERT pin. to terminate the transmission. once more and latches the data into its control register .

4222 F11

4222 F10

Figure 10. L TC4222 Serial Bus SDA Read Word Protocol Figure 11. L TC4222 Serial Bus SDA Alert Response Protocol same seven bit address with the R/W bit now set to one. SDA line and then release ALERT as shown in Figure 11.

Table 1. L TC4222 I2C Device Addressing h 76543210 A D R 2 A D R 1 A D R 0 Mass Write C6 11000110XXX Alert Response 19 00011001XXX 0 8 8 1000100XL N C L 1 8 A 1000101XLH N C 2 8 C 1000110XL N C N C 3 8 E 1000111XL N C H 4 9 8 1001100XLLL 5 9 A 1001101XLHH 6 9 C 1001110XLL N C 7 9 E 1001111XLLH

8 A 8 1010100X N C N C L

9 A A 1010101X N C H N C

1 0 A C 1010110X N C N C N C 1 1 A E 1010111X N C N C H 1 2 B 8 1011100X N C LL 1 3 B A 1011101X N C HH 1 4 B C 1011110X N C L N C 1 5 B E 1011111X N C LH 1 6 C 8 1100100XH N C L 1 7 C A 1100101XHH N C 1 8 C C 1100110XH N C N C 1 9 C E 1100111XH N C H 2 0 D 8 1101100XHLL 2 1 D A 1101101XHHH 2 2 D C 1101110XHL N C 2 3 D E 1101111XHLH 2 4 E 8 1110100XLHL 2 5 E A 1110101X N C HL 2 6 E C 1110110XHHL

Table 2. L TC4222 Register Addresses and Contents

208 D0h Control1 (A1) Sets Behavior for Channel 1

209 D1h Alert1 (B1) Selects Which Channel 1 Faults Generate Alerts

210 D2h Status1 (C1) Displays the Status of Channel 1

211 D3h Fault1 (D1) Fault Log for Channel 1

212 D4h Control2 (A2) Sets Behavior for Channel 2

213 D5h Alert2 (B2) Selects which Channel 2 Faults Generate Alerts

214 D6h Status2 (C2) Displays the Status of Channel 2

215 D7h Fault2 (D2) Fault Log for Channel 2

216 D8h SOURCE1 MSB ADC SOURCE1 MSB data

217 D9h SOURCE1 LSB ADC SOURCE1 LSB data

218 DAh SOURCE2 MSB ADC SOURCE2 MSB data

219 DBh SOURCE2 LSB ADC SOURCE2 LSB data

220 DCh ADIN1 MSB ADC ADIN1 MSB

221 DDh ADIN1 LSB ADC ADIN1 LSB

222 DEh ADIN2 MSB ADC ADIN2 MSB

223 DFh ADIN2 LSB ADC ADIN2 LSB

224 E0h SENSE1 MSB ADC SENSE1 MSB

225 E1h SENSE1 LSB ADC SENSE1 LSB

226 E2h SENSE2 MSB ADC SENSE2 MSB

227 E3h SENSE2 LSB ADC SENSE2 LSB

228 E4h ADC CONTROL Confi gures Behavior of the ADC

Table 3. CONTROL Registers A – Read/Write

5 GPIO1 Output GPIO2 Output Output Data for GPIO Pins When Confi gured as General Purpose Output

4 Reserved Mass Write Enable Allows Mass Write Addressing

2 Channel 1 Overcurrent Auto-Retry Channel 2 Overcurrent Auto-Retry Overcurrent Auto-Retry Bit

1 Channel 1 Undervoltage Auto-Retry Channel 2 Undervoltage Auto-Retry Undervoltage Auto-retry

0 Channel 1 Overvoltage Auto-Retry Channel 2 Overvoltage Auto-Retry Overvoltage Auto-retry

Table 4. ALERT Registers B – Read/Write

7 Reserved Reserved Not Used

6 Reserved Reserved Not Used

5 Channel 1 FET Short Alert Channel 2 FET Short Alert Enables Alert for FET Short Condition

4 EN1 State Change Alert EN2 State Change Alert Enables Alert When EN Changes State

3 Channel 1 Power Bad Alert Channel 2 Power Bad Alert Enables Alert When Output Power is Bad

2 Channel 1 Overcurrent Alert Channel 2 Overcurrent Alert Enables Alert for Overcurrent Condition

1 Channel 1 Undervoltage Alert Channel 2 Undervoltage Alert Enables Alert for Undervoltage Condition

0 Channel 1 Overvoltage Alert Channel 2 Overvoltage Alert Enables Alert for Overvoltage Condition

Table 5. STATUS Registers C – Read

7 FET On FET On 1 = FET On, 0 = FET Off

6 GPIO1 Input GPIO2 Input Reports the State of the GPIO1

5 Channel 1 FET Short Status Channel 2 FET Short Status Reports the State of the GPIO2

4 EN1 Status EN2 Status Indicates If the Channel is Enabled When EN is Low

3 Channel 1 Power Bad Channel 2 Power Bad Indicates Power is Bad When FB is Low

1 Channel 1 Undervoltage Channel 2 Undervoltage Indicates Input Undervoltage When UV is Low

0 Channel 1 Overvoltage Channel 2 Overvoltage Indicates Input Overvoltage When OV is High

Table 6. FAUL T Registers D – Read/Write

7 Reserved Reserved Reserved

6 Reserved Reserved Reserved

5 Channel 1 FET Short Fault

3 Channel 1 Power Bad Fault

2 Channel 1 Overcurrent Fault

1 Channel 1 Undervoltage Fault

0 Channel 1 Overvoltage Fault

Table 7. ADC Register Data Format: ADINn, SOURCEn, SENSEn MSB Bytes – Read/Write* Table 8. ADC Register Data Format: ADINn, SOURCEn, SENSEn LSB Bytes – Read/Write* Table 9. ADC CONTROL Register E – Read/Write

7 Reserved Reserved

6 Reserved Reserved

4 ADC Alert Enables the ALERT Pin to Pull Low When the ADC Finishes a Measurement

0 Halt Stops the Data Converter and Enables Point and Shoot Mode

Figure 12. 3.3V and 12V Application with Sequenced Turn-On Optically Isolated I2C Communication

4222 TA03

5.00 ± 0.10 (4 SIDES) NOTE: 1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE M0-220 VARIATION WHHD-(X) (TO BE APPROVED) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6) 0.40 ± 0.10 BOTTOM VIEW—EXPOSED PAD

3.50 REF

(4-SIDES) 3.45 ± 0.10 3.45 ± 0.10 0.75 ± 0.05 R = 0.115 TYP 0.25 ± 0.05 (UH32) QFN 0406 REV D 0.50 BSC0.200 REF 0.00 – 0.05 0.70 ±0.05 (4 SIDES) 4.10 ±0.05 5.50 ±0.05 0.25 ± 0.05 PACKAGE OUTLINE

0.50 BSC

RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER R = 0.05 TYP 3.45 ± 0.05 3.45 ± 0.05 32-Lead Plastic QFN (5mm × 5mm) (Reference L TC DWG # 05-08-1693)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However , no responsibility is assumed for its use. Linear Technology Corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. PACKAGE DESCRIPTION G36 SSOP 0204 0.09 – 0.25 (.0035 – .010) 0° – 8° 0.55 – 0.95 (.022 – .037) 5.00 – 5.60** (.197 – .221) 7.40 – 8.20 (.291 – .323) 1234 5 6 7 8 9 10 11 12 14 15 16 17 1813 12.50 – 13.10* (.492 – .516) 2526 22 21 20 19232427282930313233343536 2.0 (.079) MAX 0.05 (.002) MIN 0.65 (.0256) BSC 0.22 – 0.38 (.009 – .015) TYPMILLIMETERS (INCHES) DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS 2. DIMENSIONS ARE IN 3. DRAWING NOT TO SCALE 0.42 ±0.03 0.65 BSC 5.3 – 5.77.8 – 8.2 RECOMMENDED SOLDER PAD LAYOUT 1.25 ±0.12 G Package 36-Lead Plastic SSOP (5.3mm) (Reference L TC DWG # 05-08-1640)

Figure 13. μTCA Application Supplying 12V Payload Power to T wo μTCA Slots

4222 TA02a