TC4040BP TOSHIBA | Alldatasheet
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TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4040BP, TC4040BF, TC4040BFN TC4040B 12 STAGE RIPPLE-CARRY BINARY (Note) The JEDEC SOP (FN) is not available in COUNTER / DIVIDERS Japan. TC4040B is 12 stage ripple carry binary counter having asynchronous clear function. This counter advances its a counting stage by falling edge of CLOCK input. When wo all RESET input is placed “H” , all the circuits are reset 16 Rail \\ regardless of CLOCK input making all the outputs (Q1 ques through Q12) to be “L’. ' wos . soe ae P (DIP16-P-300-2.54A) This is most suitable for frequency dividers, control circuits Weight : 1.009 (Typ.) and timing circuits.
16 Qe 16 oat
F (SOP16-P-300-1.27) FN (SOL16-P-150-1.27) Weight : 0.18g (Typ.) Weight : 0.139 (Typ.) MAXIMUM RATINGS PIN ASSIGNMENT CHARACTERISTIC SYMBOL RATING UNIT DC Supply Voltage Veg — 0.5~Ves + 20 Input Voltage V5 — 0.5~Vpp + 0.5 Output Voltage Vss -0.5~Vpp + 0.5 ——_ Qi2 1 16 Vpp
7 Q6 2 15 Q11
Operating T. ~40~85 °C Temperature Range opr Q5 3 14 Q10 Storage Temperature ~ ©, Q7 4 13, Q8 Ranoe Tstg -65~150 Cc of 5 12 99 TRUTH TABLE Q3 6 11 RESET CLOCKA RESET OUTPUT STATE Q2 7 10 clock 4: Level Change , *: Don’t Care 961001EBA2 fail due to their inherent electrical sensitivity and vulnerability to physical stress, it the responsiblity of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to, property.n developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. T997-12-11 1/7
aa D D> D > D D Q Qi Q Q Q Q A RESET 7;—De° iQ iQ {Q Q ‘Q iQ cK cK ck cK cK cK | | | D D D Y Y Y VY VY VY 1 15 14 h2 13 4 Qi2 Qiu Q10 Qo Qs Qq7
961001 EBA2’
3 The products described in this document are subject to foreign exchange and foreign trade control laws. The Information contained herein is presented only as a guide for the applications of our products. No responsibilty is assumed by TOSHIBA CORPORATION for any'iniringements of intellectual property or ther rights ofthe third partes which fay result from 1s use. No license is granted by implication or otherwise under any intellectual property or other rights o¥ TOSHIBA CORPORATION or others. @ She information contained herein is subject to change without notice a cxadw— FT TTT OT
RECOMMENDED OPERATING CONDITIONS (Vss = OV) STATIC ELECTRICAL CHARACTERISTICS (Vss = OV) cuaracreristic |SY™-] test conDITION [V UNIT 80. Ca wae [a rv wa [ 7 5] 4.95 4.95 | 5.00 4.95 High-Level ‘tage | VO" Hour] 148 10) 9.95 9.95 | 10.00 9.95 utput Voltag IN= Nssr VoD 15| 14.95 14.95 | 15.00 14.95 V 5 0.05 0.00 | 0.05 0.05 owe ta 2 | You Vour| sta 10 0.05 0.00 | 0.05 0.05 P 9 IN=Nssr Von 15 0.05 0.00 | 0.05 0.05 mA Vo. =0.4V 5] 0.61 osi] 15 0.42 Vour=0.5V, 4.5V | 5] 3.5 35] 2.75 35 v Vour=0.5V, 4.5v | 5 15 2.25] 15 15 [our] <1 iow Steel] evn tev fa] — | oa — [we] er] — | a) current“ tevel| k[Varov —[v@[ = [=e1 | — [-0=[-o1] — |=10] | 5 0.005 150 | “A Quiescent Supply Vin =Vss, Voo # 10 0.010 300 15 0.015 600 * All valid input combinations. TTT TT TTT
DYNAMIC ELECTRICAL CHARACTERISTICS (Ta = 25°C, Vss = OV, C, = 50pF) Output Transition Time 70 200 (Low to High) thu 35 100 30 80 Output Transition Time 5 70 200 (High to Low) tra 10 35 100 15 30 80 Propagation Delay Time t 4 +0 TLOCK - pLH (CLOCK - Q1) 65 130 Propagation Delay Time t v0 ‘eo ns . pHL (CLOCK - 01) 15 65 130 Propagation Delay Time 900 1800 (CLOCK - 012) tw 450 300 360 720 Propagation Delay Time 5 900 1800 (CLOCK - Q12) tone 10 450 900 15 360 720 Propagation Delay Time 150 280 (RESET -Q) tone 70 120 50 100 5 3.5 10 Max. Clock Frequency fa 10 8.0 20 MHz 15 12.0 25 50 140 Min. Clock Pulse Width tw 20 60 15 40 Min. Pulse Width 5 100 200 (RESET) tw 10 40 80 ns 15 30 60 Min. Removal Time t 150 rareaa rem (RESET - CLOCK) 100 won Te 5 Max. Clock Input Rise Time tree 10 No Limit ys Max. Clock Input Fall Time | ticr 15 [input capacitance | cw P| | 1997-12-11 4/7
WAVEFORMS FOR MEASUREMENT OF DYNAMIC CHARACTERISTICS WAVEFORM 1 20ns 20ns 90% clock 50% 50% 50% 10% 10% tn fw 30% 90% Q 50% 50% | 10% 10% ‘town to WAVEFORM 2 20ns 20ns 30% 90% RESET 50% 50% 10% 10% ty CLOCK , , 50% Q |) 50% ton 997-T2- 5/7
DIP 16PIN OUTLINE DRAWING (DIP16-P-300-2.54A) Unit in mm
6 A aa V5
Fl =f as g 7 é ae 19.75MAX (.9520.1 a—2 moe 2.7357, | [rato 501 DET im e0.25@) Weight : 1.00g (Typ.) SOP 16PIN (200mil BODY) OUTLINE DRAWING (SOP16-P-300-1.27) Unit in mm 16 9 HHEAAABYA z jt | 8 10.8MAX 10.3#0.2 a x 3 2 = = =] s. = 3 0,810.2 Weight : 0.18g (Typ.) 9-12-11 OT
SOP 16PIN (150mil BODY) OUTLINE DRAWING (SOL16-P-150 -1.27) Unit in mm (Note) This package is not available in Japan. 16 9 st a Hg s| é 1 | 8 9,940.1 a g an an g S g te & Es S 0.70.3 Weight : 0.13g (Typ.) 1997-12-11 7/7