TC4027

TC4027BP TOSHIBA | Alldatasheet

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TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4027BP, TC4027BF, TC4027BFN (Note) The JEDEC SOP (FN) is not available in TC4027B DUAL J-K MASTER-SLAVE FLIP FLOP Japan. TC4027B is J-K master-slave flip-flop having RESET and SET functions. — In the case of J-K made, when the clock input is given with oe rial both RESET and SET at “L”, the output changes at rising 16 Rail u edge of the clock according to the states of J and K. J yu When SET input is placed at “H”, and RESET input is ~ P (DIP16-P-300-2.54A) placed at “L”, outputs become Q=“H”, and Q=“L”. Weight : 1.009 (Typ.) When RESET input is placed at “H”, and SET input is placed at “L”, outputs become Q=“L”, and Q=“H”. > _*, When both of RESET input and SET input are at “H”, 6& GE 16 & FG outputs become Q=“H” and Q=“H”. 1 1 F (SOP16-P-300-1.27) FN (SOL16-P-150-1.27) Weight : 0.189 (Typ.) Weight : 0.13g (Typ.) MAXIMUM RATINGS PIN ASSIGNMENT CHARACTERISTIC SYMBOL RATING UNIT DC Supply Voltage Vs = 0.5~Ves + 20 qi 16 Voo Input Voltage V5 - 0.5~Vpp + 0.5 a 2 15 Q2 Output Voltage Vs - 0.5~Vpp + 0.5 clock! 3 14 Q DC Input Current [ow | #10 | ma | RESETI 4 13 CLOCK2 Power Dissipation [Po _ [300 (DIP)/180 (SOIC) Ki 5 12 RESET2 Operating Temperature _A0~ 0 Range Topr 40~85 Cc a6 WW K2 Storage Temperature EET °, SET1 7 10 J2 Range Tstg 65~150 C Vss 8 9 SET2 LOGIC DIAGRAM (TOP VIEW) 1/2 TC40278 Q iis BLOCK DIAGRAM SET Do > 779 LT 7 9 Kon 'D) [ts Lo a =p Dy wD oD) a0 5 5 ad a 6—J Q—1 104) Qr—-15 3 —{ck 13 —]ck bo— Q 5K Q-2 1—-kK Q-14

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fall due to their inherent electrical sensitivity and vulnerability to physical stress. Ris the responsibilty of the buyer, when utiizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to, property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges. as set forth in the most Fecent products specifications. Also, please keep in'mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook as 17 05 EE Vy

pe fe |. fe} fe Paw Te | a ee A: Level Change a ee , + :No Change 961001EBA2" ihe products described in this document are subject to foreign exchange and foreign trade control laws The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third partis which may result from its use. No license Is granted by implication or Otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. T997-12-11 2/7

RECOMMENDED OPERATING CONDITIONS (Vss = OV) STATIC ELECTRICAL CHARACTERISTICS (Vss = OV) cuaracreristic [Y=] test conpiTION [V UNIT 80. Ca wae [a rv wa [ 7 5] 495 4.95 | 5.00 495 High-Level ‘tage | VO" Hour] 148 10) 9.95 9.95 | 10.00 9.95 utput Voltag IN= Nssr VoD 15| 14.95 14.95 | 15.00 14.95 V 5 0.05 0.00 | 0.05 0.05 owe ta 2 | You Vour| sta 10 0.05 0.00 | 0.05 0.05 P 9 IN=Nssr Von 15 0.05 0.00 | 0.05 0.05 mA Vour=0.5V, 4.5V | 5] 3.5 35 | 2.75 35 Vv Vour=0.5V, 4.5v | 5 15 2.25] 15 15 [our] <1 input ["H*tevell iy [vw=tav_[ ] — | or — | ws] orf — [10] current [*ueel| k[vizov |e — [=| = [==] =o] — [10 Quiescent Suppl 5 1 0.002] 1 30 | #A Cunent upply Vin =Vss- Voo* 10 2 0.004] 2 60 15 4 0.008 | 4 120 * All valid input combinations. TTT TT TTT

DYNAMIC ELECTRICAL CHARACTERISTICS (Ta = 25°C, Vss = OV, C. = 50pF) Output Transition Time 70 200 (Low to High) thu 35 00 30 ‘0 Output Transition Time 5 70 200 : trae 10 35 100 (High to Low) 15 30 80 Propagation Delay Time toy " 0 (CLOCK - Q, Q) tone 60 90 Propagation Delay Time ton m4 +30 (SET, RESET -Q,Q) tone 15 a5 90 3.5 8 Max. Clock Frequency fa 8.0 16 MHz 12.0 20 «Te 5 Max. Clock Input Rise Time | tia. oe Max. Clock Input Fall Time | tc. is No Limit as Min. Pulse Width t 2 v0 (SET, RESET) w 25 50 5 60 140 Min. Clock Pulse Width tw 10 35 60 15 25 40 Min. Set—up Time t * “ (J, K- CLOCK) se 5 35 Min. Hold Time 5 140 (J, K- CLOCK) ts 10 30 ns ‘ 15 35 Min. Removal Time t 20 (SET, RESET - CLOCK) rem 15 [input Capacitance | cw Ps Tr | 1997-12-11 4/7

WAVEFORMS FOR MEASUREMENT OF DYNAMIC CHARACTERISTICS WAVEFORM 1 20ns 20ns E 90% 90% CLOCK if 50% F) 10% 10% Q / 50% i; 50% tot tpHL WAVEFORM 2 20ns 20ns \\ 90% ) 90% SET 50% 10% 10% 20ns 20ns | 90% 90% RESET rf 50% f 10% 10% 90% . 90% Q 50% 50% | 4] 10% 10% toLH ‘toHL WAVEFORM 3 20ns 20ns 90% 90% JK 50% 10% 10% tsy.| [th + 20ns 20ns 90% 90% cLock 50% 10% 10% tru tHe 90% 90% Q 10% 10% T997-T2- 5/7

DIP 16PIN OUTLINE DRAWING (DIP16-P-300-2.54A) Unit in mm

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Fl =f as g 7 é ae 19.75MAX (.9520.1 a—2 moe 2.7357, | [rato 501 DET im e0.25@) Weight : 1.00g (Typ.) SOP 16PIN (200mil BODY) OUTLINE DRAWING (SOP16-P-300-1.27) Unit in mm 16 9 HHEAAABYA z jt | 8 10.8MAX 10.3#0.2 a x 3 2 = = =] s. = 3 0,810.2 Weight : 0.18g (Typ.) 9-12-11 OT

SOP 16PIN (150mil BODY) OUTLINE DRAWING (SOL16-P-150 -1.27) Unit in mm (Note) This package is not available in Japan. 16 9 st a Hg s| é 1 | 8 9,940.1 a g an an g S g te & Es S 0.70.3 Weight : 0.13g (Typ.) 1997-12-11 7/7