TC40160BP TOSHIBA | Alldatasheet
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’ ’ C*MOS DIGITAL INTEGRATED CIRCUIT TC40162BP TC40163BP SILICON MONOLITHIC ’ SYNCHRONOUS PROGRAMMABLE 4-BIT COUNTER TC40160BP DECADE WITH ASYNCHRONOUS CLEAR TC40161BP BINARY WITH ASYNCHRONOUS CLEAR . TC40162BP DECADE WITH SYNCHRONOUS CLEAR 40163BP_ BINARY WITH SYNCHRONO AR The TC4O160BP, TC40161BP, TC40162BP, and TC40163BP are synchronously programmable 4-bit counters. The TC40160BP and TC40161BP are decimal counter and 4-bit binary counter respectively having asynchronous clear function which directly clears all the flip- flop outputs. The TC40162BP and TC40163BP are decima 16 counter and 4-bit binary counter respectively which 1 are synchronous at the rising edges of clocks. CLEAR and LOAD of these counters are active at the DIP 16(SD1¢A-P) "L" level, Further, these counters are functionally compatible with the 74160, 74161, 74162, and 74163 of TTL. MAXIMUM RATINGS PIN ASSIGNMENT Input Voltage vin | Vss-0.5 ~ Vppt0.5 cioce gz 159} CARRY OUT Operating Temperature _ ° Pa fle gia Range 40 ~85 c PE 7 108 re Storage Temperature ’ TOAD cd ee Lead Temp. /Time 260°C + 10 sec (70P VIER) TRUTH TABLE ee . ' ee Ce * : No ch Ce re CS ee fast ow [uw [i fefe[e [ele] [ee [ps mee or” a Fl wt [e pepe pete fet vs) (r04b160,, 140161) fa F [ow | wu [ule [efoto fo Te] TT sce cage laf] ow | wa fwja tele le [s | cour | | ctcsois2, resorss) feat we [+ ie [e]e[e [ete | T- fe TI
TC40160BP, TC40161BP, TC40162BP, TC40163BP SS LIGIC DIAGRAM (TC40160BP, TC4°1c2BP) clock o> m7 > = —— oO J oo LH TAD >-+t-D PSS SSS DD dp abtDp—- a [_[(_$_Q0ouj$reFNNEHSSOKe{j"$tHtééNNN SE] OD L al a (ee ee P2 ~—D HDT If : a =D D1, fH SS ——— Pas De-D—o as
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a oo — on + i) oe = lr ee lm Deo as i 1) pel pt] H—b 5. ; CARR 4_) >—-p— ep oar TIMING CHART (TC40160BP, TC40162BP) ‘RESET hata Pe -~ DTD DTT T ITD LL INPUT Ps —_ - - - a _ _ a — * pSeSSSSSESSTSTE clock BKABLK T™ Cor o = ee Ls « oii }— OoTPUT aw = =a we > | Fd CARRY OUTPUT (| |] agiee Sikc PRESET " ° coum ® INHIBIT
TC4O160BP, TC401618P, 1¢40162BP, TC40163BP TCO OB, TCAD TBBP, TCAOTEZEP, TCAOTE SBP LOGIC DIAGRAM (TC40161BP, TC40163BP) jd LU PF) ° Do—d> or a, | Hu =D fe PTH |__| 4 a PDD A po HE Ee Ep itn De-d>o ae Pp, o—Do-D SST Ue co | —_ (+ a R 1 ee eer Tihs l |. — = oH Pe TER, . ——=—D— DP ID agp+Do-d>o ag TIMING CHART (TC40161BP, TC40163BP) ‘RESET Toad Py so ort rr TTT TT " ZlLlLLLliliiie: ores rine {72 P,ILTLLIILili= * FIEPETPFTELIE ~ eo 7 Qe eo a oe carey ovnuT [| 305 .
TC40160BP, TC40161BP, TC40162BP, TC40163BP ———— RECOMMENDED OPERATING CONDITIONS (Vss=0Vv) pc Supply voltage | vp [| Tt Tw input Voltage [vm [ot Pv | STATIC ELECTRICAL CHARACTERISTICS (Vgs=0v) sem w BOL, Woprl <laa 5] 4.95 4.95] 5.00 4.95 High-Level ‘our! <: Vi 10} 9.95 9.95]10.00 9.95 output Voltage OF vineVss,Vpp 15|14.95 14.95]15.00 14.95) v Low-Level ‘ouT output Voltage | Yl ys eves, Upp 10 0.05 0.00] 0.05 0.05 15 0.05 0.00} 0.05 0.05 output High - . . 7 . VIN=Vss,VpD Output Low VoL=0.5V lo} 1.5 1.3] 3.8 1a current ToL Vin=Vss, VoD Voltage TH loyr! < 14a v Voltage VIL Vopr! <1a4 Trp] Vin=18V 0.1 10-5) 0.1 1.0 soe [teen] after Yael = | oa] = Pe of = [a Current ["L" a = - 306
TC40160BP, TC40161BP, TC40162BP, TC40163BP STATIC ELECTRICAL CHARACTERISTICS (Vss=0V) cunsacrenrstre [S%-)rest coxortios [pp unite co) | srw. [ax ow. [ mvp. [wax] on] max 5 5 0.005} 5 150 Quiescent Device . Current Top] VaN=Vss. Yop 10 10 0.010} 10 300 | nA 45 20 0.015} 20 600 * All Valid input combinations. DYNAMIC ELECTRICAL CHARACTERISTICS (Ta=25°C, Vss=0V, CL=50pF) CHARACTERISTIC SYMBOL MIN. MAX. Vpp(V) 5 80 200 output Transition Time (Low to High) tTLH 10 50 100 15 40 80 ns 5 80 200 Output Transition Time (High to Low) CTHL 10 50 100 1s 40 80 Propagation Delay Time | tpn 5 250 500 (CLOCK - Q) tpHL 10 100 200 15 70 140 > tion Delay Ti te 5 300 600 ropagation Delay Time pee y pLH 10 120 240 (CLOCK-CARRY OUT) tpHL 1s 80 160 5 ton Delay i ts 5 170 340 ropagation Delay Time LH cre caRay out) a x 88 we PHL 15 45 90 Propagation Delay Time 5 180 500 (RESET - Q) tpu. 10 “75 220 40160, 40161 Only 15 55 160 5 130 | 250 Min. Clock Pulse Width 10 45 90 15 30 60 Min. Pulse Width 5 M40 280 (ESET) twh 10 55 110 40160, 40161 Only is 35 70 307
TC40160BP, TC40161BP, 1C40162BP, TC40163BP DYNAMIC ELECTRICAL CHARACTERISTICS (Ta=25°C, Vss=0V, Cy=50pF) 5 2 4 Max. Clock Frequency fot 10 5.5 1 15 8 16 Max. Clock Input Rise | | 5 Time. CL _ Max. Clock Input Fall tech 10 No Limit as Time. 15 5 55 ] 240 Min. Set-up Time Pn CLDCR) tsu 10 20 90 15 15 60 5 75 | 240 Min. Set-up Time on tsu 10 30 90 (OAD - c1ocK) 15 20 60 5 190 | 380 Min. Set-up Time tsu 10 70 | 140 (PE, TE = CLOCK) 15 so | 100 Min. Set-up Time 5 50 | 310 (RESET - CLOCK) tsy 10 20 110 40162, 40163 Only 15 15 70 Min. Hold Time 5 ° (Pn, TOAD, PE, TE~ 10 ° CLOCK) 15 5 Min. Hold Time 5 =30 0 (RESET - CLOCK) ty 10 -10 0 40162, 40163 Only 15 “5 0 Min. Removal Time 5 so | 200 (RESET - coLcK) trem 10 25 | 100 40160, 40161 Only 5 15 70 [ist cociance [ew Po 308
TC40160BP, 1C40161BP, TC40162BP, TC40163BP ea WAVEFORM FOR MEASUREMENT OF DYNAMIC CHARACTERISTICS WAVEFORM 1 w 90% CLOCK 50% 50% fl 10% Ob tTLH trHL Snr ovr =F ee (10% wg WAVEFORM 2 WAVEFORM 3 (40162, 40163) 20ns 20ne 20n8 20n8 — Toe 0% 30% TE 50 \\\\ 50% RESET 0 50% f- 10% ri 20% H- 10% 4-104! WAVEFORM 4 (40160, 40161) WAVEFORM 5 2% w \\ Fe \\ fo os WSS Ker Ye 20 ne 20n8 Z0ne . 304 90% euock 08 OD 80% 50% A 10% 10. 108 7) 9% fA r0% oF tpHL 20ne H—i08 [ese | tH 309
TC40160BP, TC40161BP, TC40162BP, TC40163BP APPLICATION CIRCUIT 1. Cascaded counter packages in the parallel-clocked mode. P] Pe Pg Py PL Pp Ps Py P) Po Ps Py Ypp rater | po Lp LDP; Pa Ps Pe Pe to 7 fi 7 [ Less di de Qs Qe EE [4 cLock | [TT Tt Ty [Ty TT _ yecr ot _[| | TT TT PT Tt yy Pp pt Gag & a a2 as ay at ae as 310