TSC332 MICROSEMI | Alldatasheet

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=RES TSC332/333/334/335 — ER/ Fd Hex Inverter Gates

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Watertown, MA 02172 LABS e 4-Inverter, 2-NAND (Open Collector) (S17),224,9260 e 4-Inverter, 2-NAND (Passive Pullup) Strobed Hex NAND (Open Collector) e Strobed Hex NAND (Passive Pullup) CD Features General Description 332/333/334/335 332/333/334/335 ® FOUR INVERTERS AND TWO GATES IN 332/333 The 332 and 333 provide four inverters and two 2-input NAND ® COLLECTOR OR’ABLE gates for applications such as “wire-OR” logic systems and © 332 SINKS UP TO 16 mA AT 12V and 20 mA AT 15V wntezt . Nanetrr f - © 332/334 OUTPUT LEVELS ADJUSTABLE TO DTL, TTL interfaces with other logic families. The 332 is used with an OR MOS LEVELS external pullup resistor while the 333 has puliup resistors on the © 333/335 HAS PULLUP RESISTORS ON CHIP chip. The 334 and 336 contain six 2-input NAND gates connected such that two gates share one strobe input and four gates share another strobe input. The configuration is ideal for applications such as transferring data in parallel from one register i another. The devices may also be used in “wire-OR” logic systems and for the interfaces with other logic families. Logic Diagram 332/333 334/335 194) —Po— 0110 (ranay oy 113) 09142 —f>o— orm a imag 02 (11) (as —_p>-— 0318) ma com (12 4 SPD aun (8) Aa. Ca (7) wie Os (5) tae [ove BAe: GRO-8 mey oe) Veco - 16 GAD-8 Voc - 16 Equivalent Circuits 332/334 333/335 Ovee O ce rok ] We 4 oo mK ai “HD a = * Ocno 3-25

Hex Inverter Gates 332, 333, 334, 335 Specifications gc (WORST-CASE) 2B mA @ 13V,42 mA @ 16V pp 140 ns | 350 ns 1/0 FUNCTION FOR tpp | A+O- | A-O+ . tpp 140 ns 1/0 FUNCTION FOR tpp | A+O- NOTE: lgg is tested at Veg +1 Volt (+13V for C type and +16V for A type) and is guranteed across the applicable temp range. tpp is guaranteed at Voc 21V and across the applicable temp rage with the output loaded with 5 unit loads. ‘See page 12 for electrical summary data. Switching Time Waveforms ete OE ete hy f ' 1 1 i urna au oy sour! Kom i 7 Loading Tables 332/333 334/335 PINS FUNCTION LOADING [Pins | FUNCTION LOADING AS Inputs TUL A Data Inputs TUL

0 Outputs 5 UL (333) B Strobe Input 2UL

7 UL (332 with 5 KQ c Strobe Input |4UL

pullup resistor) fe} Outputs 5 UL (335)

7 UL (333 with 10 K2 7 UL (334 with 5 KO

supplemental pullup. pullup resistor) resistor) 7 UL (335 with 10K 332 also handles 4 TTL loads at 400 mV supplemental pullup resistor) 334 also handles 4 TTL loads at 400 mV Typical Performance Characteristics INPUT CURRENT OUTPUT CURRENT VS OUTPUT VOLTAGE Preece VS. INPUT VOLTAGE OUTPUT HIGH® OUTPUT LOW area? “a a Bel] OW SE nl ie NS OTT | | Le | LISS - lee pi S8se Sooo I Pea] | LTTE NSS] 4 A ra wo Her] | | LITT TINSN Cp eee ETT | | | wed) | | bret TPN | “EA aaa at oa 08 F008 00 a C vm ‘ona? tosina! *333, 335 only 3-26

Hex Inverter Gates 332, 333, 334, 335 Typical Applications Rules for selecting external resistors and calculating fanout with collectors OR‘d are given in the applications notes. The external resistor of the 332 or 334 may be connected to a CLOCKED S-R FLIP-FLOP WITH BUFFERED OUTPUTS voltage other than Vcc to adjust the output voltage level. To use the NAND gates as inverters, the A and B inputs may both be connected to the same input data line, or one input may be connected to Vcc. For transfer of data, the strobe input is held high, Data on the Ser, A inputs of those gates will appear inverted on the outputs. : When the strobe input is low, the outputs remain high. If the _ two strobe inputs are connected, six lines of data may be trans- 1 ferred with one strobe control (presenting 6 unit loads). PARALLEL TRANSFER OF DATA . a seossten | aecisten Bimal Q a Q = | Q aeciste a REGISTER ea [—] ee gO REGISTER neosten LT | & Taansten ‘Two 335 strobed hex inverters transfer 12 lines in parallel from register A, B and C to register X, Y and Z when the strobe input (transfer line is momentarily taken high. The data inversion during transfer is circumvented by using the 0 outputs of registers A, B and C. Each of these registers may be made with a pair of 321 quad NAND gates. 3-27

Hex Inverter Gates 332, 333, 334, 335 Typical Applications (contd.) TTL INTERFACE FIVE-INPUT OR GATE SIXANPUT OR GATE 332 332/333 332/333 , pare” —>- ‘This type of interface will protect TTL date processing systems from electromechanical noise generated in peri- pherals. The vaiue of R is selected by the rules given in the applications notes, except that pullup is to 5V rather then 12V oF 15V Voc. ‘ec O BIDIRECTIONAL BUSING (MEMORY SYSTEM EXAMPLE) ae (el oT sp | + —1»> re [| } Ly 6, _| E TPU a a a ( a FD c 3 a ED: EF LED o a0 Y + —L) 1E=2, Ly [TT > word! wORD! ESYy e@eee ROM #ROM —— 3-28