TC312

TC312 ETC | Alldatasheet

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580 Pl it Street Flip Flops

jeasan' reel Watertown, MA 02172 LABS ¢ Master/Slave RST (617) 924- - SIT) BehS280 © Dual J-K Edge Triggered ¢ Dual J-K Master/Slave SS eee ee eee Features General Descriptions 311 311 © NOT EDGE-SENSITIVE The 311 is a clocked master/slave flip-flop that can operate in @ DIRECT SET AND RESET INPUTS set-reset or J-K modes. Applications flexibility is increased by BSA CATA INTE three data inputs to each side of the master flip-flop and by © SERARATE CLOCKINEUTS/ALLOW TWO-PHASE two clock inputs, it provides three S-R inputs, or two JK in- OPERATION puts, and operates single-phase or two-phase. 312/313 312/313 © CAI BESET OR IRESEL Witt CCockHiGHOn COW’ The 312/313 provides two fast, edge-triggered flip-flops in a © CLOCK INPUTS ARE ONLY 1 UNIT LOAD single package. Separate logic inputs allow them to be used in- @ J-K OR S-R OPERATION (313 J-K MASTER/SLAVE) dependently as J-K or set-reset flip-flops. Clock inputs present @ FAST—5 MHz TYPICAL TOGGLE RATE only 1 unit load. @ EDGE-SENSITIVE OPERATION (ON 312) For use in new designs, the non-edge sensitive 313 is © NON-EDGE SENSITIVE OPERATION (ON 313) recommended. Logic Diagrams 311 - 312/313 on ‘in wal om } bas BD waster z= soye Com wa o <i ES 00) on Die [| rio Os an & ann a, aon ar : voe= "8 a me a= On 313 FF1 and FF2 are master/slave flip-flops. Truth Tables +K MODE S-R MODE [a] x [om] [sale] c}L] a H/H cfu} oe HL HI L H Liu HLH] oO ete X = Indeterminate state 3-9

Flip Flops 311, 312, 313 Equivalent Circuits TYPICAL OUTPUT TYPICAL INPUT Voc © 7 s10n R Sige ier < 7 R= 8.2K ONA,B,5, R,T2 R= 4.1K ONT}, Specifications 311 PD 820ns | 610ns | 400ns| 250ns 1/0 FUNCTION FOR tpp | T-Q+ | T-a- | R-G+ | R-G- TYPICAL TOGGLE RATE is 2 MHz 312,313 eD 300 ns | 230ns | 600 ns 1/0 FUNCTION FOR tpp | T-O+ T-Q- R-Q+ TYPICAL TOGGLE RATE IS 5 MHz NOTE: tec is tested at Veg +1 Volt (+13V for C type and +16V for A type) and is guaranteed across the applicable temp range. tpp is guaranteed at V¢c #1V and across the applicable temp range with the output loaded with 6 unit loads, See page 12 for electrical summary data Switching Time Waveforms ‘aiasia aio —\\-m ew i. <n = j { melo toate woronee| bee 1 | 1 i) io a 1 - fas | i \\ f i i 1 i) NOTE: Jand K are tied to Veg. Loading Tables 311 [Pins _| FUNCTION LOADING AB Data inputs TUL

1 Clock input 2UL

[pins __| FUNCTION LOADING JK J-K inputs TUL T Clock inputs TUL SR Direct 5-R inputs 2UL ad Outputs 5UL 3-10

Flip Flops 311, 312, 313 Loading Tables (contd.) 313 [pins __|[ FUNCTION LOADING JK Data inputs TUL T Clock input TUL RS Direct Set/Reset | 2UL Inputs feke} Outputs 5 UL Typical Performance Characteristics INPUT CURRENT OUTPUT CURRENT VS OUTPUT VOLTAGE pura, “SnINFUTVOLTAGE OUTPUT HIGH OUTPUT LOW oe 4 2 2s eT Boo ooo 28 04) fs a 20 Pla) OHSU Oe Ser os OSs soe z 5 S s eet aT wT Fe | =e ccs Vw low ima fou tm) Typical Applications 311 312 AND gates A and B form the set and reset inputs of the master The 312 triggers on the falling edge of the clock pulse, which flip-flop. The slave has direct set and reset inputs that operate must fall faster than 3V/microsecond for proper operation. active low (for example, the R input is switched low while the Direct set and reset may be accomplished at any time, with the clock is high to reset the flip-flop). Also, input T2 has a built-in clock either high or low. inverter to inhibit data transfer from the master to the slave when the clock is high. The T1 and T2 thresholds are offset as 313 shown on the single-phase timing diagram, to ensure proper The 313 was developed to give the HiNIL logic designer the inhibition of the master and slave in the single-phase mode. most flexible dual flip-flop package possible. The 313 is cap- able of J-K Master/Slave or S-R operation with set and reset Since there are three sets of master inputs, two J and K inputs inputs. are available in the J-K connection. In either the set-reset or — | J-K modes, single-phase operation is obtained by connecting The timing diagram shown on page 28 indicates the operation se- T1 to T2, or two-phase operation by applying out-of-phase quence for J-K Master/Stave operation. The positive going edge clocks to Ty and T2. of the clock pulse inhibits the slave and enables data transfer

311 CONFIGURATION

SET-—RESET MODE J-K MODE 3 § L) es S L) ° a: Def th = el " % s " TR a 3-11

Flip Flops 311, 312, 313 Typical Applications (contd.) MASTER THRESHOLD DATA Tw TOMASTER rancor orrtr | ~ Se eR ere, TP Bvimsires ne SLAVE THRESHOLD to the master (Master/Slave thresholds are offset to ensure proper inhibition and enable). The falling edge inhibits the Clock Pulse Width (CP) 300 nsec min. master and allows data transfer to the slave. +-K Input Setup Time 2 cP J-K Input Release Time Onsec min. Direct set or reset may be accomplished at any time, with the SorR Pulse Width 300 nsec min. clock pulse either high or low. Clock Rise and Fall Time — N/A For reliable operation the following 313 timing recommenda- Due to the master/slave action of the 313, data must be present tions should be followed. They apply across both the applic- during the entire time the clock is high to ensure proper data able temp range and Vcc spread. transfer to the output. NOTE: Because of the high noise immunity of the 312/313, it can be used ina variety of counter configurations with inexpensive diodes replacing the external gating normally required. Use IN4148 or similar high-voltage 312, 313 CONFIGURATIONS diodes or the diodes in a 331 gate expander. SYNCHRONOUS MOD 5, BINARY CODED OUTPUT Q vec TRUTH TABLE ¢ 0 0 0 i a i o} 1] 0 en) ra} ato o| oj o Shot SYNCHRONOUS MOD 5, SHIFT MODE TRUTH TABLE =e [+ [en] 08 | ac | ° oO ° Cys {st ijeis 1] 1] 0 or es of ofa ‘wrut © o|o|o TRUTH TABLE MOD 6, BINARY CODED OUTPUT o| ol] o 1 ° o i 2 o in c | | r}a]o «, 3 ce, 8 o| oj 1 r}o}.4 ‘Sito ei els 3-44

Flip Flops 311, 312, 313 Typical Applications (contd.) SYNCHRONOUS MOD 6, BINARY CODED OUTPUT TRUTH TABLE | ofo|o o2 im 1lele 4 4 0 1 ° TUES PpEE 4HE rfofa woce fT SARE © oj] olfo SYNCHRONOUS MOD 7, BINARY CODED OUTPUT a, oe vs TRUTH TABLE q o ° oO [idl 1] 0] 0 BD, q 1 1] 0 aiden ane 1 o 1 |) j o}at 4 —— oT oj} 9 exe aero re SYNCHRONOUS MOD 9, BINARY CODED OUTPUT TRUTH TABLE oy % ee 2% Yee % H [7 [ea | 08 | ac | 20 | a ox olo|ofo|o 4 1{ 1] o]o]o > 4 2}o}1]}]o0]o0 foe Tic afi falole bi q a4} o}ol1jo 7 | q q s}1|ol1]o 6}o}1}r}o } bs 1 1 1 ° s}o]of]o|. e.0¢%.9 —— Sie 1 oj ej eer SYNCHRONOUS BCD DECADE COUNTER q o{o]of]o]o { { I ifr ]{olo]o 4 4 al 2/o]1]o]o q q mi s}1}o]1}o A elo} tr} a] o vlatatato } } i s]o}o]o|]4 SSSI es; tr] oy; o)4 SS w}o}o|}olo 3-13