TC281

TC281_03 TI1 | Alldatasheet

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1036- × 1010-PIXEL CCD IMAGE SENSOR SOCS058D – JUNE 1996 – REVISED MARCH 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 High-Resolution, Solid-State Frame-Transfer Image Sensor /C0068 11.3-mm Image Area Diagonal /C0068 1000 (H) x 1000 (V) Active Elements /C0068 Up to 30 Frames per Second /C0068 8-µm Square Pixels /C0068 Low Dark Current /C0068 Advanced Lateral Overflow Drain for Antiblooming /C0068 Single-Pulse Image Area Clear Capability /C0068 Dynamic Range of More Than 60 dB /C0068 High Sensitivity and Quantum Efficiency /C0068 Nondestructive Charge Detection Through Texas Instruments Advanced BCD Node Technology /C0068 High Near-Infrared (IR) and Blue Response /C0068 Solid-State Reliability With No Image Burn-In, Residual Imaging, Image Distortion, Image Lag, or Microphonics

description

The TC281 is a frame-transfer charge-coupled-device (CCD) image sensor that provides high-resolution image acquisition capability for image-processing applications such as robotic vision, medical X-ray analysis, and metrology. The image-sensing area measures 8 mm horizontally and 8 mm vertically; the image-area diagonal measures 11,3 mm and the sensor has 8-µm square pixels. The image area contains 1000 active lines with 1000 active pixels per line. The dark reference signal can be obtained from ten dark reference lines located between the image area and the storage area, 28 dark reference pixels located at the left edge of each horizontal line, and 8 dark reference pixels located at the right edge of each horizontal line. The storage section of the TC281 device contains 1010 lines with 1036 pixels per line. The area is protected from exposure to light by a metal layer. Photoelectric charge that is generated in the image area of the sensor can be transferred into the storage section in less than 110 µs. After the image capture is completed (integration time) and the image is transferred into the storage, the image readout is accomplished by transferring charge, one line at a time, into the serial register located below the storage area. The serial register contains 1036 active pixels and 9 dummy pixels. The maximum serial-register data rate is 40 megapixels per second. If the storage area must be cleared of all charge, charge can be transferred quickly across the serial registers into the clearing drain located below the register. A high performance bulk charge detection (BCD) node converts charge from each pixel into an output voltage. A low-noise, two-stage, source-follower amplifier further buffers the signal before it is sent to the output pin. A readout rate of 30 frames per second is easily achievable with this device. This MOS device contains limited built-in gate protection. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to VSS . Under no circumstances should pin voltages exceed absolute maximum ratings. Avoid shorting OUT to VSS during operation to prevent damage to the amplifier. The device can also be damaged if the output terminals are reverse-biased and an excessive current is allowed to flow. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2003, Texas Instruments Incorporated Î Î Î Î Î ÎÎ ÎÎ ÎÎÎÎ Î Î Î Î Î Î Î ÎÎ ÎÎÎ SUB 1 ODB 2 IAG 3 SUB 4 SAG 5 SAG 6 SUB 7 OUT 8 ADB 9 CDB 10 VGATE 11

22 SUB

21 TDB

20 IAG

19 SUB

18 SUB

17 SUB

15 SRG

14 TRG

13 VSOURCE

12 RST

(TOP VIEW) All trademarks are the property of their respective owners. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1036- × 1010-PIXEL CCD IMAGE SENSOR SOCS058D – JUNE 1996 – REVISED MARCH 2003

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description (continued) The blooming protection of the sensor is based on an advanced lateral overflow drain (ALOD). The antiblooming function is activated when a suitable dc bias is applied to the overflow drain pin. With this type of blooming protection it is also possible to clear the image area of charge completely. This is accomplished by providing a single 10-V pulse of at least 1 µs duration to the overflow drain pin. The TC281 image sensor uses TI-proprietary advanced virtual-phase (AVP) technology, the advanced lateral overflow drain, and the BCD detection node. These features provide the TI image sensing devices with a high blue response, high near-IR sensitivity, low dark current, high photoresponse uniformity, and single-phase clocking. The TC281 is characterized for operation from -10/C0095 C to 45/C0095 C. functional block diagram Top Drain Image Area Storage Area Serial Register and Transfer Gate Clearing Drain TDB

13 Amplifier

1036- × 1010-PIXEL CCD IMAGE SENSOR SOCS058D – JUNE 1996 – REVISED MARCH 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 sensor topology diagram

1000 Pixels

28 Pixels 8 Pixels

1000 Lines

10 Lines

1010 Lines

1 Pixel1 Pixel

1 Dummy Pixel

NAME NO. I/O DESCRIPTION ADB 9 I Supply voltage for amplifier drain bias CDB 10 I Supply voltage for clearing drain bias IAG 3, 20 I Image area gate NC 16 No internal connection ODB 2 I Supply voltage overflow drain antiblooming bias OUT 8 O Output signal RST 12 I Reset gate SAG 5, 6 I Storage area gate SRG 15 I Serial register gate SUB 1, 4, 7, 17, 18, 19, 22 Substrate and clock return TDB 21 NC Supply voltage for test diode TRG 14 I Transfer gate VGATE 11 I Bias voltage for the gate of the BCD node VSOURCE 13 I Bias voltage for the source of the BCD node

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1010 Clocks

1046 Clocks

1010 Cycles

Figure 1. Overview of Frame Timing with Variable Integration Figure 2. Expanded Parallel Transfer Timing

Figure 3. Expanded Storage Area-to-Serial Register Transfer and Pixel Readout Timing

9525 Clocks

Figure 4. Special Modes of Operation: Storage Area Clear

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Figure 5. Special Modes of Operation: Binning in the potential wells of the pixels. The wells have a finite charge storage capacity determined by the pixel design. and traded for the well capacity.

1036- × 1010-PIXEL CCD IMAGE SENSOR SOCS058D – JUNE 1996 – REVISED MARCH 2003 7POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 advanced lateral overflow drain (continued) Applying a 10-V pulse for a minimum duration of 1 µs above the nominal dc bias level causes the charge in the image area to be completely cleared. This feature permits a precise control of the integration time on a frame-by-frame basis. The single-pulse clear capability also reduces smear by eliminating accumulated charge from the pixels before the start of the integration (single-sided smear). Application of a negative 2-V pulse during the parallel transfer is recommended to prevent possible artifacts resulting from slight column-to-column pixel well capacity variations. storage area A metal light shield covers the storage area to prevent a further integration of charge when charge is being stored before readout. To use the sensor in a single-shot mode after being dormant for a long period of time, you must perform multiple storage area clears to ensure the complete charge removal (see Figure 4). serial register The serial register shifts the data out of the sensor area at a maximum rate of 40 MHz, thus achieving a 1000 x 1000 pixel readout with the frame rate of 30 frames per second. The data is shifted to the BCD node on the falling edge of the SRG clocking pulses. The data can also be transferred out of the serial registers in a parallel direction to the clear drain. This allows partial line readouts. The timing for this operating mode consists of transferring the next row from the storage into the serial register while also clocking the TRG. Binning of multiple pixels within a column to increase the device sensitivity can be performed by multiple line transfers into the serial register prior to the register readout. The timing for this mode of operation is shown in Figure 5. Care must be taken not to exceed the well capacity of the serial register by transferring too many lines into it. Horizontal binning is also possible in this sensor. It can be accomplished in the BCD detection node by a suitable skipping of the reset pulses. bulk charge detection node and output amplifier The TC281 image sensor uses a patented TI charge detection device called the bulk charge detection node. In this node, the signal electron packets are transferred under a uniquely designed p-channel MOS transistor where they modulate the transistor threshold voltage. The threshold voltage changes are then detected; they represent the desired output signal. After sensing is completed, charge is removed from the node by applying a reset pulse. One of the key advantages of the BCD charge detection concept is that charge is sensed nondestructively. The nondestructive readout does not generate reset noise, eliminating the need for the CDS post processing. Other advantages are high speed and low noise. Emitter-follower output buffering is recommended for the TI image sensors. TI also recommends that the emitter-follower be ac coupled to the rest of the signal processing chain. ac coupling eliminates problems with the sensor output dc stability and the sensor-to-sensor dc output level variations.

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the nonuniformity is specified as a percentage of the total amplitude, as shown in Figure 7. Figure 6. Pixel Nonuniformity, Figure 7. Pixel Nonuniformity,

1036- × 1010-PIXEL CCD IMAGE SENSOR SOCS058D – JUNE 1996 – REVISED MARCH 2003 9POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Substrate at ground recommended operating conditions MIN NOM MAX UNIT ADB, CDB 11 12 13 Supply voltage, VCC Vsource 12 V Vgate 0 Image area clearing Vclear 15 15.5 16 Supply voltage for ODB Antiblooming control Vabc 5 5.5 6 V Parallel transfer Vxfer 4 4.5 5 Supply current ADB 3.5 5 mA Substrate bias voltage 0 V Image area gate IAG High 1.5 2 2.5 Image area gate, IAG Low –10.5 –10 –9.5 Storage area gate SAG High 1.5 2 2.5 Storage area gate, SAG Low –10.5 –10 –9.5 Clock voltage Serial register gate SRG High 1.5 2 2.5 VClock voltage Serial register gate, SRG Low –10.5 –10 –9.5 V Transfer gate TRG High 1.5 2 2.5 Transfer gate, TRG Low –10.5 –10 –9.5 Reset gate RST High 5 5 8 Reset gate, RST Low 0 0 0.5 IAG, SAG 5 10 Clock frequency, fclock SRG RST 40 MHz TRG 5 10

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electrical characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER MIN TYP MAX UNIT Dynamic range (see Note 2) 62 dB Charge-conversion factor 10 µV/e Charge-transfer efficiency (see Note 3) 0.99990 0.99995 1 Signal-response delay time, Tau (see Note 4) 7 ns Output resistance 310 400 Ω Noise-equivalent signal 12 25 electrons Supply current (see Note 5) IDD 3.5 5 mA IAG 14500 SAG 14500 Capacitance SRG 52 pF TRG 50 RST 5.5 † All typical values are used at TA = 25°C. NOTES: 2. Dynamic range is –20 times the logarithm of the mean-noise signal divided by the saturation-output signal. 3. Charge-transfer efficiency is one minus the charge loss per transfer in the output register. The test is performed in the dark using an electrical input signal. 4. Signal-response delay time is the time between the falling edge of the SRG pulse and the output-signal valid state. 5. VADC at 12 V and VSUBSTRATE at ground. optical characteristics PARAMETER MIN TYP MAX UNIT Sensitivity (see Note 6) No IR filter 240 mV/luxSensitivity (see Note 6) With IR filter 30 mV/lux Saturation signal, Vsat (see Note 7) Antiblooming disabled 320 mV Maximum usable signal, VUSE Antiblooming disabled 120 mV Blooming overload ratio (see Note 8) 300 1000 Image-area well capacity 32K electrons Smear at 5 MHz (see Notes 9 and 10) 0.06% Dark current TA = 21°C 0.3 nA/cm2 Electronic-shutter capability 1/1000 1/30 Saturation sec NOTES: 6. Based on 16.67 ms integration time. 7. Saturation is the condition in which further increases in exposure do not lead to further increase in output signal. 8. Blooming-overload ratio is the ratio of blooming exposure to saturation exposure. 9. Smear is a measure of the error introduced by transferring charge through an illuminated pixel in shutterless operation. It is equivalent to the ratio of the single-pixel transfer time to the exposure time using an illuminated section that is 1/10 of the image-area vertical height with recommended clock frequencies. 10. The exposure time is 16.67 ms, the fast dump clocking rate during vertical timing is 10 MHz, and the illuminated section is 1/10 of the height of the image section.

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Figure 10. Typical Spectral Quantum Efficiency

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APPLICATION INFORMATION

NOTES: A. TI recommends designing ac-coupled systems. B. Inputs from user-defined timer C. Decoupling capacitors are not shown. SUB ODB IAG SUB SAG SAG SUB OUT ADB CDB VGATE SUB TDB IAG SUB SUB SUB NC SRG TRG VSOURCE RST AB_IN CLR_IN IAG_IN SAG_IN SRG_IN TRG_IN ODB Discrete ODB Driver IAG SAG Discrete Driver RST_IN SRG TRG RST VDD VDD Discrete Serial Driver AB CLR IAG SAG SRG TRG RST ccd ANALOG OUT (AC Coupled) 3Q1 NPN 100 1 kΩ 100 kΩ Figure 11. Typical Application Circuit Table 1. Supply Voltages for Application Circuits

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NOTES: A. MOSFET driver with a 4-A peak current and a 2-Ω output resistance (see Figure 14). B. Image area clear (CLR) is active high while the parallel transfer (AB) is active low. These two pulses generate the timing for ODB, as shown in Figure 1. C. Decoupling capacitors are not shown. IN NC P-OUT 4-A Peak FET Driver CLR –V –V N-OUT 0.22 µF 0.22 µF IN NC P-OUT 4-A Peak FET Driver AB –V –V N-OUT 0.22 µF 0.022 µF 200 K Ω 1 kΩ 3.83 kΩ 3.24 kΩ ODB VDD VDD VDD Figure 12. Typical ODB Driver Circuit

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NOTES: A. MOSFET driver with a 4-A peak current and a 2-Ω output resistance (see Figure 13). B. Decoupling capacitors are not shown. IN NC P-OUT 4-A Peak FET Driver –V –V N-OUT VCC R17 806 Ω R18 1 kΩ PNP IAG IAG_IN VAA IN NC P-OUT 4-A Peak FET Driver –V –V N-OUT VCC R19 806 Ω R20 1 kΩ PNP SAG SAG_IN VAA Figure 15. Typical Parallel Driver Circuit

1036- × 1010-PIXEL CCD IMAGE SENSOR SOCS058D – JUNE 1996 – REVISED MARCH 2003 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA The package for the TC281 consists of a ceramic base, a glass window, and a 22-lead frame. The package leads are configured in a dual in-line organization and fit into mounting holes with 2,54 mm (0.10 in) center-to-center spacing. The glass window is sealed to the package by an epoxy adhesive. It can be cleaned by any standard procedure for cleaning optical assemblies or by wiping the surface with a cotton swab moistened with alcohol. Optical Center Index Dot Pin 1 Package Center Ô Ô Ó Ó Ó Ó ÔÔ ÔÔ ÔÔ ÔÔ Ó Ó Ó 17.90 17.40 9.51 9.21 28.22 27.66 25.13 24.87 16.60 16.40 1.00 0.90 0.508 2.10 1.70 1.12 0.92 3.22 2.62 18.03 17.53 0.30 0.20 0.76 0.16 5.10 3.50 0.56 0.46 2.67 2.41 Package Center 0.08 ±0.08 TC281 (22 pin) 0.67 NOTES: A. All linear dimensions are in millimeters. B. Single dimensions are nominal. C. The center of the package and the center of the image area are not coincident. D. Each pin centerline is located within 0,25 mm (0.010 in) of its true longitudinal position.

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