TC241PKG

TC241 TI | Alldatasheet

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780- × 488-PIXEL CCD IMAGE SENSOR SOCS006C – AUGUST 1986 – REVISED DECEMBER 1991 Copyright  1991, Texas Instruments Incorporated 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• High-Resolution, Solid-State Image Sensor for NTSC B/W TV Applications
• 11-mm Image-Area Diagonal, Compatible With 2/3” Vidicon Optics
• 754 (H) x 244 (V) Active Elements in Image-Sensing Area
• Low Dark Current
• Electron-Hole Recombination Antiblooming
• Dynamic Range . . . More Than 60 dB
• High Sensitivity
• High Photoresponse Uniformity
• High Blue Response
• Single-Phase Clocking
• Solid-State Reliability With No Image Burn-in, Residual Imaging, Image Distortion, Image Lag, or Microphonics

description

The TC241 is a frame-transfer charge-coupled device (CCD) image sensor designed for use in single-chip B/W NTSC TV applications. The device is intended to replace a 2/3-inch vidicon tube in applications requiring small size, high reliability, and low cost. The image-sensing area of the TC241 is configured into 244 lines with 780 elements in each line. Twenty-four elements are provided in each line for dark reference. The blooming-protection feature of the sensor is based on recombining excess charge with charge of opposite polarity in the substrate. This antiblooming is activated by supplying clocking pulses to the antiblooming gate, which is an integral part of each image- sensing element. The sensor is designed to operate in an interlace mode, electronically displacing the image-sensing elements by one-half of a vertical line during the charge integration period in alternate fields, effectively increasing the vertical resolution and minimizing aliasing. The device can also be run as a 754 (H) by 244 (V) noninterlaced sensor with significant reduction in the dark signal. A gated floating-diffusion detection structure with an automatic reset and voltage reference incorporated on-chip converts charge to signal voltage. A low-noise, two-stage, source-follower amplifier buffers the output and provides high output-drive capability. The TC241 is built using TI-proprietary virtual-phase technology, which provides devices with high blue response, low dark current, high photoresponse uniformity, and single-phase clocking. The TC241 is characterized for operation from –10°C to 45°C. This MOS device contains limited built-in gate protection. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to SUB. Under no circumstances should pin voltages exceed absolute maximum ratings. Avoid shorting OUTn to ADB during operation to prevent damage to the amplifier. The device can also be damaged if the output terminals are reverse-biased and an excessive current is allowed to flow. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. SUB GND AMP GND OUT1 OUT2 OUT3 ADB TDB SAG IAG SUB SUB CDB IDB TRG SRG1 SRG2 SRG3 SAG IAG ABG SUB 1211 DUAL-IN-LINE PACKAGE (TOP VIEW) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

780- × 488-PIXEL CCD IMAGE SENSOR SOCS006C – AUGUST 1986 – REVISED DECEMBER 1991

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Gates and Serial Registers Multiplexer, Transfer Storage Area Blooming Protection Image Area With Top Drain

6 Dummy

780- × 488-PIXEL CCD IMAGE SENSOR SOCS006C – AUGUST 1986 – REVISED DECEMBER 1991 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 sensor topology diagram Area Image-Storage Area Image-Sensing 488 244 251 251 251 One 1/2-Amplitude Element Columns I/O DESCRIPTIONNAME NO. I/O DESCRIPTION ABG 21 I Antiblooming gate ADB 5 I Supply voltage for amplifier-drain bias AMP GND 9 Amplifier ground CDB 13 I Supply voltage for clearing-drain bias GND 10 Ground IAG† 2 I Image-area gate IAG† 20 I Image-area gate IDB 14 I Supply voltage for input diode bias OUT1 8 O Output signal 1 OUT2 7 O Output signal 2 OUT3 6 O Output signal 3 SAG † 3 I Storage-area gate SAG † 19 I Storage-area gate SRG1 16 I Serial-register gate 1 SRG2 17 I Serial-register gate 2 SRG3 18 I Serial-register gate 3 SUB † 1 Substrate and clock return SUB † 11 Substrate and clock return SUB † 12 Substrate and clock return SUB † 22 Substrate and clock return TDB 4 I Supply voltage for top-drain bias TRG 15 I Transfer gate † All pins of the same name should be connected together externally.

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nodes. The location of each of these blocks is shown in the functional block diagram. operation or under special circumstances when nonstandard TV operation is desired. are used to span this distance. The location of the dummy elements is shown in the functional block diagram. Figure 1. Charge-Accumulation Process

Figure 2. Charge-Transfer Process

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Figure 3. Timing Diagram

Figure 4. Buffer Amplifier and Charge-Detection Node

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• Amplitude of the nonuniform pixel
• Polarity of the nonuniform pixel – Black – White
• Location of the nonuniformity (see Figure 5) – Area A – Element columns near horizontal center of the area – Element rows near vertical center of the area – Area B – Up to the pixel or line border – Up to area A – Other – Edge of the imager – Up to area B
• Nonuniform pixel count
• Distance between nonuniform pixels
• Column amplitude The CCD sensors are characterized in both an illuminated condition and a dark condition. In the dark condition, the nonuniformity is specified in terms of absolute amplitude as shown in Figure 6. In the illuminated condition, the nonuniformity is specified as a percentage of the total illumination as shown in Figure 7. BA

20 Pixels

15 Pixels

Figure 5. Sensor-Area Map

Figure 6. Pixel-Nonuniformity, Figure 7. Pixel-Nonuniformity, pixels in the illuminated condition. The sum of all nonuniform combinations do not exceed the total count.

780- × 488-PIXEL CCD IMAGE SENSOR SOCS006C – AUGUST 1986 – REVISED DECEMBER 1991

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to the substrate terminal. recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC ADB, CDB, IDB, TDB 11 12 13 V Substrate bias voltage 0 V High level 1.5 2 2.5 IAG Intermediate level§ –5 Low level –10 –9 –8 SRG1 SRG2 SRG3 High level 1.5 2 2.5 SRG1 , SRG2 , SRG3 Low level –10 –9 –8 Input voltage V‡ High level 2 4 6 VInput voltage, VI‡ ABG Intermediate level§ –2.5 V Low level –7 SAG High level 1.5 2 2.5 SAG Low level –10 –9 –8 TRG High level 1.5 2 2.5 TRG Low level –10 –9 –8 IAG, SAG 2.05 Clock frequency, fclock SRG1, SRG2, SRG3, TRG 4.77 MHz ABG 2.05 Load capacitance OUT1, OUT2, OUT3 8 pF Operating free-air temperature, TA –10 45 °C ‡ The algebraic convention, in which the least-positive (most negative) value is designated minimum, is used in this data sheet for clock voltage levels. § Adjustment is required for optimal performance.

780- × 488-PIXEL CCD IMAGE SENSOR SOCS006C – AUGUST 1986 – REVISED DECEMBER 1991 11POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 electrical characteristics over recommended operating ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER MIN TYP † MAX UNIT Dynamic range (see Note 2) Antiblooming disabled (see Note 3) 60 dB Charge-conversion factor 1.4 1.6 1.8 µV/e Charge-transfer efficiency (see Note 4) 0.9999 0.99995 Signal-response delay time, τ (see Note 5 and Figure 11) 18 20 22 ns Gamma (see Note 6) 0.97 0.98 Output resistance 700 800 Ω Noise voltage 1/f noise (5 kHz) 0.13 µV/√HzNoise voltage Random noise (f = 100 kHz) 0.11 µV/√H z Noise-equivalent signal 120 electrons ADB (see Note 7) 20 Rejection ratio at 4.77 MHz SRG1, SRG2, SRG3 (see Note 8) 40 dB ABG (see Note 9) 20 Supply current 5 mA IAG 12000 SRG1, SRG2, SRG3 120 Input capacitance, Ci ABG 4000 pF TRG 350 SAG 14000 † All typical values are at TA = 25 °C NOTES: 2. Dynamic range is –20 times the logarithm of the mean-noise signal divided by the saturation-output signal. 3. For this test, the antiblooming gate must be biased at the intermediate level. 4. Charge-transfer efficiency is one minus the charge loss per transfer in the output register. The test is performed in the dark using an electrical input signal. 5. Signal-response delay time is the time between the falling edge of the SRG clock pulse and the output-signal valid state. 6. Gamma ( γ) is the value of the exponent in the equation below for two points on the linear portion of the transfer-function curve (this value represents points near saturation): /C0466Exposure (2) Exposure (1)/C0467 /C0103 /C0043/C0466Output signal (2) Output signal (1)/C0467 7. ADB rejection ratio is –20 times the logarithm of the ac amplitude at the output divided by the ac amplitude at ADB. 8. SRGn rejection ratio is –20 times the logarithm of the ac amplitude at the output divided by the ac amplitude at SRGn. 9. ABG rejection ratio is –20 times the logarithm of the ac amplitude at the output divided by the ac amplitude at ABG.

780- × 488-PIXEL CCD IMAGE SENSOR SOCS006C – AUGUST 1986 – REVISED DECEMBER 1991

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optical characteristics, TA = 40°C (unless otherwise noted) PARAMETER MIN TYP MAX UNIT Sensitivity No IR filter Measured at VU 150 mV/lxSensitivity With IR filter U (see Notes 10 and 11) 19 mV/lx Saturation signal, Vsat (see Note 12)Antiblooming disabled, interlace off 320 400 mV Maximum usable signal, Vuse Antiblooming enabled, interlace on 180 360 mV Blooming overload ratio (see Note 13) Interlace on 100 Blooming-overload ratio (see Note 13) Interlace off 200 Image-area well capacity 200 x 103 electrons Smear (see Note 14) See Note 15 0.00072 Dark current Interlace off TA = 21°C 0.027 nA/cm2 Dark signal (see Note 16) TC241-30 15 mVDark signal (see Note 16) TC241-40 20 mV Pixel uniformity Output signal = 50 mV±10 mV TC241-30 3.5 mVPixel uniformity O utput signal = 50 mV ±10 mV TC241-40 5 mV Column uniformity Output signal = 50 mV±10 mV TC241-30 0.5 mVColumn uniformity O utput signal = 50 mV ±10 mV TC241-40 0.7 mV Shading Output signal = 100 mV 15% NOTES: 10. Sensitivity is measured at an integration time of 16.667 ms with a source temperature of 2856 K. A CM-500 filter is used. 11. VU is the output voltage that represents the threshold of operation of antiblooming. VU ≈ 1/2 saturation signal. 12. Saturation is the condition in which further increase in exposure does not lead to further increase in output signal. 13. Blooming-overload ratio is the ratio of blooming exposure to saturation exposure. 14. Smear is a measure of the error induced by transferring charge through an illuminated pixel in shutterless operation. It is equivalent to the ratio of the single-pixel transfer time during a fast dump to the exposure time using an illuminated section that is 1/10 of the image-area vertical height with recommended clock frequencies. 15. Exposure time is 16.67 ms and the fast-dump clocking rate during vertical timing is 2.05 MHz. 16. Dark-signal level is measured from the dummy pixels.

Figure 8. Typical Vsat, Vuse Relationship

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Figure 9. Typical Clock Waveform for ABG, IAG, and SAG Figure 10. Typical Clock Waveform for SRG1, SRG2, SRG3, and TRG Figure 11. SRG and CCD Output Waveforms

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APPLICATION INFORMATION

4.7 µF 100 Ω OUT1 OUT2 OUT3 GT3 GT1 GT2 15 pF 14.3-MHz Oscillator 20 pF 4443424140393837363534 VCC 1213141516171819202122 L ADB VABG– ABLVL VABG+V TMS3473B IALVL VSS 47 kΩ 47 kΩ 100 Ω 100 Ω 100 Ω 4.7 µF 4.7 µF 4.7 µF 100 Ω 100 Ω 100 Ω SC (90) SC BF CBLK CSYNC CP1 CP2 BCP2 CP2 47 kΩ 47 kΩ 100 pF 1112 1 kΩ SH2, 3 SH1 1 kΩ SH2, 3 SH1 VCC 4.7 kΩ VCC ABS2 ABS1 ABS0 ADB VCC VSS V ABLVL IALVL VABG+ VABG– 12 V 5 V –10 V 2 V –2.5 V –5 V 4 V –6 V DC VOLTAGES VSS VAGB+ GND PD SAIN MIDSEL ABIN IAIN I IALVL VAGB– VCC SAOUT ABOUT IAOUT ABLVL VCC ABSR IASR VSS DLADJ GND PD SRG2,3IN SRG1IN TRGIN 2,3PC1 2,3PC2 SSR

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SH2, 3 SH1 GND T S2, 3 GT1 GT2 GT3 BCPS0 BCPS1 VDS E/L FI BCP1 SUPPORT CIRCUITS DEVICE PACKAGE APPLICATION FUNCTION TMS3471CFS 44 pin flatpack Timing generator NTSC timing generator TMS3472ADW 20 pin flatpack with tabs Serial driver Driver for SRG1, SRG2, SRG3, and TRG TMS3473BDW 20 pin small outline Parallel driver Driver for ABG, IAG, and SAG TL1593CNS 16 pin small outline (EIAJ) Sample and hold Three-channel sample-and-hold IC Figure 16. Typical Application Circuit Diagram † Decoupling capacitors are not shown. ‡ TI recommends designing AC coupled systems.

780- × 488-PIXEL CCD IMAGE SENSOR SOCS006C – AUGUST 1986 – REVISED DECEMBER 1991 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA The package for the TC241 consists of a ceramic base, a glass window, and a 22-lead frame. The glass window is sealed to the package by an epoxy adhesive. The package leads are configured in a dual in-line organization and fit into mounting holes with 2.54 mm (0.10 in) center-to-center spacings. (0.217 ± 0.030) 5,50 ± 0,76 3,86 (0.152) MAX Optical Center 27,81 (1.095) MAX 8,00 (0.315) 23,39 (0.921) 0,25 (0.010) 10,16 (0.400) TYP 2,79 (0.110) MAX(0.730) 18,54 2,01 (0.079) Index Dot 9,35 (0.368) REF 0,46 (0.018) 2,54 (0.100) (see Note D) 18,24 (0.718) 2,01 x 2,39 (0.079 x 0.094) ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES CL TC241 (22 pin) Optical (see Note B) NOTES: A. Single dimensions are nominal. B. The center of the package and the center of the image area are not coincident. C. The distance from the top of the glass to the image-sensor surface is typically 1,46 mm (0.057 in). The glass is 0,95 ±0,08 mm thick and has an index of refraction of 1.53. D. Each pin centerline is located within 0,25 mm (0.010 in) of its true longitudinal position.

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