TC1302A MICROCHIP | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 26

Technical content

Features

  • Dual Output LDO: - VOUT1 = 1.5V to 3.3V @ 300 mA - VOUT2 = 1.5V to 3.3V @ 150 mA
  • Output Voltage (See Table 8-1)
  • Low Dropout Voltage: - VOUT1 = 104 mV @ 300 mA Typical - VOUT2 = 150 mV @ 150 mA Typical
  • Low Supply Current: 116 µA Typical TC1302A/B with both output voltages available
  • Reference Bypass Input for Low-Noise Operation
  • Both Output Voltages Stable with a Minimum of 1 µF Ceramic Output Capacitor
  • Separate VOUT1 and VOUT2 SHDN pins (TC1302B)
  • Power-Saving Shutdown Mode of Operation
  • Wake-up from SHDN: 5.3 µs. Typical
  • Small 8-pin DFN or MSOP Package Options
  • Operating Junction Temperature Range: - -40°C to +125°C
  • Overtemperature and Overcurrent Protection

Applications

  • Cellular/GSM/PHS Phones
  • Battery-Operated Systems
  • Hand-Held Medical Instruments
  • Portable Computers/PDAs
  • Linear Post-Regulators for SMPS
  • Pagers Related Literature
  • AN765, “Using Microchip’s Micropower LDOs”, DS00765, Microchip Technology Inc., 2002
  • AN766, “Pin-Compatible CMOS Upgrades to BiPolar LDOs”, DS00766, Microchip Technology Inc., 2002
  • AN792, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Application”, DS00792, Microchip Technology Inc., 2001

Description

The TC1302A/B combines two Low Dropout (LDO) regulators into a single 8-pin MSOP or DFN package. Both regulator outputs feature low dropout voltage, 104 mV @ 300 mA for VOUT1, 150 mV @ 150 mA for VOUT2, low quiescent current consumption, 58 µA each and a typical regulation accuracy of 0.5%. Several fixed-output voltage combinations are available. A reference bypass pin is available to further reduce output noise and improve the power supply rejection ratio of both LDOs. The TC1302A/B is stable over all line and load conditions, with a minimum of 1 µF of ceramic output capacitance, and utilizes a unique compensation scheme to provide fast dynamic response to sudden line voltage and load current changes. Additional features include an overcurrent limit and overtemperature protection that combine to provide a robust design for all load fault conditions. Package Types 8-Pin DFN/MSOP NC SHDN2 Bypass GND NC VOUT2 VIN VOUT1 TC1302A NC SHDN2 Bypass GND NC VOUT2 VIN VOUT1 DFN8 MSOP8 NC SHDN2 Bypass GND SHDN1 VOUT2 VIN VOUT1 TC1302B NC SHDN2 Bypass GND SHDN1 VOUT2 VIN VOUT1 DFN8 MSOP8 Low Quiescent Current Dual Output LDO

© 2005 Microchip Technology Inc. Functional Block Diagrams Typical Application Circuits LDO #2 150 mA LDO #1 300 mA LDO #2 150 mA VIN VOUT1 VOUT2 Bandgap Reference SHDN2 GND Bypass TC1302A TC1302B VIN SHDN2 GND Bypass SHDN1 LDO #1 300 mA Bandgap Reference VOUT1 VOUT2 1.2V 1.2V NC GND NC BATTERY COUT1 1 µF Ceramic X5R CIN 1 µF TC1302A COUT2 1 µF Ceramic X5R CBYPASS (Note) 10 nF Ceramic Bypass VIN 7 2.7V to 4.2V VOUT2 6 SHDN2 ON/OFF Control VOUT2 2.8V @ 300 mA 2.6V @ 150 mA VOUT1 NC GND SHDN1 BATTERY COUT1 1 µF Ceramic X5R CIN 1 µF TC1302B COUT2 1 µF Ceramic X5R Bypass VIN 7 2.7V to 4.2V VOUT2 6 SHDN2 ON/OFF Control VOUT2 2.8V @ 300 mA 2.6V @ 150 mA ON/OFF Control VOUT1 Note: CBYPASS is optional VOUT1

© 2005 Microchip Technology Inc. DS21333B-page 3 TC1302A/B 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Continuous Operating Temperature Range ..-40°C to +125°C † Notice: Stresses above those listed under “Maximum Rat- ings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Expo- sure to maximum rating conditions for extended periods may affect device reliability. DC CHARACTERISTICS COUT1 = COUT2 = 1 µF, CBYPASS = 10 nF, SHDN > VIH, TA = +25°C. Boldface type specifications apply for junction temperatures of -40°C to +125°C. Parameters Sym Min Typ Max Units Conditions Input Operating Voltage VIN 2.7 6.0 V Note 1 Maximum Output Current IOUT1Max 300 mA VIN = 2.7V to 6.0V (Note 1) Maximum Output Current IOUT2Max 150 mA VIN = 2.7V to 6.0V (Note 1) Output Voltage Tolerance (VOUT1 and VOUT2) VOUT VR – 2.5 VR±0.5 VR + 2.5 Note 2 Temperature Coefficient (VOUT1 and VOUT2) TCVOUT ppm/°C Note 3 Line Regulation (VOUT1 and VOUT2) ΔVOUT/ΔVIN 0.02 0.2 %/V (VR + 1V) ≤ VIN ≤ 6V Load Regulation, VOUT ≥ 2.5V (VOUT1 and VOUT2) ΔVOUT/ VOUT 0.1 IOUTX = 0.1 mA to IOUTMax, (Note 4) Load Regulation, VOUT < 2.5V (VOUT1 and VOUT2) ΔVOUT/ VOUT -1.5 0.1 +1.5 IOUTX = 0.1 mA to IOUTMax, (Note 4) Thermal Regulation ΔVOUT/ΔPD 0.04 %/W Note 5 Dropout Voltage (Note 6) VOUT1 > 2.7V VIN – VOUT 104 180 mV IOUT1 = 300 mA VOUT2 > 2.6V VIN – VOUT 150 250 mV IOUT2 = 150 mA Supply Current TC1302A IIN(A) 103 180 µA SHDN2 = VIN, IOUT1 = IOUT2 = 0 mA TC1302B IIN(B) 114 180 µA SHDN1 = SHDN2 = VIN, IOUT1 = IOUT2 = 0 mA Note The minimum VIN has to meet two conditions: VIN ≥ 2.7V and VIN ≥ VR + VDROPOUT. VR is defined as the higher of the two regulator nominal output voltages (VOUT1 or VOUT2). TCVOUT = ((VOUTmax - VOUTmin) * 106)/(VOUT * ΔT). Regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 0.1 mA to the maximum specified output current. Changes in output voltage due to heating effects are covered by the thermal regulation specification. Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied, excluding load or line regulation effects. Specifications are for a current pulse equal to ILMAX at VIN = 6V for t = 10 msec. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its value measured at a 1V differential. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, θJA). Exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown.

© 2005 Microchip Technology Inc. TEMPERATURE SPECIFICATIONS Shutdown Supply Current TC1302A IIN_SHDNA µA SHDN2 = GND Shutdown Supply Current TC1302B IIN_SHDNB 0.1 µA SHDN1 = SHDN2 = GND Power Supply Rejection Ratio PSRR dB f ≤ 100 Hz, IOUT1 = IOUT2 = 50 mA, CIN = 0 µF Output Noise eN 830 nV/(Hz)½ f ≤ 1 kHz, IOUT1 = IOUT2 = 50 mA, CIN = 0 µF Output Short Circuit Current (Average) VOUT1 IOUTsc1 200 mA RLOAD1 ≤ 1Ω VOUT2 IOUTsc2 140 mA RLOAD2 ≤ 1Ω SHDN Input High Threshold VIH %VIN VIN = 2.7V to 6.0V SHDN Input Low Threshold VIL %VIN VIN = 2.7V to 6.0V Wake Up Time (From SHDN mode), (VOUT2) tWK 5.3 µs VIN = 5V, IOUT1 = IOUT2 = 30 mA, See Figure 5-1 Settling Time (From SHDN mode), (VOUT2) tS µs VIN = 5V, IOUT1 = IOUT2 = 50 mA, See Figure 5-2 Thermal Shutdown Die Temperature TSD 150 VIN = 5V, IOUT1 = IOUT2 = 100 µA Thermal Shutdown Hysteresis THYS VIN = 5V Electrical Specifications: Unless otherwise indicated, all limits are specified for: VIN = +2.7V to +6.0V. Parameters Sym Min Typ Max Units Conditions Temperature Ranges Operating Junction Temperature Range TA -40 +125 Steady State Storage Temperature Range TA -65 +150 Maximum Junction Temperature TJ +150 Transient Thermal Package Resistances Thermal Resistance, MSOP8 θJA 208 °C/W Typical 4-Layer Board Thermal Resistance, DFN8 θJA °C/W Typical 4-Layer Board with Vias DC CHARACTERISTICS (Continued) COUT1 = COUT2 = 1 µF, CBYPASS = 10 nF, SHDN > VIH, TA = +25°C. Boldface type specifications apply for junction temperatures of -40°C to +125°C. Parameters Sym Min Typ Max Units Conditions Note The minimum VIN has to meet two conditions: VIN ≥ 2.7V and VIN ≥ VR + VDROPOUT. VR is defined as the higher of the two regulator nominal output voltages (VOUT1 or VOUT2). TCVOUT = ((VOUTmax - VOUTmin) * 106)/(VOUT * ΔT). Regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 0.1 mA to the maximum specified output current. Changes in output voltage due to heating effects are covered by the thermal regulation specification. Thermal regulation is defined as the change in output voltage at a time t after a change in power dissipation is applied, excluding load or line regulation effects. Specifications are for a current pulse equal to ILMAX at VIN = 6V for t = 10 msec. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its value measured at a 1V differential. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, θJA). Exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown.

© 2005 Microchip Technology Inc. DS21333B-page 9 TC1302A/B Note: Unless otherwise indicated, VIN = VR +1V, IOUT1 = IOUT2 = 100 µA, CIN = 4.7 µF, COUT1 = COUT2 = 1 µF (X5R or X7R), CBYPASS = 0 pF, SHDN1 = SHDN2 > VIH, TA = +25°C. FIGURE 2-25: 150 mA Dynamic Load Step VOUT2.

© 2005 Microchip Technology Inc. 3.0 TC1302A PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: TC1302A PIN FUNCTION TABLE 3.1 Regulated Output Voltage #1 (VOUT1) Connect VOUT1 to the positive side of the VOUT1 capacitor and load. Capable of 300 mA maximum output current. VOUT1 output is available when VIN is available; there is no pin to turn it OFF. See TC1302B if ON/OFF control of VOUT1 is desired. 3.2 Circuit Ground Pin (GND) Connect GND to the negative side of the input and output capacitor. Only the LDO internal circuitry bias current flows out of this pin (200 µA maximum). 3.3 Reference Bypass Input By connecting an external 10 nF capacitor (typical) to the Bypass Input, both outputs (VOUT1 and VOUT2) will have less noise and improved Power Supply Ripple Rejection (PSRR) performance. The LDO output voltage start-up time will increase with the addition of an external bypass capacitor. By leaving this pin unconnected, the start-up time will be minimized. 3.4 Output Voltage #2 Shutdown (SHDN2) ON/OFF control is performed by connecting SHDN2 to its proper level. When the input of this pin is connected to a voltage less than 15% of VIN, VOUT2 will be OFF. If this pin is connected to a voltage that is greater than 45% of VIN, VOUT2 will be turned ON. 3.5 Regulated Output Voltage #2 (VOUT2) Connect VOUT2 to the positive side of the VOUT2 capacitor and load. This pin is capable of a maximum output current of 150 mA. VOUT2 can be turned ON and OFF using SHDN2. 3.6 Unregulated Input Voltage Pin (VIN) Connect the unregulated input voltage source to VIN. If the input voltage source is located more than several inches away or is a battery, a typical input capacitance of 1 µF to 4.7 µF is recommended. Pin No. Name Function NC No connect. VOUT1 Regulated output voltage #1, capable of 300 mA. GND Circuit ground pin. Bypass Internal reference bypass pin. A 10 nF external capacitor can be used to further reduce output noise and improve PSRR performance. SHDN2 Output #2 shutdown control input. VOUT2 Regulated output voltage #2, capable of 150 mA. VIN Unregulated input voltage pin. NC No connect.

© 2005 Microchip Technology Inc. DS21333B-page 11 TC1302A/B 4.0 TC1302B PIN DESCRIPTIONS The descriptions of the pins are listed in Table 4-1. TABLE 4-1: TC1302B PIN FUNCTION TABLE 4.1 Regulated Output Voltage #1 (VOUT1) Connect VOUT1 to the positive side of the VOUT1 capacitor and load. Capable of 300 mA maximum output current. For the TC1302B, VOUT1 can be turned ON and OFF using the SHDN1 input pin. 4.2 Circuit Ground Pin (GND) Connect GND to the negative side of the input and output capacitor. Only the LDO internal circuitry bias current flows out of this pin (200 µA maximum). 4.3 Reference Bypass Input By connecting an external 10 nF capacitor (typical) to the bypass input, both outputs (VOUT1 and VOUT2) will have less noise and improved Power Supply Ripple Rejection (PSRR) performance. The LDO output voltage startup time will increase with the addition of an external bypass capacitor. By leaving this pin unconnected, the startup time will be minimized. 4.4 Output Voltage #2 Shutdown (SHDN2) ON/OFF control is performed by connecting SHDN2 to its proper level. When this pin is connected to a voltage less than 15% of VIN, VOUT2 will be OFF. If this pin is connected to a voltage that is greater than 45% of VIN, VOUT2 will be turned ON. 4.5 Regulated Output Voltage #2 (VOUT2) Connect VOUT2 to the positive side of the VOUT2 capacitor and load. This pin is capable of a maximum output current of 150 mA. VOUT2 can be turned ON and OFF using SHDN2. 4.6 Unregulated Input Voltage Pin (VIN) Connect the unregulated input voltage source to VIN. If the input voltage source is located more than several inches away, or is a battery, a typical minimum input capacitance of 1 µF and 4.7 µF is recommended. 4.7 Output Voltage #1 Shutdown (SHDN1) ON/OFF control is performed by connecting SNDN1 to its proper level. When this pin is connected to a voltage less than 15% of VIN, VOUT1 will be OFF. If this pin is connected to a voltage that is greater than 45% of VIN, VOUT1 will be turned ON. Pin No. Name Function NC No connect. VOUT1 Regulated output voltage #1, capable of 300 mA. GND Circuit ground pin. Bypass Internal reference bypass pin. A 10 nF external capacitor can be used to further reduce output noise and improve PSRR performance. SHDN2 Output #2 shutdown control input. VOUT2 Regulated output voltage #2, capable of 150 mA. VIN Unregulated Input voltage pin. SHDN1 Output #1 shutdown control input.

© 2005 Microchip Technology Inc. 5.0 DETAILED DESCRIPTION 5.1 Device Overview The TC1302A/B is a combination device consisting of one 300 mA LDO regulator with a fixed output voltage VOUT1 (1.5V – 3.3V) and one 150 mA LDO regulator with a fixed output voltage VOUT2 (1.5V – 3.3V). For the TC1302A, the 300 mA output (VOUT1) is always present, independent of the level of SHDN2. The 150 mA output (VOUT2) can be turned ON/OFF by controlling the level of SHDN2. For the TC1302B, VOUT1 and VOUT2 each have independent shutdown input pins (SHDN1 and SHDN2) to control their respective outputs. 5.2 LDO Output #1 LDO output #1 is rated for 300 mA of output current. The typical dropout voltage for VOUT1 = 104 mV @ 300 mA. A 1 µF (minimum) output capacitor is needed for stability and should be located as close to the VOUT1 pin and ground as possible. 5.3 LDO Output #2 LDO output #2 is rated for 150 mA of output current. The typical dropout voltage for VOUT2 = 150 mV. A 1 µF (minimum) capacitor is needed for stability and should be located as close to the VOUT2 pin and ground as possible. 5.4 Input Capacitor Low input source impedance is necessary for the two LDO outputs to operate properly. When operating from batteries, or in applications with long lead length (> 10 inches) between the input source and the LDO, some input capacitance is recommended. A minimum of 1.0 µF to 4.7 µF is recommended for most applications. When using large capacitors on the LDO outputs, larger capacitance is recommended on the LDO input. The capacitor should be placed as close to the input of the LDO as is practical. Larger input capacitors will help reduce the input impedance and further reduce any high-frequency noise on the input and output of the LDO. 5.5 Output Capacitor A minimum output capacitance of 1 µF for each of the TC1302A/B LDO outputs is necessary for stability. Ceramic capacitors are recommended because of their size, cost and environmental robustness qualities. Tantalum or aluminum electrolytic capacitors can be used on the LDO outputs as well. The Equivalent Series Resistance (ESR) requirements on the electrolytic output capacitor’s are between 0 and 2 ohms. The output capacitor should be located as close to the LDO output as is practical. Ceramic materials, X7R and X5R, have low temperature coefficients and are well within the acceptable ESR range required. A typical 1 uF X5R 0805 capacitor has an ESR of 50 milli- ohms. Larger LDO output capacitors can be used with the TC1302A/B to improve dynamic performance and power supply ripple rejection performance. A maximum of 10 µF is recommended. Aluminum electrolytic capacitors are not recommended for low temperature applications of < -25 °C. 5.6 Bypass Input The Bypass pin is connected to the internal LDO reference. By adding capacitance to this pin, the LDO ripple rejection, input voltage transient response and output noise performance are all increased. A typical bypass capacitor between 470 pF to 10 nF is recommended. Larger bypass capacitors can be used, but result in a longer time period for the LDO outputs to reach their rated output voltage when started from SHDN or VIN. 5.7 GND For the optimal noise and PSRR performance, the GND pin of the TC1302A/B should be tied to a quiet circuit ground. For applications that have switching or noisy inputs, tie the GND pin to the return of the output capacitor. Ground planes help lower inductance and voltage spikes caused by fast transient load currents and are recommended for applications that are subjected to fast load transients. 5.8 SHDN1/SHDN2 Operation The TC1302A SHDN2 pin is used to turn VOUT2 ON and OFF. A logic-high level on SHDN2 will enable the VOUT2 output, while a logic-low on the SHDN2 pin will disable the VOUT2 output. For the TC1302A, VOUT1 is not affected by SHDN2 and will be enabled as long as the input voltage is present. The TC1302B SHDN1 and SHDN2 pins are used to turn VOUT1 and VOUT2 ON and OFF. They operate independent of each other.

© 2005 Microchip Technology Inc. 6.0 APPLICATION CIRCUITS/ ISSUES 6.1 Typical Application The TC1302A/B is used for applications that require the integration of two LDOs. FIGURE 6-1: Typical Application Circuit TC1302A/B. 6.1.1 APPLICATION INPUT CONDITIONS 6.2 Power Calculations 6.2.1 POWER DISSIPATION The internal power dissipation within the TC1302A/B is a function of input voltage, output voltage, output current and quiescent current. The following equation can be used to calculate the internal power dissipation for each LDO. EQUATION 6-1: In addition to the LDO pass element power dissipation, there is power dissipation within the TC1302A/B as a result of quiescent or ground current. The power dissipation, as a result of the ground current, can be calculated using the following equation. EQUATION 6-2: The total power dissipated within the TC1302A/B is the sum of the power dissipated in both of the LDOs and the P(IGND) term. Because of the CMOS construction, the typical IGND for the TC1302A/B is 116 µA. Operating at a maximum of 4.2V results in a power dissipation of 0.5 milliWatts. For most applications, this is small compared to the LDO pass device power dissi- pation and can be neglected. The maximum continuous operating junction temperature specified for the TC1302A/B is +125°C. To estimate the internal junction temperature of the TC1302A/B, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (RθJA) of the device. The thermal resistance from junction-to-ambient for the 3x3DFN8 pin package is estimated at 41° C/W. EQUATION 6-3: Package Type = 3x3DFN8 Input Voltage Range = 2.7V to 4.2V VIN maximum = 4.2V VIN typical = 3.6V VOUT1 = 300 mA maximum VOUT2 = 150 mA maximum NC GND NC BATTERY COUT1 1 µF Ceramic X5R CIN 1 µF TC1302A COUT2 1 µF Ceramic X5R Cbypass 10 nF Ceramic Bypass VIN 7 2.7V to 4.2V VOUT2 6 SHDN2 ON/OFF Control VOUT2 2.8V @ 300 mA 1.8V VOUT1 NC BATTERY COUT1 1 µF Ceramic X5R CIN 1 µF TC1302B COUT2 1 µF Ceramic X5R Bypass VIN 7 2.7V to 4.2V VOUT2 6 SHDN2 ON/OFF Control VOUT2 2.8V @ 300 mA 1.8V ON/OFF Control VOUT1 VOUT1 @ 150 mA GND @ 150 mA SHDN1 PLDO VIN MAX) VOUT MIN IOUT MAX) PLDO = LDO Pass device internal power dissipation VIN(MAX) = Maximum input voltage VOUT(MIN)= LDO minimum output voltage PI GND VIN MAX IVIN PI(GND) = Total current in ground pin. VIN(MAX)= Maximum input voltage. IVIN = Current flowing in the VIN pin with no output current on either LDO output. TJ MAX PTOTAL RθJA TAMAX TJ(MAX) = Maximum continuous junction temperature. PTOTAL = Total device power dissipation. RθJA = Thermal resistance from junction to ambient. TAMAX = Maximum Ambient Temperature.

© 2005 Microchip Technology Inc. DS21333B-page 15 TC1302A/B The maximum power dissipation capability for a package can be calculated given the junction-to- ambient thermal resistance and the maximum ambient temperature for the application. The following equation can be used to determine the package maximum internal power dissipation. EQUATION 6-4: EQUATION 6-5: EQUATION 6-6: 6.3 Typical Application Internal power dissipation, junction temperature rise, junction temperature and maximum power dissipation are calculated in the following example. The power dissipation, as a result of ground current, is small enough to be neglected. 6.3.1 POWER DISSIPATION EXAMPLE Device Junction Temperature Rise The internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction to ambient for the application. The thermal resistance from junction to ambient (RθJA) is derived from an EIA/JEDEC standard for measuring thermal resistance for small surface-mount packages. The EIA/JEDEC specification is JESD51-7 “High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages”. The standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. The actual thermal resistance for a particular application can vary depending on many factors, such as copper area and thickness. Refer to AN792, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Application”, (DS00792), for more information regarding this subject. Junction Temperature Estimate To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated below. Maximum Package Power Dissipation at 50°C Ambient Temperature Package Package Type = 3x3DFN8 Input Voltage VIN = 2.7V to 4.2V LDO Output Voltages and Currents VOUT1 = 2.8V IOUT1 = 300 mA VOUT2 = 1.8V IOUT2 = 150 mA PD MAX TJ MAX TA MAX RθJA PD(MAX) = maximum device power dissipation. TJ(MAX) = maximum continuous junction temperature. TA(MAX) = maximum ambient temperature. RθJA = Thermal resistance from junction to ambient. TJ RISE PD MAX RθJA TJ(RISE) = Rise in device junction temperature over the ambient temperature. PD(MAX) = Maximum device power dissipation. RθJA = Thermal resistance from junction-to- ambient. TJ TJ RISE TA TJ = Junction temperature. TJ(RISE) = Rise in device junction temperature over the ambient temperature. TA = Ambient Temperature. Maximum Ambient Temperature TA(MAX) = 50°C Internal Power Dissipation Internal power dissipation is the sum of the power dissipation for each LDO pass device. PLDO1(MAX) = (VIN(MAX) - VOUT1(MIN)) x IOUT1(MAX) PLDO1 = (4.2V - (0.975 x 2.8V)) x 300 mA PLDO1 = 441.0 milliWatts PLDO2 = (4.2V - (0.975 X 1.8V)) x 150 mA PLDO2 = 366.8 milliWatts PTOTAL = PLDO1 + PLDO2 PTOTAL= 807.8 milliWatts TJ(RISE) = PTOTAL x RqJA TJRISE = 807.8 milliWatts x 41.0° C/W TJRISE = 33.1°C TJ = TJRISE + TA(MAX) TJ = 83.1°C 3x3DFN8 (41°C/Watt RθJA) PD(MAX) = (125°C - 50°C)/41° C/W PD(MAX) = 1.83 Watts MSOP8 (208°C/Watt RθJA) PD(MAX) = (125°C - 50°C)/208° C/W PD(MAX) = 0.360 Watts

© 2005 Microchip Technology Inc. DS21333B-page 17 TC1302A/B 9.0 PACKAGING INFORMATION 9.1 Package Marking Information X1 represents VOUT1 configuration: X2 represents VOUT2 configuration: For a listing of TC1302A/B standard parts, refer to the Product Identification System on page 23. 8-Lead MSOP XXXXXX YWWNNN Example: BFH 0542 256 Example: 32AFH 542256 8-Lead DFN XXXX YYWW NNN — 32A = TC1302A — F = 2.8V VOUT1 — H = 2.6V VOUT2 Code VOUT1 Code VOUT1 Code VOUT1 A 3.3V J 2.4V S 1.5V B 3.2V K 2.3V T 1.65V C 3.1V L 2.2V U 2.85V D 3.0V M 2.1V V 2.65V E 2.9V N 2.0V W 1.85V F 2.8V O 1.9V X G 2.7V P 1.8V Y H 2.6V Q 1.7V Z I 2.5V R 1.6V Code VOUT2 Code VOUT1 Code VOUT2 A 3.3V J 2.4V S 1.5V B 3.2V K 2.3V T 1.65V C 3.1V L 2.2V U 2.85V D 3.0V M 2.1V V 2.65V E 2.9V N 2.0V W 1.85V F 2.8V O 1.9V X G 2.7V P 1.8V Y H 2.6V Q 1.7V Z I 2.5V R 1.6V Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. e e

© 2005 Microchip Technology Inc. 8-Lead Plastic Micro Small Outline Package (UA) (MSOP) D A L c (F) α E p B n φ β Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not .037 REF F Footprint (Reference) exceed .010" (0.254mm) per side. Notes: Drawing No. C04-111 *Controlling Parameter Mold Draft Angle Top Mold Draft Angle Bottom Foot Angle Lead Width Lead Thickness β α c B φ .003 .009 .006 .012 Dimension Limits Overall Height Molded Package Thickness Molded Package Width Overall Length Foot Length Standoff Overall Width Number of Pins Pitch A L D E .016 .024 .118 BSC .118 BSC .000 .030 .193 TYP. .033 MIN p n Units .026 BSC NOM INCHES

0.95 REF

.009 .016 0.08 0.22 0.23 0.40 MILLIMETERS*

0.65 BSC

0.85

3.00 BSC

0.60

4.90 BSC

.043 .031 .037 .006 0.40 0.00 0.75 MIN MAX NOM 1.10 0.80 0.15 0.95 MAX 15° 15° JEDEC Equivalent: MO-187 15° 15°

© 2005 Microchip Technology Inc. DS21333B-page 19 TC1302A/B 8-Lead Plastic Dual Flat No Lead Package (MF) 3x3x0.9 mm Body (DFN) D Dimensions D and E do not include mold flash or protrusions. Mold flash or protrusions shall not Exposed Pad Width Exposed Pad Length Lead Length *Controlling Parameter Lead Width Drawing No. C04-062 Notes: Exposed pad dimensions vary with paddle size. exceed .010" (0.254mm) per side. Overall Width L b D .019 .012 .007 .047 .055 .010 .118 BSC Number of Pins Standoff Lead Thickness Overall Length Overall Height Pitch A p n Units A E Dimension Limits .000 .001 .008 REF. .118 BSC .031 .026 BSC MIN INCHES NOM TOP VIEW EXPOSED METAL PAD 0.48 0.26 0.30 .022 .069 .015 .096 0.23 1.20 1.39 0.55 0.37 1.75 2.45 0.02 0.80 0.20 REF. MILLIMETERS* .002 .039 0.00 MIN MAX NOM 0.05 1.00 MAX BOTTOM VIEW ID INDEX PIN 1 E L p b n Package may have one or more exposed tie bars at ends. AREA Pin 1 visual index feature may vary, but must be located within the hatched area. (NOTE 2) TIE BAR (NOTE 1) EXPOSED 0.90 .035 (Note 4) (Note 4) 5. JEDEC equivalent: Pending

© 2005 Microchip Technology Inc. NOTES:

© 2005 Microchip Technology Inc. DS21333B-page 21 TC1302A/B APPENDIX A:

REVISION HISTORY

Revision B (January 2005) The following is the list of modifications: Correct the incorrect part number options shown on the Product Identification System page and change the “standard” output voltage and reset voltage combinations. Added Appendix A: Revision History. Revision A (September 2003) Original data sheet release.

© 2005 Microchip Technology Inc. NOTES:

© 2005 Microchip Technology Inc. DS21333B-page 23 TC1302A/B PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Device: TC1302A: Dual Output LDO with Single Shutdown input. TC1302B: Dual Output LDO with Dual Shutdown Inputs. Standard Configurations: * VOUT1/VOUT2 Configuration Code TC1302A 3.0/1.65 DT TC1302B 3.0/1.65 2.6/1.8 2.5/1.8 DT HP IP * Contact Factory for Alternate Output Voltage Configurations. Temperature Range: V = -40°C to +125°C Package: MF = Dual Flat, No Lead (3x3 mm body), 8-lead UA = Plastic Micro Small Outline (MSOP), 8-lead Tube or Tape and Reel: Blank = Tube TR = Tape and Reel Examples: TC1302ADTVMF: 3.0, 1.65, 8LD DFN pkg. TC1302BDTVMF: 3.0, 1.65, 8LD DFN pkg. TC1302BHPVMFTR: 2.6, 1.8, 8LD DFN pkg, Tape and Reel. TC1302BIPVUA: 2.5, 1.8, 8LD MSOP pkg. PART NO. X VOUT1 Type A/B TC1302 X VOUT2 X Temp Range XX Package XX Tube or Tape & Reel Standard Configurations

© 2005 Microchip Technology Inc. NOTES:

© 2005 Microchip Technology Inc. DS21333B-page 25 Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WAR- RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

© 2005 Microchip Technology Inc. AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westford, MA Tel: 978-692-3848 Fax: 978-692-3821 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Qingdao Tel: 86-532-502-7355 Fax: 86-532-502-7205 ASIA/PACIFIC India - Bangalore Tel: 91-80-2229-0061 Fax: 91-80-2229-0062 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 Japan - Kanagawa Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Taiwan - Hsinchu Tel: 886-3-572-9526 Fax: 886-3-572-6459 EUROPE Austria - Weis Tel: 43-7242-2244-399 Fax: 43-7242-2244-393 Denmark - Ballerup Tel: 45-4450-2828 Fax: 45-4485-2829 France - Massy Germany - Ismaning Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 England - Berkshire Tel: 44-118-921-5869 Fax: 44-118-921-5820 WORLDWIDE SALES AND SERVICE 10/20/04