TC110G26

TC110G TOSHIBA | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 5

Technical content

Toshiba introduces the new generation gate arrays - The TC110G series-capable of integrating 5X more than the TC17G series. Uses Toshiba's proprietary HC 2MOSNLSI technologies. State of the art processing with high packlng densities which produced a 4Mbit Dynamie RAM. TC110G Series-50K gates/D.6ns. Compact and powerful! General Toshiba CMOS Gate Array family, TC11 OG Series, with interconnect routing which is not confined to "routing channels". This technique increases silicon efficiency (functions/mm2). Higher density and Toshiba HC 2 MOS process provide subnanosecond speeds of 0.6ns typical gate delays (2-input NAND gate, fanout=2, tpd.). TC110G Series is introduced as 14 base arrays with 1 .4K to 50K estimated usable gates. Gate Array design using TC 11 OG Series is supported by the TOSHIBA MAINFRAME CAD SYSTEM. Hierarchical designs with large macro capabilites. Product Lines Part Number Gate'n Estimated<2l Complexitv Usable Gates TC110G C9 129,042 50,000 TC110G AO 100, 182 40,000 TC110G 75 74,970 30,000 - -- ·-----TC110G 51 50,904 20,000 TC110G 38 37,932 15,000 TC110G 32 32,000 13,000 TC110G 26 25,740 10,000 TC110G 21 21,060 8,400 -- TC110G 17 17,082 6,800 TC110G 14 14,204 5,600 TC110G 11 11,092 4,400 TC110G 08 8,000 3,200 TC110G 05 5,120 2,000 - TC110G 03 3,498 1.400 Notes: 1 . Raw-gates. Product Specifications Process technology Gate speed (inner gate, typ.) Maximum loggie frequency Supply voltage Application Maximum Pads '3> 368 326 282 234 204 188 168 154 140 128 114 100 - 2. Based on 40% array utilization. Actual utilization varies, depending on cell types used. 3. Additional I/O pads may be configured as Voo/Vss, subject to number and drive of output buffers. 4. I/O signals presently limited to 256 by tester capability.

• Thistechnical data may be controlled u n der U.S. Export Administration Regulations and may be subjectto the approval of the Ex ort Administration Re ulations is strictly rohibited. I TC11 OG series HC 2MOS Si-gate double layer metal 1.5µm 0.6ns 150MHz ASTTL/ECL Maximum I/O Pads ''H4> 256 256 256 226 -- 196 180 160 146 132 120 106 - TAEC

Basic Cell Delay vs Fanout (TC110G38 , Voo= SV , Ta= 2S°C with estimated wiring lengths) Basic Cell Output Buffer lnput Buffer U) 5 ~s en s i; 4 ~4 i; 4 Qi ~~· Q) Qj "O "O 3 ~ 3 c: 3 ~ o c:

• ~ 2 .Q o ro 2 ·~ 2 tU Ol Ol ~ c. ro ro e , c. c. 01 0 1 ,,,_ JBUF Cl. ci: ci: 1 2 3 4 5 6 7 a g 10 20 40 60 80 100 1 ? 3 4 5 6 7 8 9 10 Fanout Output Load Capacitance (pF) Fan out Absolute Maximum Ratings (Vss = OV) Recommended Commercial Operating Conditions (Vss = OV) Symbol Parameter Rating Unit Voo DC supply voltage -0.3 to +7.0 V Symbol Parameter Rating Unit V1N DC input voltage - 0.3 to Voo+ 0.3 V Voo DC supply voltage 4.75 to 5.25 V l1N DC input current ::1:10 mA Ta Ambient temperature O to + 70 oc Tstg Storage temperature -40 to + 125 oc Specified at Voo= SV ± 5% ambient temperature Symbol Parameter Condltion TC11 OG Serles Unit Min. Max. Low Level lnput Voltage V1H TTL Level 2.0 V CMOS Level 3.5 SCHMITT Trigger 4.0 Hi~h Level lnput Voltage V1L TTL Level 0.8 V CMOS Level 1.5 SCHMITT Trigger 1.0 hH High Level lnput Current V1N=Voo -10 10 µ,A With Pull-down Resistors 10 200 hL Low Level lnput Current V1N =Vss -10 10 µ,A With Pull-up Resistors -200 -10 High Level Output Voltage Type 81 loH= -1mA Type B2 loH= -2mA VoH Type B4 loH= -4mA 2.4 V Type B6 loH= -6mA Type B8 loH= -SmA Type B121•> loH= -12mA Low Level Output Voltage Type B1 loL=1mA Type s3 ___ loL=2mA VoL Type B4 loL=4mA 0.4 V Type B6 loL=6mA Type B8 loL=BmA Type 812<1> lm=12mA - -- High lmpedance Leakage Current -10 10 loz With Pull-up Resistors VouT=Voo or Vss -200 -10 µ,A With Pull-down Resistors 10 200 loo Quiescent Supply Current _ V1N '."'Voo or Vss 10012) µ,A Notes: (1) Requ1res two output pads. (2) Customer-Design Dependent

Development Flow & Customer Interface Interface level Level 3 Level 4 (1) At level-2, design proced ure takes place by custom er at Toshiba LSI D esign Center and at customer site for level-3. (2) As for the EWS supp ort. please refer to "EWS INTERFACE " (Oocument ID: SEMl-E-81011) CAS System Features •TOSHIBA MAINFRAME CAD SYSTEM Integrated Hlerarchlcal Design System • Functional design • Logic design • Auto place using Macrocell and Macrofunctions library for: & route •Test pattern generation High-speed logic slmulatlon and Flexible auto place and route Maximum circuit size: • 50K gates Compatible Interface language (TOL, TSTL) Rernote-access In man·machine environment Package Adaptability List As of June 1989 ! 24 DIP 42 I 542 564 100 PGA 120 135 f MetalPGA 144 180 224 120 144 Cavity Down PGA 155 223 299 PLCC 68 i 84 I I µ 44 100A 11 Square 100 1) PFP 120 144 160 184 I Rectangular f--- 100 100 '1 CFP 144 160 184 A : Adap table D Chec k w ith Toshiba for availability (Under development) P: Check w ith Toshiba for availability (Un der planning) A A A A A A A A A A A A A 05 08 11 14 17 21 26 32 38 51 75 AD C9 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A D D A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A p p p D D D D D A A A A A A A A A A A A A p A A A A A A A A A D A A A . A A A A A : D A A D D A A A A A A A A A A D D A A A A A A A A A A D D D D D D D A A A A A A A A A D p p A A A A A p p A A A A A D p p A A A A A p p A A A A A A p A A : A A p p A A A A A A A A D D D D D D D D D ; D D D D Notes: 1) Fiat Package 100 pin is classified into 2 types determined by numbe r of inner leads available: 100A - 84 inner leads. 100-100 1nner leads. 2) Please refer to "Package Selector Guide" (Docum ent I.O. SEMl -E-S 1001) for further information in detail.

Gate Array? TC11 OG Series Library TC17G series-compatlble macrocells and macro­ functions

• Macrocell performance optimization (Standard/High drive)
• Macrocell equivalent to SSl/MSI Functional block of Megacells, Megafunctions
• 2900 family Macrocells Logic Gate 62 lnverter/lnternal Buffer 15 Tri-state Interna! Buffer 6 Latch 22 Flip-flop 36 Decoder 8 Multiplexer 14 Adder 6 lnput Buffer 48 Output Buffer 40 Total 581 RAM RAM-C SINGLE) PORT RAM RAM-E TRIPLE) PORT RAM
• Asynchronous
• Separated 1/0, 3 state Output
• Max. 4608 Bit/Black (8 - 256 Word X 4 -36 Bit)
• Read Access Time (tAcc) 15ns typ. _
• Asynchronous
• 2 Read 1 Write e Max. 1152 Bit/Block (16-64 Word X 4-18 Bit)
• Read Access Time(tAcc) 11 ns typ. Part No.: TC110G 51 Used Gates: 15000 Gates
• Multiplier, Barrelshifter, ALU, CLA, FIFO e LSl/VLSI CPU Peripheral Buildlng-block memory (32 to 16K bit)
• RAM cell: 3 gates
• ROM cell: 1/4 gate
• Customer-defined architecture Macrofunction List Types Function LSI 74HC Series Compatible Compatible COMPARATORS 6 2 COUNTERS 19 11 DECODERS 10 4 ---- FLIP-FLOPS - 6 GATES - 16 MULTIPLEXERS 11 10 - -- -- REGISTERS 19 16 ---- ---- OTHERS 8 7 Total 77 73 ROM ROM-A • Asynchronous SINGLE) e Max . 16384 Bit/Block PORT (64 - 1024 Word X 2 - 32 Bit) ROM •Read Access Time(tAcc) 18ns typ.

Features

• Proprietary 1.5µm HC 2 MOS/VLSI process technology.
• 0.6ns speed (2-input NAND gate, fanout = 2, tpd.)
• Achieves ultra high speed equivalent to 10K ECL.
• High packing density up to 129K raw gates.
• 3K to 129K raw gates.
• Up to 256 110 pins.
• Variable channel width architecture allows efficient silicon utilization.
• Full input/output TTL/CMOS compatibility.
• Advanced packaging techniques.
• Design is fully supported by TOSHIBA MAINFRAME CAD SYSTEM
• Programmable I/O cells with siew rate control (e.g. Output drive up to 12mA).
• Large macro capability (e.g. RAMs, ROMs, Megafunctions, Megacells* ).
• Performance optimization (e.g. Standard/High drive cells).
• Scheduled to be released gradually TC110G Series Base Array
• Variable routing track and column
• Max. 129K raw gates (1 raw gate=2 pairs of Pch./Nch. transistor=4 transistors) Fixed column 1 gate Fixed routing channel (1 basie cell) RAM/ROM Variable routing track 1 raw gate (1 unit cell) 1 gate = 1 basie cell 3§J3§83§G~ Nch Pch Nch ~ Double co\\umn = 1 unit cell = 1 raw gate ingle column = 1 gate single column = 1 gale