SN888C TI1 | Alldatasheet
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Technical content
- Exceeds Requirements of EIA-485 Standard • E-meters
- Bus-Polarity Correction within 76 ms DESCRIPTION• Data Rate: 300 bps to 250 kbps The SN888C is a low-power RS-485 transceiver with• Works with Two Configurations: bus-polarity correction and transient protection. Upon – Failsafe Resistors Only hot plug-in the device detects and corrects the bus polarity within the first 76 ms of bus idling. On-chip– Failsafe and Termination Resistors transient protection protects the device against• Up to 256 Nodes on a Bus IEC61000 ESD and EFT transients.
- SOIC-8 Package for Backward Compatibility The SN888C is available in an SOIC-8 package. The• Bus-Pin Protection: device is characterized from –40°C to 85°C. – ±16 kV HBM protection – ±12 kV IEC61000-4-2 Contact Discharge – +4 kV IEC61000-4-4 Fast Transient Burst
Figure 1. Typical Network Application With Polarity Correction (POLCOR) Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. necessarily include testing of all parameters.
B A D DE R RE POLCOR D R DE RE Vcc B A GND SN888C SLLSEI4 –SEPTEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. SOIC-8 Block Diagram(TOP VIEW) DRIVER PIN FUNCTIONS INPUT ENABLE OUTPUTS
DESCRIPTION
H H H L Actively drives bus high L H L H Actively drives bus low X L Z Z Driver disabled X OPEN Z Z Driver disabled by default OPEN H H L Actively drives bus high POLARITY-CORRECTING MODE(1) H H L H Actively drives bus low L H H L Actively drives bus high X L Z Z Driver disabled X OPEN Z Z Driver disabled by default OPEN H L H Actively drives bus low (1) The polarity-correcting mode is entered when VID < VIT– and t > tFS and DE = low. This state is latched when /RE turns from low to high. RECEIVER PIN FUNCTIONS DIFFERENTIAL ENABLE OUTPUTINPUT DESCRIPTION VID = VA – VB /RE R NORMAL MODE VIT+ < VID L H Receive valid bus high VIT– < VID < VIT+ L ? Indeterminate bus state VID < VIT– L L Receive valid bus low X H Z Receiver disabled X OPEN Z Receiver disabled Open, short, idle bus L ? Indeterminate bus state POLARITY-CORRECTING MODE(1) VIT+ < VID L L Receive valid bus low VIT– < VID < VIT+ L ? Indeterminate bus state VID < VIT– L H Receive polarity corrected bus high X H Z Receiver disabled X OPEN Z Receiver disabled Open, short, idle bus L ? Indeterminate bus state (1) The polarity-correcting mode is entered when VID < VIT– and t > tFS and DE = low. This state is latched when /RE turns from low to high.
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Product Folder Links: SN888C
www.ti.com SLLSEI4 –SEPTEMBER 2013 ABSOLUTE MAXIMUM RATINGS(1) VALUE UNIT MIN MAX VCC Supply voltage –0.5 7 Input voltage range at any logic pin –0.3 5.7 V Voltage input range, transient pulse, A and B, through 100 Ω –100 100 Voltage range at A or B inputs –18 18 Receiver output current –24 24 mA Continuous total-power dissipation See THERMAL INFORMATION table IEC 61000-4-2 ESD (Contact Discharge), bus terminals and GND ±12 IEC 61000-4-4 EFT (Fast transient or burst) bus terminals and GND ±4 IEC 60749-26 ESD (HBM), bus terminals and GND ±16 kV Test Method A114 (HBM), all pins ±8 JEDEC Standard 22 Test Method C101 (Charged Device Model), all pins ±1.5 Test Method A115 (Machine Model), all pins ±200 V TJ Junction temperature 170 TSTG Storage temperature –65 150 (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. THERMAL INFORMATION SN888C THERMAL METRIC(1) UNITSPACKAGE SOIC (D) θJA Junction-to-ambient thermal resistance 116.1 θJCtop Junction-to-case (top) thermal resistance 60.8 θJB Junction-to-board thermal resistance(2) 57.1 °C/W ψJT Junction-to-top characterization parameter 13.9 ψJB Junction-to-board characterization parameter 56.5 θJCbot Junction-to-case (bottom) thermal resistance NA (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. POWER DISSIPATION PARAMETER TEST CONDITIONS VALUE UNITS RL = 300 Ω, 164UnterminatedPower dissipation CL = 50 pF (driver) Driver and receiver enabled, RL = 100 Ω, 247PD VCC = 5.5 V, TJ = 150°C RS-422 load mWCL = 50 pF (driver)50% duty cycle square-wave signal at RL = 54 Ω, 316250-kbps signaling rate: RS-485 load CL = 50 pF (driver) Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: SN888C
SLLSEI4 –SEPTEMBER 2013 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VCC Supply voltage 4.5 5 5.5 VID Differential input voltage –12 12 VI Input voltage at any bus terminal (separate or common mode)(1) –7 12 V VIH High-level input voltage (driver, driver-enable, and receiver-enable inputs) 2 VCC VIL Low-level input voltage (driver, driver-enable, and receiver-enable inputs) 0 0.8 Driver –60 60 IO Output current mA Receiver –8 8 CL Differential load capacitance 50 pF RL Differential load resistance 60 Ω 1/tUI Signaling rate 0.3 250 kbps TJ Junction temperature –40 150 °CTA(2) Operating free-air temperature (see THERMAL INFORMATION for additional –40 85 information) (1) The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet. (2) Operation is specified for internal (junction) temperatures up to 150°C. Self-heating due to internal power dissipation should be considered for each application. Maximum junction temperature is internally limited by the thermal shut-down (TSD) circuit which disables the driver outputs when the junction temperature reaches 170°C.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RL = 60 Ω, 375 Ω on each See Figure 2 1.5 2.5 output from –7 to +12 VDriver differential-output│VOD│ Vvoltage magnitude RL = 54 Ω (RS-485) 1.5 2.5 See Figure 3 RL = 100 Ω (RS-422) 2 3 Change in magnitude of RL = 54 Ω, CL = 50 pF –0.2 0 0.2Δ│VOD driver differential-output See Figure 3 V│ voltage Steady-state common-mode 1 VCC / 2 3VOC(SS) Voutput voltage Change in differential driver –0.2 0 0.2Center of two 27-Ω loadΔVOC common-mode output See Figure 3resistorsvoltage mV Peak-to-peak driver common- 850VOC(PP) mode output voltage Differential output 8COD pFcapacitance Positive-going receiver 35 100 VIT+ differential-input voltage mV threshold Negative-going receiver –100 –35 VIT– differential-input voltage mV threshold Receiver differential-input 40 60 VHYS (1) voltage threshold hysteresis mV (VIT+ – VIT– ) Receiver high-level output IOH = –8 mA 2.4 VCC – 0.3VOH Vvoltage Receiver low-level output IOL = 8 mA 0.2 0.4VOL Vvoltage Driver input, driver enable, –2 2 II and receiver enable input µA current (1) Under any specific conditions, VIT+ is ensured to be at least VHYS higher than VIT–.
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Product Folder Links: SN888C
www.ti.com SLLSEI4 –SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Receiver high-impedance VO = 0 V or VCC, /RE at VCC –10 10IOZ µAoutput current Driver short-circuit output │IOS│ with VA or VB from –7 to +12 V 150│IOS│ mAcurrent VCC = 4.5 to 5.5 V or VI = 12 V 75 125Bus input current (driverII µAdisabled) VCC = 0 V, DE at 0 V VI = –7 V –100 –40 Driver and receiver enabled DE = VCC, /RE = 750 900 GND, No load Driver enabled, receiver DE = VCC, /RE = VCC, 650 disabled No load ICC Supply current (quiescent) µA Driver disabled, receiver DE = GND, /RE = 750 enabled GND, No load Driver and receiver disabled DE = GND, D = GND 0.4 5 /RE = VCC, No load Supply current (dynamic) See SWITCHING CHARACTERISTICS 3.3 ms > bit time > 4 μs (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DRIVER tr, tf Driver differential-output rise and 400 700 1200 fall times RL = 54 Ω, CL = 50 See Figure 4 nstPHL, tPLH Driver propagation delay pF 90 700 1000 tSK(P) Driver pulse skew, |tPHL – tPLH| 25 200 tPHZ, tPLZ Driver disable time 50 500 nsSee Figure 5 andtPHZ, tPLZ Driver enable time Receiver enabled 500 1000Figure 6 Receiver disabled 3 9 µs RECEIVER tr, tf Receiver output rise and fall times 18 30 tPHL, tPLH Receiver propagation delay time CL = 15 pF See Figure 7 85 195 ns tSK(P) Receiver pulse skew, |tPHL – tPLH| 1 15 tPHZ, tPLZ Receiver disable time 50 500 tPZL(1), Driver enabled See Figure 8 20 130 ns tPZH(1) Driver disabled See Figure 9 2 8 µsReceiver enable timetPZL(2), tPZH(2) tFS Bus failsafe time Driver disabled See Figure 10 44 58 76 ms Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: SN888C
Figure 2. Measurement of Driver Differential-Output Voltage With Common-Mode Load Figure 3. Measurement of Driver Differential and Common-Mode Output With RS-485 Load Figure 4. Measurement of Driver Differential-Output Rise and Fall Times and Propagation Delays Figure 5. Measurement of Driver Enable and Disable Times With Active-High Output and Pull-Down Load Figure 6. Measurement of Driver Enable and Disable Times With Active-Low Output and Pull-Up Load
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1.5 V or 0 V
Figure 7. Measurement of Receiver Output Rise and Fall Times and Propagation Delays Figure 8. Measurement of Receiver Enable and Disable Times With Driver Enabled Figure 9. Measurement of Receiver Enable Times With Driver Disabled Figure 10. Measurement of Receiver Polarity-Correction Time With Driver Disabled
D,RE Vcc DE Input 100k DE Vcc R Output R Vcc 16V 16V A B Driver Outputs 16V 16V A Receiver Inputs Vcc B R SN888C SLLSEI4 –SEPTEMBER 2013 www.ti.com EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
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Product Folder Links: SN888C
Figure 12. Polarity Correction Timing Prior to a Data Transmission reverses the input signal and RS turns high. POLCOR logic, then fed into the driver. polarity is reestablished at the master end. This process repeats each time the device powers up and detects an incorrect bus polarity.
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B A D DE R RE POLCOR a) Independent driver and receiver enable signals b) Combined enable signals for use as directional control pin c) Receiver always on R D Vcc GND B A D DE R RE POLCOR R D Vcc GND B A D DE R RE POLCOR R D SN888C www.ti.com SLLSEI4 –SEPTEMBER 2013
APPLICATION INFORMATION
The SN888C device is a half-duplex RS-485 transceiver operating from a single 5-V ±10% supply. The driver and receiver enable pins that allow for the configuration of different operating modes. Figure 13. Transceiver Configurations Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal. sent on the bus, enabling the node to verify the correct data has been transmitted. RS-485 cable with Z0 = 120 Ω. Typical cable sizes are AWG 22 and AWG 24. Table 1. VID With a Failsafe Network and Bus Termination
1 KΩ 1 KΩ 131 mV
5 V 54 Ω
10 KΩ 10 KΩ 13 mV
failsafe networks with a 54-Ω differential bus termination.
signal jitter of up to 5 or 10%. leading to a maximum physical stub length as shown in Equation 1.
- tr is the 10 / 90 rise time of the driver
- c is the speed of light (3 × 108 m/s or 9.8 × 108 ft/s)
- v is the signal velocity of the cable (v = 78%) or trace (v = 45%) as a factor of c (1) Based on Equation 1, with a minimum rise time of 400 ns, Equation 2 shows the maximum cable-stub length of the SN888C device. LStub ≤ 0.1 × 400 × 10-9 × 3 × 108 × 0.78 = 9,4 m (or 30.6 ft) (2)
Figure 14. Stub Length
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encountered in industrial environments, such as in factory automation and power-grid systems. with the aforementioned 500-V surge transient. surge transient almost disappear from the scale. Figure 17. Power Comparison of ESD, EFT, and Surge Transients transients as well as for an EFT pulse train, commonly applied during compliance testing.
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SLLSEI4 –SEPTEMBER 2013 www.ti.com Design and Layout Considerations for Transient Protection Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high- frequency layout techniques must be applied during PCB design. In order for PCB design to be successful, begin with the design of the protection circuit in mind. 1. Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your board. 2. Use Vcc and ground planes to provide low-inductance. Note that high-frequency currents follow the path of least inductance, not the path of least impedance. 3. Design the protection components into the direction of the signal path. Do not force the transients currents to divert from the signal path to reach the protection device. 4. Apply 100-NF to 220-nF bypass capacitors as close as possible to the VCC-pins of transceiver, UART, controller ICs on the board. 5. Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to minimize effective via-inductance. 6. Use 1-k to 10-k pull-up or pull-down resistors for enable lines to limit noise currents in these lines during transient events. 7. Insert pulse-proof resistors into the A and B bus lines, if the TVS clamping voltage is higher than the specified maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping current into the transceiver and prevent it from latching up. – While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal- oxide varistors (MOVs), which reduce the transients to a few-hundred volts of clamping voltage, and transient blocking units (TBUs) that limit transient current to 200 mA.
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Product Folder Links: SN888C
the bus transceiver through a multi-channel, digital isolator (Figure 20). Figure 20. Isolated Bus Node With Transient Protection Power isolation is accomplished using the push-pull transformer driver SN6501 and a low-cost LDO, TLV70733. pulled-up via 4.7-k resistors to limit input currents during transient events. diversion is necessary as noise transients on the bus are usually referred to earth potential. prevent charging of the floating ground to dangerous potentials during normal operation. transients might charge CHV to high-potentials. connecting this island to PE ground at the entrance of the power supply unit (PSU). the chassis at the other end.
www.ti.com 16-Feb-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN888CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 RS485N EESA SN888CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 RS485N EESA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
www.ti.com 16-Feb-2014 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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