TBA520

TBA520 FAIRCHILD | Alldatasheet

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FAIRCHILD LINEAR INTEGRATED CIRCUIT GENERAL DESCRIPTION — The TBA52O is synetvonous demodulator for drect drive of color ‘ideo output stages tt consuvcted on a single slicon chip sing the Falrculd Plose soit CONNECTION DIAGRAM Process. The TBA520 is designed for use in color television receivers, operating on the Phase Alternate - Line PAL} system. This circuit consists of two synchronous demodulators, a decoding matrix and a (TOP VIEW) PAL switch with internal multivibrator. PACKAGE OUTLINE 98 voamircation : Pew evrerin FS cine puLse © DOUBLE BALANCED SYNCHRONOUS DEMODULATOR mae one ans ¢ INTERNAL DECODING MATRIX, ny our ay # INTERNAL PAL SWITCH evrowa © PROVISION FOR OUTPUT DC LEVEL MATCHING Sy our LEVEL AOJUST : “o a your est POINT ps f By arin Pe eowa i ABSOLUTE MAXIMUM RATINGS oh ‘Supply Voltage aa 13.2V ORDER INFORMATION. Internal Power Dissipation Lp 550 mW TYPE PART NO. Voltage on Identification Input A oy 50V 520 TBA520 Current into Identification input ¢ }e & 1.0mA (6200) —(TrBAS200}1 Operating Temperature Range y 20°C to +60°C ‘Storage Temperature Range 85°C to +125°C {Not recommended for new design. Pin Temperature (Soldering, 10 s) 260°C EQUIVALENT CIRCUIT ee =a ! == ie al 5 : i [br eee | : ae ane fal 108

FAIRCHILD ¢ TBAS20 ELECTRICAL CHARACTERISTICS: Tq = 25°C, V,.= 12V, See Test Circuit, unless otherwise specified, CHARACTERISTICS CONDITIONS [min [Tye | Max | UNITS Supply Current (lg) a ma Tolor Difference Gain RLY Chane! 20) vv BY Channel Vg = V13 = 50 mVpk-ak, f= 4.4 MHz | 125 vw G-Y Channel | tote 1) Maximum Color Difference Output Voltage (Notes 2,3) R-Y Output (V4 pk-pk) | (Notes 2,3) 3.2 Vpkpk B-Y Output (V7 pk-pk) 40 Vpk-pk G-Y Output (V5 pk-pk) 18 Vpk-pk Color Difference de Output Voltage 1 R-Y Output (V4) 79 v B-Y Output (V7) 7 | toy G-¥ Output (Vs) 7 | v Input Resistance of Chroma Inputs (R9, R13) | Vg = V13= 20mVrms (Sinusoidal) a Input Capacitance of Chroma Inputs (C9,C13)__|_f = 4.4MHz pF Output Resistance at Color Difference ? a 4 Terminals (R4, R5, R7) | 2 “ input Resistance of Reference Inputs (2, RB) [oe de Peak-to-Peak PAL Switch Output Voltage | (V3 pk-pk) (Note 4) 25 Vpk-pk ‘etivation Threshold Voltage (V4) ~ OTS vO Activation Threshold Current (14) "ification Circuit is Active 80 | uA Deactivation Threshold Voltage (Va) Tdentification Cieultis nective -| «dt NoTEs. 1. GY output is typically equal to 0.51 (#-Y) ~0.19 (8-¥). 2. Gain is equal t0.0.7 of sma signal gain 3. Reference input (Vapepu and Vapi -px) range is 0.5 V t0 2.0 V. | Test ciRcUIT UNE PULSE INPUT tt oT Ose neu 20 nF. etry ty © 18-y) eur bs hs fs bs pe ps fo fo TIT 771 \\oEnro OrtFey, FEFANO 0 32% Zine input ak nero 3 PAL Switch OUTPUT $Sy eure = sor fae 16OF 150F = 9 BY CHROMA INPUT T son fom T3200 Beet aonsr | = = coor 13 Rye cever aBasT rl jr ai TeANE nase pur Laser wow L 1 preaticeresniis i = = TB onauno —Eaeae—ee ours 4-185,

FAIRCHILD ¢ TBAS20

APPLICATION INFORMATION

‘The function is quoted against the corresponding pin numbers. 1. Identification bias The input current required to stop the flip-flop, “Ident on": Ion > BOUA. For “Ident off”: Voff = 8.0 t0 40.4 V. 2. RY subcarrier reference input An 1.0 V peak-to-peak signal is required via a de blocking capacitor, Under no circumstances should this signal be less than 0.5 V peak-to peak. The input resistance at this pin i typically 1kS 3. PAL square wave output The amplitude is 2.5 V peak-to-peak from an emiter follower 4, RLY signal output (G-¥ at pin 5 and B-Y at pin 7) No external de load needed except that direct connection must be made vie the low pass filter to the FG 8 matrix of the TBAS3O. ‘The signals produced are in the following ratios: Vev=13VRy (al Vey = 0.76 Vay () Vg. 0.26 Vay Condition (a) refers to (B-¥) + (R-Y) audition in the G-¥ matrix. Condition (b) refers to the phase reversed (RY! input signal where (G-Y) is obtained by subteaction. The de levels should each be adjusted, starting with the (B-¥) to +7.5 V at nominal supply voltage. j The maximum peak-to-peak voltages for the condition m > 0.7 (m = ratio of minimum to maximum differential gains) are: Va-vipk-pk) "3-2 Vo-vipkpk) "18 Ve-Viok-ok) = 4.0V The output impedance for each signal is 2.7 KO. The drifts in de levels of the color difference output signals for a change in ambient temperature of 40°C fatter equilibrium is reached from switch-on) are typically: Absolute shitt 50 t0 +50mV Vay relative to Vg.y — -20 0 +20mV j Ve.y realtive to Vg.y — ~20t0 +20mV Vay telative to Vg.y — -20t0 +20mV The changes in de level with supply voltage are approximately linear and track together. The ~3.0d8 bandwidth of the color difference signals is 1.5 MHz 5. GY signal output (see pin 4) 6. Positive supply Also de level setting for B-Y output (pin 7). The maximum allowable voltage on this pin is 13.2 V. The minimum supply voltage to insure | setting the B-Y output de level correctly (+7.5 V) is 11.6 V (in such case Rig would be set to zero). 7. BLY signal output (see pin 4) 8. BLY subcarrier reference input The requirements here are identical with those for pin 2. 9. Chrominance B-Y input signal {An input signal up 10 360 mV peak-to-peak (color bars) is advisable. For driving the TBAS3O an input signal of 160 mV is required. 10, Internally connected No external connection should be made. 11. C level setting for G-¥ output signal (circuit diagram on page 2) 12, DC level setting for R-Y output (see circuit diagram on page 2) 13. Chrominance R-Y input signat | ‘An ingut signal up t0 600 mV peak-to-peak (color bors) is advisable. The input impedance is the same as for pin 9. 14, Line pulse input (flip-flop synchronizing) | A 4.0 V poak negative going line flyback pulse should be applied via separate 10 nF capacitors to pins 14 and 15, Pulse amplitude to lie between 3.0 V and 4.5 V peak-to-peak. 15, Line pulse input (see pin 14). | 16. Ground. BLOCK DIAGRAM | | 4 aay eS CaS ee CS OC <n 4-186