TB9081FG

TB9081FG TOSHIBA | Alldatasheet

Document overview

• PDF pages: 65

Technical content

Features

• 3-phase pre-drivers : PWM control to 20kHz
• Build-in fail-safe relay pre-drivers
• Build-in Charge Pump
• High response Current Detection circuit
• Miscellaneous-abnormal-detection circuits (Under voltage (VB, VCC) / Over voltage (VCC) / Over temp. / FET short-circuit detection)
• Build-in ABIST/LBIST functions
• Operating voltage range : VB=4.5 to 28V, VCC=3.0 to 5.5V
• Operational temperature range : -40 to 125°C
• Package : LQFP-64pin (0.5mm pitch)
• AEC-Q100 Qualified
• TM-SILTM  Developed according to ISO 26262 ASIL-D  Safety Manual and Safety Analysis Report  Functional redundancy and built-in ABIST and LBIST  SPI interface with CRC check The product(s) is/are compatible with RoHS regulations (EU directive 2011 / 65 / EU) as indicated, if any, on the packaging label ("[[G]]/RoHS COMPATIBLE", "[[G]]/RoHS [[Chemical symbol(s) of controlled substance(s)]]", "RoHS COMPATIBLE" or "RoHS COMPATIBLE, [[Chemical symbol(s) of controlled substance(s)]]>MCV"). LQFP64-P-1010-0.50E Weight: 0.35 g (typ.)

2019-02-27 2 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Table of contents Internal block diagram Package pin layout (top view) Pin description Functional descriptions (1) Charge pump circuit (2) Pre -drivers (3) Current detector (4) Oscillator/divider (5) Abnormal detecti on circuit (5-1) VB1/VB2 under voltage detection (5-2) VCC1/VCC2 under voltage detection (5-3) VCC1/VCC2 over voltage detection (5-4) Over temperature detection (5-5) Short-circuit detection (5-6) Oscillati on frequency monitoring (6) ALARM input circuit (7) EN_CP input circuit (8) ABIST function (9) SPI Communication circuit (9-1) SPI communication operation (9-2) Register map Absolute maximum ratings

Electrical characteristics

Revision history

RESTRICTIONS ON PRODUCT USE

2019-02-27 3 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Internal block diagram Notes 1: Some of the functional blocks, circuit, or constants in the block diagram may be omitted or simplified for explanatory purpose. (including individual block diagram) VB1 VB2 HUO HVO LUO LVO PGND1 PGND2 PGND3 VRI SDIN SDOUT SCK TEST LWO /CS ALARM1 HWO BR1O RUO ALARM2 CLKOUT NDIAG VCC_OP BR2O RVO RWO BR1I BR2I RUI RVI RWI HUI HVI HWI LUI LVI LWI VRO AMP1P AMP1N AMP2N AMP2O AMP2P AMP3P AMP3N AMP3O AMP1O SHW SHV SHU HS AGND1 AGND2 VCC1 VCC2 EN_CP CP1H CP1L VCPL CP2H CP2L VCPH Each voltage det ection cir cuit Current sensor AMP1AMP3 V REF1 AMP2 Pre-Driver 11ch For Motor：6ch For Relay：5ch OSC SPI FET short detection TSD1 TSD2 TSD3 Charge pump ALA RM input circuit Error Logic BG1 BG2 EN_CP input circuit

2019-02-27 4 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Package pin layout (top view) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 BR2I RUI RVI RWI TB9081FG BR1I PGND2 RWO RVO RUO LWO LVO LUO PGND1 NC SCK CLKOUT AMP1P VRO AGND1 VCC1 SDOUT SDIN VRI AMP3O AMP3N AMP3P AMP2O VCC_OP AMP1N AGND2 HVI HWI LUI LVI LWI /CS HUI TEST CP2L VB2 HUO HVO AMP2N AMP2P SHW NDIAG CP1LALARM2 CP1H ALARM1 AMP1O EN_CP SHV CP2H VB1 BR1O BR2O VCPH HS VCPL SHU VCC2 PGND3 HWO

2019-02-27 5 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Pin description Pin No. Symbol Input/output Definition Pull-Up/Down Notes

1 RUI IN U-Phase Motor Relay Input Pull-Down 50kΩ -

2 RVI IN V-Phase Motor Relay Input Pull-Down 50kΩ -

3 VCC2 Power supply Power supply 2 (3.3V or 5V) - - -

4 RWI IN W-Phase Motor Relay Input Pull-Down 50kΩ -

5 PGND1 GND Power GND1 - - -

6 RUO OUT U-Phase Motor Relay Output - - push-pull

7 RVO OUT V-Phase Motor Relay Output - - push-pull

8 RWO OUT W-Phase Motor Relay Output - - push-pull

9 NC - - - - -

10 LWO OUT Pre-Driver Output LW - - push-pull

11 LVO OUT Pre-Driver Output LV - - push-pull

12 LUO OUT Pre-Driver Output LU - - push-pull

13 PGND2 GND Power GND2 - - -

14 HS IN High-side Drain Input - - -

15 SHU IN Motor Connect PIN U-phase - - -

16 VCPL Power supply Charge-pump voltage (for low sides) - - -

17 CP2L OUT 2nd Charge Pump Drive Output - - push-pull

18 SHV IN Motor Connect PIN V-phase - - -

19 CP1L OUT 1st Charge Pump Drive Output - - push-pull

20 SHW IN Motor Connect PIN W-phase - - -

21 CP2H IN/OUT 2nd Charge Pump Output - - -

22 VCPH Power supply Charge-pump voltage (for high sides) - - -

23 CP1H IN/OUT 1st Charge Pump Output - - -

24 VB2 Power supply Power Supply2 (Battery 12V) - - -

25 VB1 Power supply Power Supply1 (Battery 12V) - - -

26 HWO OUT Pre-Driver Output HW - - push-pull

27 HVO OUT Pre-Driver Output HV - - push-pull

28 HUO OUT Pre-Driver Output HU - - push-pull

29 BR2O OUT BR2 Power supply relay Output - - push-pull

30 BR1O OUT BR1 Power supply relay Output - - push-pull

31 PGND3 GND Power GND 3 - - -

32 EN_CP IN Charge-pump enable signal Pull-Down 50kΩ -

33 BR2I IN BR2 Power supply relay Input Pull-Down 50kΩ -

34 BR1I IN BR1 Power supply relay Input Pull-Down 50kΩ -

35 HWI IN Pre-Driver Input HW Pull-Down 50kΩ -

36 HVI IN Pre-Driver Input HV Pull-Down 50kΩ -

37 HUI IN Pre-Driver Input HU Pull-Down 50kΩ -

38 LUI IN Pre-Driver Input LU Pull-Down 50kΩ -

39 LVI IN Pre-Driver Input LV Pull-Down 50kΩ -

40 LWI IN Pre-Driver Input LW Pull-Down 50kΩ -

41 /CS IN SPI chip select Pull-Up 50kΩ -

42 SCK IN SPI clock input Pull-Down 50kΩ -

43 VCC1 Power supply Power supply 1 (3.3V or 5V) - - -

44 SDIN IN SPI input Pull-Down 50kΩ -

45 SDOUT OUT SPI Output - - push-pull

46 AGND1 GND The GND 1 for analog circuits - - -

47 VRO OUT Reference voltage amplifier Output - - -

48 VRI IN Reference voltage amplifier input - - -

49 AMP3O OUT Current-detection amplifier Output 3 - - push-pull

50 AMP3N IN Current-detection amplifier input 3 (-) - - -

51 AMP3P IN Current-detection amplifier input 3 (+) - - -

52 AMP2O OUT Current-detection amplifier Output 2 - - push-pull

53 AMP2N IN Current-detection amplifier input 2 (-) - - -

54 AMP2P IN Current-detection amplifier input 2 (+) - - -

55 VCC_OP Power supply The power supply for Current-detection amplifier (5V/3.3V) - - -

56 AMP1O OUT Current-detection amplifier Output 1 - - push-pull

57 AMP1N IN Current-detection amplifier input 1 (-) - - -

58 AMP1P IN Current-detection amplifier input 1 (+) - - -

59 AGND2 GND The ground 2 for analog circuits - - -

60 NDIAG OUT Error Output Pin - - push-pull

61 CLKOUT OUT Clock output - - push-pull

62 ALARM2 IN Pre-driver enable 2 Pull-Down 50kΩ -

63 TEST IN Test terminal Pull-Down 50kΩ -

64 ALARM1 IN Pre-driver enable 1 Pull-Down 50kΩ -

2019-02-27 6 ©2015-2019 Toshiba Electronic Devices & Storage Corporation

• Description of an internal signal name <Usage power supply/GND list> Internal signal name Description State H L abst_pass Normal signal of ABIST ABIST normal ABIST abnormal abst_end End signal of ABIST ABIST end ABIST unfinished gate_en_u Pre-driver output enabling signal (U phase) Enable Disable gate_en_v Pre-driver output enabling signal (V phase) Enable Disable gate_en_w Pre-driver output enabling signal (W phase) Enable Disable gate_en_r Pre-driver output enabling signal (relay) Enable Disable gate_off_u Error output signal (Pre-driver output enabling, U phase) Enable Disable gate_off_v Error output signal (Pre-driver output enabling, V phase) Enable Disable gate_off_w Error output signal (Pre-driver output enabling, W phase) Enable Disable gate_off_r Error output signal (Pre-driver output enabling, relay) Enable Disable cp_en Enabling signal for charge pump circuit Enable Disable cp_off Error output signal (charge pump circuit enabling) Enable Disable vbl1 VB1/VB2 under voltage detection signal 1 Detection Release vbl2 VB1/VB2 under voltage detection signal 2 Detection Release vcl1 VCC1/VCC2 under voltage detection signal 1 Detection Release vcl2 VCC1/VCC2 under voltage detection signal 2 Detection Release por_x Internal reset signal Reset release Reset vch VCC1/VCC2 over voltage detection signal Detection Release vphh VCPH clamp voltage detection signal Detection Release tsd1det Over temperature detection signal1 Detection Release tsd2det Over temperature detection signal2 Detection Release tsd3det Over temperature detection signal3 Detection Release shuho Short-circuit detection signal (U phase low side) Detection Release shvho Short-circuit detection signal (V phase low side) Detection Release shwho Short-circuit detection signal (W phase low side) Detection Release shulo Short-circuit detection signal (U phase high side) Detection Release shvlo Short-circuit detection signal (V phase high side) Detection Release shwlo Short-circuit detection signal (W phase high side) Detection Release Symbol Pin name Function/Application Vb VB1,VB2 Battery power supply Vcc VCC1,VCC2 External 5V/3.3V power supply Vccop VCC_OP The power supply for current detection amplifier (5V/3.3V) Vcph VCPH Charge pump voltage (for high sides) Vcpl VCPL Charge pump voltage (for low sides) AGND AGND1,AGND2 GND for analog circuitry PGND PGND1,PGND2,PGND3 Power GND

2019-02-27 7 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Divider Charge Pump1 Vb CP1H CP1L VCPL Charge Pump2 VCPH CP2H CP2L Clamp （16V） Pre-drv. （Low-side） Pre-drv. （High-side） Control Circuit Vb Vb EN_CP 50kΩ Vcc SR1 SR3 SR2 (vphh) Vcc Logic Vcc Vcc Vb (por_x） CP_SW (por_x） (cp_en） Error Logic (cp_off） VB+12V detector 36V detector Vcc Vcc Vcc Vcc Vcc Vcc (por_x） (por_x） (por_x） (por_x） (por_x） Functional descriptions (1) Charge pump circuit TB9081FG build in Charge pump for Pre-Drivers and it can control external Nch MOSFETs directly. Two charge pump voltages the object for the high side drive of a motor and the object for the relay drive of a motor, and for the low side drive of a motor is generated. The charge pump voltage (Vcph) for a high side drive and a relay drive control by an internal circuit, and if Vcph goes up to Vb+12V (Typ.), a charge pump will suspend operation. Furthermore, in consideration of an overvoltage state, if V cph goes up to 37V (Typ.), a charge pump will stop, and if V cph is less than 36.5V (Typ.), a charge pump will resume operation. The charge pump voltage (V cpl) for a low s ide drive is generated from V cph. If V cpl goes up to 16V (Typ.), a clamp will start and it will not become the voltage more than clamp voltage. It is possible to build the switching circuit (CP_SW) in the V b side of a charge pump circuit, to make a transistor turn off by CP_SW, and to stop the supply to Vcph from Vb. Vcc voltage turns off the transistor of CP_SW on condition of the c onditions as for which below V cc voltage detection voltage becomes, or EN_CP=L. For details, please refer to a (7) EN_CP circuit. Moreover, it is possible to operate or stop a charge pump by terminal EN_CP. The charge pump operates at the time of EN_CP="H", and it stops at the time of EN_CP="L" and also suspends the supply to Vcph from Vb . A Vcph output voltage is set to 0V at the time of the charge-pump stop by EN_CP="L." When the charge pump is stopped by the control in the IC, V cph output voltage will become the "Vb-3VF". Fig.1- a Charge pump circuit Block Diagram Ccp=0.1μF Ccp=0.1μF Cvcph1=10μF Cvcpｌ1=4.7μF Cvcph2=0.1μF Cvcpｌ2=0.1μF Rcp=15Ω Rcp=15Ω

2019-02-27 8 ©2015-2019 Toshiba Electronic Devices & Storage Corporation (2) Pre -drivers TB9081FG has the pre-driver circuit it is for the motor relay drive, for the power relay drive, for the low-side drive of the motor and for the high- side drive of the motor. Each pre-driver circuit has a respective input and output terminals are controlled by a signal inputted to the input terminals. Fig.2- a Pre-driver circuit Block Diagram HUI Battery HVI HWI BR1I BR2I RUI RVI RWI LUI LVI LWI HUO BR1O BR2O HVO HWO RUO RVO RWO LUO LVO LWO 1kΩ 1kΩ 1kΩ 1kΩ 1kΩ (gate_en_w) 50kΩ Vcc 50kΩ Vcc 50kΩ Vcc 50kΩ Vcc 50kΩ Vcc 50kΩ Vcc 50kΩ Vcc 50kΩ Vcc 50kΩ Vcc 50kΩ Vcc 50kΩ Vcc Vcph Vcpl M 10kΩ 10kΩ 10kΩ 10kΩ 10kΩ Pre-drv. logic Vcc (gate_en_r) (gate_en_v) (gate_en_u) output current switching time control logic Vcc （por_x） (clk4m)

2019-02-27 9 ©2015-2019 Toshiba Electronic Devices & Storage Corporation <A power supply relay drive circuit, a motor relay drive circuit> A power supply relay drive circuit is a circuit which controls FET for a relay on the battery power -supply side. A motor relay drive circuit is a circuit which controls FET for a relay on the motor side. A truth table is shown in table 2- a and 2- b. Refer to the (6) ALARM input circuit for the details of the internal signal (gate_en_r) in a truth table. Moreover, resistance 1kΩ is built in the output of a power supply relay drive and a motor relay drive. Furthermore, the diode for prevention of backflow at the time of reverse connection is built in the output of a power supply relay drive circuit. - Table 2- a Input/output truth table 1 (power supply relay drive circuit) - Power supply relay drive circuit 1 Input Internal signal Output Notes BR1I (gate_en_r) BR1O L H L - H H H - * L L - *:Don't care - Power supply relay drive circuit 2 Input Internal signal Output Notes BR2I (gate_en_r) BR2O L H L - H H H - * L L - *:Don't care - Table 2- b Input/output truth table 2 (motor relay drive circuit) - Motor relay drive circuit 1 (U phase) Input Internal signal Output Notes RUI (gate_en_r) RUO L H L - H H H - * L L - *:Don't care - Motor relay drive circuit 2 (V phase) Input Internal signal Output Notes RVI (gate_en_r) RVO L H L - H H H - * L L - *:Don't care - Motor relay drive circuit 3 (W phase) Input Internal signal Output Notes RWI (gate_en_r) RWO L H L - H H H - * L L - *:Don't care

2019-02-27 10 ©2015-2019 Toshiba Electronic Devices & Storage Corporation <A high side drive circuit, a low side drive circuit> A high side drive circuit is a circuit which drives FET of the high side of a motor. A low side drive circuit is a circuit which drives FET of the low side of a motor. A high side drive circuit and a low side drive circuit built in each 3ch. An input signal (HUI/HVI/HWI, LUI/LVI/LWI) is changed by a control block, and output (HUO/HVO/HWO, LUO/LVO/LWO) is outputted. A truth table is shown in table 2- c. Refer to the (6) ALARM input circuit for the details of the internal signal (gate_en_u, gate_en_v, gate_en_w) in a truth table. When HUI/LUI, HVI/LVI, and HWI/LWI are H/H, an output will be L/L (prohibition input). The operation at the time of prohibition input detection can be set up through a SPI communication. Moreover, the current at the time of Turn on/Turn off of a high side drive circuit and a low side drive circuit is the current limit after 8 μs (typ.). This current -limiting time can be set up a 3 value or no limit time through a SPI communication. When gate_en_u, gate_en_v, and gate_en_w switch from “H” to “L” by the failure detection and ALARM1 or ALARM2 output ting low, and then, the high side drive circuit and the low side drive circuit output high, it switches to “L”. At this time, it has an output current capability which is decided by the ON resistance and the gate resistance of the output driver during the current limit time. However, only Vcc under voltage detection, the output current capability will be the output limit current Iolmtl even within the current limit time. - Table 2- c Input/output truth table 3 (a high side drive circuit, a low side drive c ircuit) - FET drive circuit 1 (U phase) Input Internal signal Output Notes HUI LUI (gate_en_u) HUO LUO L L H L L - L H H L H - H L H H L - H H H L L Inhibit input mode * * L L L - *: Don’t care - FET drive circuit 2 (V phase) Input Internal signal Output Notes HVI LVI (gate_en_v) HVO LVO L L H L L - L H H L H - H L H H L - H H H L L Inhibit input mode * * L L L - *: Don’t care - FET drive circuit 3 (W phase) Input Internal signal Output Notes HWI LW I (gate_en_w) HWO LW O L L H L L - L H H L H - H L H H L - H H H L L Inhibit input mode * * L L L - *: Don’t care

2019-02-27 11 ©2015-2019 Toshiba Electronic Devices & Storage Corporation (3) Current detector TB9081FG are built three amplifiers for motor -current detection and one amplifier for reference voltage generation (Fig3- a). The amplifiers for motor-current detection can amplify the difference voltage which produces according to the current which flows through the shunt resistance connected to the motor actuator. The amplifier for reference voltage generation is used as buffer amplifier for reference voltage generation. As an external configuration of the current detection, it is available in either 1 shunt configuration or 3 shunt configuration. Fig.3- a Motor-current detection circuit Block Diagram AMP1O AMP1N AMP1P Vccop AMP2O AMP2N AMP2P Vccop AMP3O AMP3N AMP3P Vccop VRO VRI Vccop (vbg1) (vbg1) (vbg1) (vbg1)

2019-02-27 12 ©2015-2019 Toshiba Electronic Devices & Storage Corporation (4) Oscillator /divider The oscillator has composition with built -in CR, and an Oscillation frequency is Fc=4MHz (typ.). An oscillator will start operation after internal signal (por_x) release. 4 MHz (clk4m) is used as the system clock of a logic circuit, and an operation clock of the digital filter of the short-circuit detector of external FET. Clock 1MHz (clk1m), it is used as an operation clock of the digital filter of an ALARM detector. Clock 500kHz (clk500k), it is used as an operation clock of a charge pump. Clock 16kHz (clk16k), it is used as an operation clock of ABIST. CLKOUT output (terminal) will output a clock set by the SPI (clk4m, clk500k, clk16k). Fig.4- a Oscillator, divider Block Diagram <Timing chart of divider> Fig.4-b Timing chart of divider Divider (clk16k) OSC Vcc CLKOUTmux ALARM filter ABIST control FET Short filter SPI communication circuit (clk500k) Charge Pump Logic Vcc Low voltage monitoring VCC1 VCC2 （por_x） （vcl1） 100Ω （vcl2） (clk4m) (clk1m) output current switching time control (clk4m) Vcc （clk16k） （clk4m） (vcl1） (por_x） (vcl2） （clk1m） （clk500k）

2019-02-27 13 ©2015-2019 Toshiba Electronic Devices & Storage Corporation (5) Abnormal detection circuit TB9081FG is built in miscellaneous abnormal detection circuit , such as the under voltage detection (VB1, VB2, VCC1, VCC2), over voltage detection (VCC1, VCC2), over temperature detection, external FET short-circuit detection and frequency abnormal detection. The contents of a monitoring function list and the internal signal are shown below. The details of operation are indicated in (5-1) and after. When failure detection turns off the pre- driver circuit, the short -circuit detection function becomes invalid. When the operation returns from the abnormalities after that and the operation of a pre- driver circuit returns, a short-circuit detection function becomes effective again.

• Monitoring function list Monitoring function SPI Setup Setup bit Operation in detection *Note 1 *Note 5 Initial value ABIST Register writing NDIAG * Note 2 * Note 4 VB1/VB2 Under voltage Valid 00 pre-driver circuit OFF - - ○ L hold 01 pre-driver circuit OFF ○ ○ L 1* pre-driver circuit OFF - ○ H VCC1/VCC2 Under voltage Invalid - Pre-driver / charge pump / dividing circuit OFF - - - L VCC1/VCC2 Over voltage Valid 00 Pre-driver / charge pump circuit continued operation - ○ ○ L hold

01 Pre-driver circuit OFF ○

10 Pre-driver / charge pump circuit OFF -

11 pre-driver / charge pump circuit OFF-hold - Over temperature Valid 00 Pre-driver / charge pump circuit continued operation - ○ ○ L hold 01 pre-driver circuit OFF - 10 pre-driver / charge pump circuit OFF ○ 11 pre-driver / charge pump circuit OFF-hold - External FET Short-circuit Valid 000 Pre-driver / charge pump circuit continued operation - - ○ L hold

001 Pre-driver-circuit(only detection phase ) OFF -

010 Pre-driver ci rcuit (only detection phase)

011 Pre-driver circuit (all phases) OFF -

100 Pre-driver circuit (all phases) OFF-hold -

101 Pre-driver (all phases) / charge pump circuit

110 Pre-driver (all phases) / charge pump circuit

111 No detection - - H

Valid 000 Pre-driver / charge pump circuit continued operation - ○ (Low frequency) ○ L hold

001 Pre-driver circuit OFF -

010 Pre-driver / charge pump circuit OFF -

011 Pre-driver / charge pump OFF-hold -

1** No detection ○ - H Pre-driver prohibition input detection *Note 3 Valid 0 Pre-driver OFF, when inputting inhibit signals. charge pump circuit continued operation ○ - - H

1 Pre-driver OFF, when input ting inhibit

signals. charge pump circuit continued operation - ○ L hold SPI communication error Invalid - Pre-driver / charge pump circuit continued operation - - ○ L hold *:don't care

2019-02-27 14 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Note 1) It describes about Pre-driver, charge pump and divider. The definition of OFF and OFF-hold is as follows. OFF: the operation after returning from an abnormal state is possible. OFF-hold: Hold OFF even after returning from an abnormal state. Note 2) It describes about NDIAG operation in detection. The \L hold\ hold the output NDIAG=L even after releasing from the abnormal detection. Note 3) If register setting=0, there is no register writing and NDIAG becomes H, even in case of the abnormal detection. If register setting=1, it has register writing and NDIAG becomes L, in case of the abnormal detection. Note 4) if set to other than \L hold\ in NDIAG, register will be cleared and NDIAG=H by recovering from the abnormal detection, Note 5) Both Pre-driver circuit (all phases) OFF and Pre-driver circuit OFF turn off power relay and motor relay Pre-driver. Pre-driver-circuit(only detection phase) OFF turns off the high side and the low side Pre-driver of detected phase only.

2019-02-27 15 ©2015-2019 Toshiba Electronic Devices & Storage Corporation (5-1) VB1/VB2 under voltage detection Under voltage detection of VB1/VB2 is performed. Two detection comparators and two filters are built in. If at least one filter outputs “H”, under voltage detection is performed. The band gap voltage recognized as the reference of a detection comparator is generated from a separate band gap circuit (BG1 and BG2). Fig.5-1a VB1/VB2 under voltage detection Block Diagram NDIAG Pre-Dr. VB1 (vbl1) /CS SCK SDIN SDOUT BG1 Logic vbg1 Vcc Vcc VB2 ＋ (vbl2)vbg2 Vcc BG2 Error Logic under voltage monitoring2 SPI communication circuit under voltage monitoring1 Vcc Vcc (clk4m) Filter Filter

2019-02-27 16 ©2015-2019 Toshiba Electronic Devices & Storage Corporation ➣ A-(1) Under voltage of Vb If VB1 voltage and VB2 voltage are less than the threshold value of the under voltage detection voltage (vthbll), L detection comparator of Vb outputs “H”. ➣ A-(2) Under voltage detection of Vb After the detection filter time (Tbl), Vb under voltage detection signal (vbl1 and vbl2) outputs high, the under voltage state is detected, and the pre- driver circuit is turned off . The oscillating circuit and the charge pump circuit are not turned off. The pre-driver circuit holds OFF until the under voltage is released. The NDIAG output state after detection can be chosen among the 3 modes through SPI communication. A setup does not become effective even i f the mode is changed in Vb under voltage detection state. The setup becomes effective after Vb under voltage is released and the register (uvb) is cleared. ➣ A-(3) Return of Vb voltage (under voltage release) If VB1 voltage and VB2 voltage exceed vthblh, Vb under voltage detection signal (vbl1 and vbl2) outputs low, the under voltage state is releas ed, and the pre- driver circuit recovers to the normal operation. In case NDIAG outputs low, it outputs high when the register (uvb) is cleared through SPI communication. During under voltage detection, NDIAG outputs low because the register (uvb) is not cleared. Fig.5-1b Timing chart of VB1/VB2 under voltage detection (1) (2) (3) control by input signal control by input signal control by input signal NDIAG H*O/ L*O VCPL VCPH Tbl register uvb_op = “00” register uvb_op = “01” （initial value） register uvb_op = “1*” Pre-driver OFF NDIAG：no L output Pre-driver：OFF NDIAG：L output Pre-driver：OFF Pre-driver OFF NDIAG：L hold Pre-driver：OFF Vthbll under voltage detection under voltage release Vthblh L hold VB1 VB2 vbl2 Tbl Vthbll Vthblh Tbl Vthbll Vthblh control by input signal Pre-driver OFF Tblvbl1 Tbl Tbl under voltage detection under voltage detection under voltage release under voltage release

2019-02-27 17 ©2015-2019 Toshiba Electronic Devices & Storage Corporation (5-2) VCC1/VCC2 under voltage detection Under voltage detection of VCC1/VCC2 is performed. Two detection comparators are built in. If at least one comparator outputs “H”, under voltage detection is performed. The band gap voltage recognized as the reference of a detection comparator is generated from a separate band gap circuit (BG1 and BG2). Fig.5-2a VCC1/VCC2 under voltage detection Block Diagram NDIAG Pre-Dr. VCC1 CP1 CP2 (vcl1) (vch) /CS SCK SDIN SDOUT BG1 Logic vbg1 Vcc Vcc VccVCC2 (vcl2)vbg2 Vcc BG2 (gate_en_u,v,w,r) (cp_en) Error Logic under voltage monitoring2 SPI communication circuit over voltage monitoring under voltage monitoring1 Vcc Vcc Filter (clk4m) （por_x）

2019-02-27 18 ©2015-2019 Toshiba Electronic Devices & Storage Corporation ➣ B-(1) Under voltage of Vcc VCC1 voltage and VCC2 voltage are less than the threshold value of the under voltage detection voltage (vthcll). ➣ B-(2) Under voltage detection of Vcc After the response relaxation time (Tcl), Vcc under voltage detection signal (vcl1 and vcl2) outputs high, the under voltage state is detected, por_x outputs low, and NDIAG outputs low. Then, the pre- driver circuit, the charge pump, and the oscillating circuit are turned off. Each circuit holds OFF until the under voltage is released. ➣ B-(3) Return of Vcc voltage (under voltage release) If VCC1 voltage and VCC2 voltage exceed vthclh, Vcc under voltage detection signal (vcl1 and vcl2) outputs low, and the under voltage state is released. ➣ B-(4) Recover of normal operation After LBIST and ABIST are performed, the normal operation recovers in case the judgment of BIST “OK”. The charge pump circuit starts operation and the pre- driver circuit is turned on. In case the judgment of BIST “NG”, the charge pump circuit and the pre-driver circuit do not operate. NDIAG outputs high in the judgment of “OK”, and low in the judgment of “NG”. Fig.5-2b Timing chart of VCC1/VCC2 under voltage detection * When Vcc is lower than the detection voltage of Vcc under voltage further, IC will be the stand-by state. In the stand-by state, functions other than Vcc under voltage detection are turned off. VCC1 VCC2 vcl1 NDIAG Vthcll H*O/ L*O clk4m VCPL VCPH Vthclh Tcl Oscillation start vcl2 Tcl control by input signal control by BIST result and input signal por_x LBIST control by BIST result ABIST control by BIST result Pre-driver OFF under voltage detection under voltage release Oscillator OFF Charge pump OFF (1) (2) (3) (4)

2019-02-27 19 ©2015-2019 Toshiba Electronic Devices & Storage Corporation (5-3) VCC1/VCC2 over voltage detection Over voltage detection of VCC1/VCC2 is performed. The detection comparator and the filter are built in. If the filter outputs high, over voltage detection is performed. Fig.5-3a VCC1/VCC2 over voltage detection Block Diagram NDIAG Pre-Dr. VCC1 CP1 CP2 (vcl1) (vch) /CS SCK SDIN SDOUT BG1 Logic vbg1 Vcc Vcc VccVCC2 (vcl2)vbg2 Vcc BG2 (gate_en_u,v,w,r) (cp_en) Error Logic under voltage monitoring2 SPI communication circuit over voltage monitoring under voltage monitoring1 Vcc Vcc Filter (clk4m) （por_x）

2019-02-27 20 ©2015-2019 Toshiba Electronic Devices & Storage Corporation ➣ C-(1) Vcc voltage rise If VCC1 voltage and VCC2 voltage exceed the threshold value of over voltage detection (vthchh), H detection comparator of Vcc outputs high. ➣ C-(2) Over voltage detection of Vcc After the detection filter time ( Tch), Vcc over voltage detection signal (vch) outputs high and NDIAG outputs low. The operation after detection can be chosen among 4 modes through SPI communication. A setup does not become effective even if the mode is changed in Vcc over voltage detection state. The setup becomes effective after Vcc over voltage is released and the register (ovc) is cleared. ➣C-(3) Return of Vcc voltage (over voltage release) If VCC1 voltage and VCC2 voltage are less than vthchl, Vcc over voltage detection signal (vch) outputs low and the over voltage is released. In the case of register ovc_op is 11, even if the over voltage is released, each circuit continues OFF and NDIAG keeps outputting low. When the register ( ovc_op) is 00, 01, and 10, each circuit operates normally and NDIAG keeps outputting low. When the register (ovc) is cleared through SPI communication, each circuit operates normally and NDIAG outputs high. During over voltage detection, the register (ovc) is not cleared and NDIAG outputs low. Fig.5-3b Timing chart of VCC1/VCC2 over voltage detection (1) (3) (2) control by input signal control by input signal control by input signal VCC1 VCC2 vch NDIAG H*O/ L*O VCPL VCPH Tch register ovc_op = “00” register ovc_op = “01” （initial value） register ovc_op = “10” register ovc_op = “11” Tch NDIAG：L hold NDIAG：L hold Pre-driver：OFF Tch NDIAG：L hold Pre-driver：OFF Charge pump：OFF Tch NDIAG：L hold Pre-driver：OFF-hold Charge pump：OFF-hold L hold Vthchh Vthchl Vthchh Vthchl Vthchh Vthchl Vthchh Vthchl L holdL holdL hold Pre-driver OFF high voltage detection high voltage detection high voltage detection high voltage detection high voltage release high voltage release high voltage release high voltage release Pre-driver OFF Pre-driver OFF-hold Charge pump OFF Charge pump OFF-hold

2019-02-27 21 ©2015-2019 Toshiba Electronic Devices & Storage Corporation (5-4) Over temperature detection Three over temperature detection comparators are built in. Three detection comparators and three filters are built in. If at least one filter outputs high, the over temperature detection becomes effective. The band gap voltage recognized as the reference of a detection comparator is generated from two band gap circuits (BG1 and BG2). When chip temperature exceeds 170°C , the comparator switches and the over temperature is detected. The operation after detecti on can be chosen among 4 modes through SPI communication. When IC internal temperature becomes 160°C or less, the over temperature detection is released. Fig.5-4a Over temperature detection Block Diagram NDIAG /CS SCK SDIN SDOUT Logic Vcc 2VF AGND VccVcc 2VF AGND VccVcc AGND Vcc 2VF Vcc BG1 vbg1 BG2 vbg2 Pre-Dr. CP1 CP2 (gate_en_u,v,w,r) (cp_en) Error Logic SPI communication circuit (tsd2det) (tsd3det) (tsd1det) Vcc Vcc Filter (clk4m) Filter Filter （por_x）

2019-02-27 22 ©2015-2019 Toshiba Electronic Devices & Storage Corporation ➣ D-(1) Over temperature detection If the temperature exceeds Tsdh, after the detection filter time (Ttsd), the over temperature detection signal (tsd1 to 3det) outputs high, and the over temperature is detected. The operation after detection can be chosen among 4 modes through SPI communication. A setup does not become effective even if the mode is changed during over temperature state. The setup becomes effective when the over temperature state is released and the register (tsd*det) is cleared. ➣ D-(2) Release of over temperature detection If temperature is less than Tsdl, the over temperature detection signal (tsd1 to 3det) outputs low, and the over temperature detection is released. When register (tsd_op) is 11, even if the over temperature detection is released, each circuit continues OFF and NDIAG leeps outputting low. When the register (tsd_op) is 00, 01, and 10, each circuit operates normally. However, NDIAG holds low. When the register (tsd*det ) is cleared through SPI communication, each circuit operates normally and NDIAG outputs high. During over temperature detection, the register (tsd*det) is not cleared and NDIAG outputs low. Fig.5-4b Timing chart of over temperature detection (1) (2) NDIAG：L hold NDIAG：L hold Pre-driver：OFF NDIAG：L hold Pre-driver：OFF Charge pump：OFF NDIAG：L hold Pre-driver：OFF-hold Charge pump：OFF-hold tsd*det control by input signal control by input signal control by input signal temp NDIAG Tsdh H*O/ L*O VCPL VCPH register tsd_op = “00” register tsd_op = “01” register tsd_op = “10” （initial value） register tsd_op = “11” Tsdl Tsdh Tsdl Tsdh Tsdl Tsdh Tsdl L holdL holdL holdL hold Ttsd Ttsd Ttsd Ttsd over temperature detection over temperature release over temperature detection over temperature release over temperature detection over temperature release over temperature detection over temperature release Pre-driver OFF Pre-driver OFF Pre-driver OFF-hold Charge pump OFF Charge pump OFF-hold

2019-02-27 23 ©2015-2019 Toshiba Electronic Devices & Storage Corporation (5-5) Short-circuit detection Short-circuit of external MOSFET is detected by monitoring the dorain terminal and the source terminal of the external MOSFET. When short -circuit is detected, the operation after detection can be chosen among 8 modes through SPI communication. Moreover, detection threshold voltage and detection time can be set from four values through SPI communication. At the time of short-circuit detection release, in case that the register (sh_op) is 010, 100, and 110, even if short -circuit detection is released, each circuit continues OFF and NDIAG holds L. When the register (tsd_op) is 000, 001, 011, and 101, each circuit operates normally, but NDIAG holds L. When the register (sc**) is cleared through SPI communication, each circuit operates normally and NDIAG outputs high. Fig.5-5a Short-circuit detection Block Diagram

• Table5-5a Short-circuit detection state Comparator input Comparator output Input signal Abnormal condition SHU > LREF shul = H LUI = H External MOSFET short-circuit of HUO SHV > LREF shvl = H LVI = H External MOSFET short-circuit of HVO SHW > LREF shwl = H LW I = H External MOSFET short-circuit of HWO SHU < HREF shuh = H HUI = H External MOSFET short-circuit of LUO SHV < HREF shvh = H HVI = H External MOSFET short-circuit of LVO SHW < HREF shwh = H HWI = H External MOSFET short-circuit of LWO * HREF = HS- Vthh_sh (detection threshold voltage of the H igh side), LREF = Vthl_sh (detection threshold voltage of the Low side) * The detection threshold voltage of the High side is specified between HS and SH* of the IC terminal. Please set up the threshold value of HREF in consideration of the generating voltage by external resistance of HS terminal and SH* terminal, and the voltage between drain and source of MOSFET of the High side. * The detection threshold voltage of the Low side is specified between SH* and PGND(s) of the IC terminal.Please set up the threshold value of LREF in consideration of the generating voltage by external resistance of SH* terminal, the generating voltage by the shunt resistance for current detection, and the voltage between drain and source of MOSFET of the Low side. HUO HVO HWO LUO LVO LWO HS GND SHW SHV SHU- Error Logic Threshold setting Filter (shuh) (shvh) (shwh) (shul) (shvl) (shwl) Pre-drv. input circuit (shwlo) (shuho) (shvho) (shwho) (shulo) (shvlo) HREF LREF vthl_sh vthh_sh (clk4m) M SPI communication circuit Threshold setting NDIAG Logic Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Filter Filter Filter Filter Filter (gate_en_r) (gate_en_v) (gate_en_w) (gate_en_u) （por_x） Pre-drv. logic Pre-Drv. (Relay)

2019-02-27 24 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Fig.5-5b Timing chart of short-circuit detection (Register (sh_op) = ”000”) SH* NDIAG H*O VCPL VCPH register sh_op = “000” NDIAG：L hold Hi-side short-circuit det ection Tsf L*O Tsf H*I L*I Tsf SH* NDIAG H*O VCPL VCPH short-circuit release Lo-side short-circuit occured Tsf L*O Tsf H*I L*I L holdL hold sh*hsh*h sh*lsh*l Lo-side short-circuit det ection sh*hosh*ho sh*losh*lo short-circuit release

2019-02-27 25 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Fig.5-5c Timing chart of short-circuit detection (Register ( sh_op) = ”001” and ”011”) * "001" : Pre-driver OFF in only a detection phase. "011": Pre-driver OFF in all phase register sh_op = “001”, ”011” Pre-drv OFF Pre-drv OFF Pre-drv OFF SH* NDIAG H*O VCPL VCPH L*O H*I L*I Pre-drv OFF Pre-drv OFF SH* NDIAG H*O VCPL VCPH L*O H*I L*I L holdL hold sh*hsh*h sh*lsh*l Tsf TsfTsf Tsf Tsf sh*hosh*ho sh*losh*lo Hi-side short-circuit det ection short-circuit release Lo-side short-circuit occured Lo-side short-circuit det ection short-circuit release NDIAG：L hold Pre-driver：OFF

2019-02-27 26 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Fig.5-5d Timing chart of short-circuit detection (Register (sh_op) = ”010” and ”100”) *”010”: Pre-driver OFF in only a detection phase ”100”: Pre-driver OFF in all phase register sh_op = “010”(initial value), ”100” Pre-drv OFF-hold SH* NDIAG H*O VCPL VCPH L*O H*I L*I Pre-drv OFF-hold SH* NDIAG H*O VCPL VCPH L*O H*I L*I L holdL hold sh*hsh*h sh*lsh*l Tsf TsfTsf Tsf Tsf sh*hosh*ho sh*losh*lo Pre-drv OFF-hold Pre-drv OFF-hold Hi-side short-circuit det ection short-circuit release Lo-side short-circuit occured Lo-side short-circuit det ection short-circuit release NDIAG：L hold Pre-driver：OFF-hold

2019-02-27 27 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Fig.5-5e Timing chart of short-circuit detection (Register (sh_op) = ”101”) register sh_op = “101” Charge pump OFF Charge pump OFF Pre-drv OFF Pre-drv OFF Pre-drv OFF Charge pump OFF SH* NDIAG H*O VCPL VCPH L*O H*I L*I Charge pump OFF Pre-drv OFF Pre-drv OFF Charge pump OFF SH* NDIAG H*O VCPL VCPH L*O H*I L*I L holdL hold sh*hsh*h sh*lsh*l Tsf TsfTsf Tsf Tsf sh*hosh*ho sh*losh*lo Hi-side short-circuit det ection short-circuit release Lo-side short-circuit occured Lo-side short-circuit det ection short-circuit release NDIAG：L hold Pre-driver：OFF Charge pump：OFF

2019-02-27 28 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Fig.5-5f Timing chart of short-circuit detection (Register (sh_op) = ”110”) register sh_op = “110” Pre-drv OFF-hold Pre-drv OFF-hold Charge pump OFF-hold SH* NDIAG H*O VCPL VCPH L*O H*I L*I Pre-drv OFF-hold Pre-drv OFF-hold Charge pump OFF-hold SH* NDIAG H*O VCPL VCPH L*O H*I L*I L holdL hold sh*hsh*h sh*lsh*l Tsf TsfTsf Tsf Tsf sh*hosh*ho sh*losh*lo Hi-side short-circuit det ection short-circuit release Lo-side short-circuit occured Lo-side short-circuit det ection short-circuit release NDIAG：L hold Pre-driver：OFF-hold Charge pump：OFF-hold

2019-02-27 29 ©2015-2019 Toshiba Electronic Devices & Storage Corporation (5-6) O scillating frequency monitoring It detects the abnormality in frequency when oscillating frequency is low and high. The low frequency detection circuit of oscillating frequency resets the input of a comparator for every clk1m. If the frequency becomes low and reset is overdue, the output of a comparator is reversed and the abnormality in frequency is detected at the rising edge of the following clk1m. In the high frequency detection circuit of the oscillating frequency, a comparator repeats H/L output for every clk 1m. When oscillating frequency becomes high, a det ection comparator continues outputting H, and the detection comparator continues outputting H at the falling edge of 1st count of clk1m, the abnormality in high frequency is detected. The operation in failure detection can be chosen among 5 modes through SPI communication. A setup does not become effective even if the mode is changed in the frequency failure detection state. The setup becomes effective after the abnormality in frequency are releas ed and the register (err_of and err_uf) is cleared. Abnormality of frequency is not detected in case that the register (ferr_op) is 1**. When frequency failure detection is released, in case that the register (ferr_op) is 011, even if frequency failure detection is released, each circuit continues OFF and NDIAG holds L. In case that the register (ferr_op) is 000, 001, and 010, each circuit recovers to the normal operation. However, NDIAG holds L. When the register (err_of and err_uf) is cleared through SPI communication, each circuit recovers to the normal operation and NDIAG outputs high. Fig.5-6a Frequency monitoring circuit Vcc (vbg2) Vcc (clk1m) Cwdl (clkslow) Vcc (vbg2) (clkf ast) (fsin) Vcc Cwdh (ffin) NDIAG /CS SCK SDIN SDOUT Logic Vcc Pre-Dr. CP1 CP2 (cp_en) Error Logic SPI communication circuit Abnormal detection circuit (fso_x) Abnormal detection circuit (ffo_x) High frequency monitoring Low frequency monitoring （por_x） （por_x） （por_x） Vcc Vcc (gate_en_u,v,w,r)

2019-02-27 30 ©2015-2019 Toshiba Electronic Devices & Storage Corporation （clk1m） NDIAG （ffin） （clkf ast） （ffo_x） clk1m：1カウント目の 立下りエッジで検出 Fig.5-6b Timing chart of frequency monitoring (Low frequency) Fig.5-6c Timing chart of frequency monitoring (High frequency) （clk1m） （fsin） （fso_x） NDIAG （clkslow） detect at the rising edge of 1st count of clk1m detect at the falling edge of 1st count of clk 1m

2019-02-27 31 ©2015-2019 Toshiba Electronic Devices & Storage Corporation (6) ALARM input circuit As an input terminal of an ALARM signal, TB9081FG have two terminals of ALARM1 and ALARM2. An ALARM signal controls Enable/Disable of the Pre- drivers (a FET drive circuit, a motor relay drive circuit, a power supply relay drive circuit). In the case of ALARM1= "L" or ALARM2= "L", the Pre- drivers will be Disable. In the case of ALARM1="H" and ALARM2="H", Enable/Disable is decided by the input and internal signal of each Pre-drivers. Also, the input side of the ALARM1 and ALARM2 terminal has a built -in digital filter (D .F.) for noise removal. Digital filter time can be set through the SPI communication. If ALARM1=“L” or ALARM2=“L” is detected, the short-circuit detection function is enabled. Fig.6-a FET drive circuit control Block Diagram Table 6-a FET drive circuit control truth table Input signal Internal input signal Internal control signal FETdrive circuit ALARM1 ALARM2 (por_x) (gate_off_u) (gate_off_v) (gate_off_w) (gate_off_r) (gate_en_u) (gate_en_v) (gate_en_w) (gate_en_r) H H H L - - - L - - - U phase Disable H H H H - - - H - - - U phase Enable H H H - L - - - L - - V phase Disable H H H - H - - - H - - V phase Enable H H H - - L - - - L - W phase Disable H H H - - H - - - H - W phase Enable H H H - - - L - - - L Relay Disable H H H - - - H - - - H Relay Enable (Note 1) “*”: Don’t care (Note 2) Although " -":gate_off_* and gate_en_* have logic dependence in phase, the logic dependence to other phase is nothing. 50kΩ ALARM2 Vcc (por_x） D.F. (clk1m） Error Logic (gate_off_u） 50kΩ ALARM1 LogicVcc (gate_en_u） Vcc D.F. Pre-Dr. U phase H-side/L-side (alm1） (alm2） (gate_off_v） (gate_off_w） (gate_off_r） (gate_en_v） Pre-Dr. V phase H-side/L-side (gate_en_w） Pre-Dr. W phase H-side/L-side (gate_en_r） Pre-Dr. Relay

2019-02-27 32 ©2015-2019 Toshiba Electronic Devices & Storage Corporation (7) EN_CP input circuit EN_CP signal controls Enable/Disable of a charge pump circuit. In the case of input signal EN_CP= "L", the charge pump circuit will be Disable. In the case of EN_CP="H", Enable/Disable of the charge pump circuit is decided by an internal signal. Also, the charge pump SW circuit (CP_SW) will be Disable in case of input signal EN_CP = "L" or the internal signal (por_x) = "L". In the case of EN_CP = (por_x) = "H", it will be Enable. Fig.7-a EN_CP input circuit Block Diagram Table 7-a Charge-pump-circuit control truth table Input signal Internal input signal Internal control signal Charge pump circuit Charge pump SW circuit EN_CP (por_x) (cp_off) (cp_en) L * * L Disable Disable H L * L Disable Disable H H L L Disable Enable H H H H Enable Enable (Note) "*":Don't care 50kΩ Vcc EN_CP (cp_en） Error Logic (cp_off） Logic (por_x） CP1 CP2 Control Circuit Divider Vcc VCPH CP_SW (por_x） Vb CP1H CP2H Vcc

2019-02-27 33 ©2015-2019 Toshiba Electronic Devices & Storage Corporation (8) ABIST function At the time of IC starting, it is diagnosed whether miscellaneous abnormal detection is functioning normally. At the time of IC starting, a divider starts operation after VCC1/VCC2 under voltage release, and it starts diagnosis of ABIST after LBIST completion. Diagnosis of ABIST is performed even when a judgment of LBIST is NG. At the time of ABIST starting, the input voltage of the comparator is changed by the switch for diagnosis, and each detection comparator is reversed. Then, the diagnosis is performed. Diagnosis is performed in order synchronizing with a clock (clk16k), and diagnostic information is input to the ABIST judgment circuit. Also, NDIAG=L is kept during the diagnosis. After completion of all diagnosis, the IC switches to the normal operation. When the abnormal detection is not diagnosed, NDIAG will be H. When the abnormal detection is diagnosed, NDIAG will be L and keep the diagnosis information. A diagnostic part is as follows. VCC1/VCC2 over voltage detection, VCPH clamp voltage detection, over temperature detection, and frequency abnormal detection (low frequency side) Fig.8-a ABIST Block Diagram (VCC1/VCC2 over voltage detection) Table 8-a Circuit operation truth table (CP_SW circuit) Input signal CP_SW circuit EN_CP Before ABIST During ABIST ABIST OK ABIST NG L Disable Enable Disable Disable H Enable Enable Enable Enable Table 8-b Circuit operation truth table (charge pump circuit) Input signal Charge pump circuit EN_CP Before ABIST During ABIST ABIST OK ABIST NG L Disable Disable Disable Disable H Disable Disable Enable Disable Table 8-c Circuit operation truth table (pre-driver circuit) Input signal Pre-diver circuit ALARM1 ALARM2 Before ABIST During ABIST ABIST OK ABIST NG L * Disable Disable Disable Disable * L Disable Disable Disable Disable H H Disable Disable Enable Disable (Note)“*”: Don’t care NDIAG Divider Logic Vcc (clk16k) VCC1 BG1 vbg1 Vcc （abst_end）ABIST Control Error Logic SPI communication circuit (por_x） VCC2 (vch) over voltage monitoring （abst_pass） Normal operation Diagnosis operation

2019-02-27 34 ©2015-2019 Toshiba Electronic Devices & Storage Corporation <ABIST whole operation / startup operation> ➣ H-(1) IC startup At the time of IC starting, the divider is started the operation by the release of Vcc under voltage. ➣ H-(2) LBIST running The divider starts the operation and starts the LBIST. ➣ H-(3) ABIST start up The ABIST is started after the LBIST. The detection comparator is changed every 2clk of clk16k, and diagnosed whether the detection comparator is outputting the failure detection signal correctly. The comparator for an over temperature detection is diagnosed to the beginning. ➣ H-(4) Diagnosis Each comparator is diagnosed as follows. VCC1/VCC2 over voltage, VCPH cramp voltage, and a frequency monitoring (low frequency) ➣ H-(5) ABIST completion When all detection comparator diagnosis is completed, the IC switches to the normal operation mode, and the charge pump circuit starts the operation. Then the pre-driver can be ON. Also, the diagnosis result is output to the NDIAG. In the case of the diagnosis NG, the charge pump circuit and the pre-driver circuit are kept OFF. Fig.8-b ABIST timing chart *1 Regardless of EN_CP input signals , Vcph is equal to Vcpl=Vb -3VF (Vcpl<=16V) during running the ABIST. *2 There is no start order of VB1/2, and VCC1/2. The slew rate of Vb and Vcc should be use in the following range. Less than Vb=8V/μs Less than Vcc=0.3V/μs *3 When an abnormal detection of vphh is diagnosed, if Vb is lower than Vcc, maximum 10μA current flows in the cycle of 2clk of clk16k (125μs). *4 The running time of LBIST and ABIST is about 2.4ms (typ.). clkl vch tsd1det tsd3det NDIAG H*O/ L*O VCPL VCPH control by BIST result and input signal control by BIST result tsd2det VCC1 VCC2 VB1 VB2 clk16k vcl1 vcl2 Vthclh under voltage release abnormal state diagnosis normal state diagnosis vphh control by BIST result and EN_CP clk4m LBIST ABIST (1) (2) (3) (5) (4)

2019-02-27 35 ©2015-2019 Toshiba Electronic Devices & Storage Corporation (9) SPI Communication circuit The SPI communication circuit consists of an SPI core circuit and a register read circuit block. Only when /CS is L, communication with a microcomputer is attained. A microcomputer writes data in SDIN at the rising edge of a clock, and IC reads data at the following falling edges. Moreover, IC writes data in SDOUT at the rising edge of a clock, and a microcomputer reads data at the following falling edges. SDIN receives the data bit from a microcomputer in order from MSB to LSB. SDOUT transmits a data bit to a microcomputer in order from MSB to LSB. An output is push- pull composition and will be a Hi-Z at the time of /CS= "H". Moreover, inside IC, the /CS terminal have pull -up by resistance, and the SDIN and SCK terminal have pull-down by resistance. Fig.9-a SPI Communication circuit Block Diagram (9-1) SPI Communication operation When /CS is L, the serial data are transmitted or received synchronizing with the SCK. When /CS is H, the SDOUT output will be a high impedance. The data length is 40 bits. As a function, there are two kinds, the read operation and the write operation, and the write / read operation can be selected with "RW" bit. ”Dummy” bit does not influence the operations. <Write operation> The data structure of the write operation is shown in Fig.9-b. SDIN is consist of ”RW” bit, ”Address” bit, ”Dummy” bit (2 bits), ”Data” bit, ”CRC” bit, and ”Dummy” bit (16bits). ”RW” bit is the bit to select the write or the read operation, and when ”RW” bit=’1,’ the write operation is selected. ”Address” bit is the bit to specify the address , and ”Data” bit is the write data bit . Data of ”Data” bit is written to "Address" bit. ”CRC” bit is calculated by the micro controller, according to 16 bits of ”RW” bit, ”Address” bit, ”Dummy” bit (2bits), and “Data” bit. SDOUT is all ”Dummy” bit. In addition, perform the read operation after writing and confirm the correct data are written. Even if data are written to the empty bits, the data are not written. Fig.9-b Data structure of write operation /CS SDIN SDOUT SPI communication circuit SCK Logic Vcc SPI core circuit register read circuit register Vcc Vcc Vcc Vcc AGND （por_x） Vcc AGND AGND SDIN SDOUT SCK /CS RW Address (5bit) Data (8bit) CRC (8bit) Dummy（16bit） Dummy（40bit） Dummy (2bit)

2019-02-27 36 ©2015-2019 Toshiba Electronic Devices & Storage Corporation <Read operation> The data structure of the read operation is shown in Fig.9-c. SDIN is consist of ”RW” bit, ”Address” bit, ”Dummy” bit (10 bits), ”CRC” bit and ”Dummy” bit (16 bits). ”RW” bit is the bit to select the write or the read operation, and at when ”RW” bit=’0’, the read operation is selected. ”Address” bit is the bit to specify the address, and the data are read from the address of ”Address” bit. ”CRC” bit is calculated by the micro controller, according to 16 bits of ”RW” bit, ”Address ”bit, and ”Dummy” bit (10 bits). SDOUT is consist of ”Dummy” bit (8 bits), ”Data” bit, ”Dummy” bit (16 bits), and ”CRC” bit. The data read from the address of ”Address” bit of the SDIN is output to ”Data” bit. "CRC" bit outputs the value which is calculated from 8 bits of "Data" bit by the IC. Fig.9-c Data structure of read operation <CRC error judgment> An error judgment is performed by the CRC to confirm the data communication correctly. The generation polynomial used for the calculation is the following. x8+x4+x3+x2+1 In the case of CRC error, the operation is the following. (1) In the case of write operation The write data are not written to the IC. Fig.9-d CRC error in the case of write operation (2)In the case of read operation Incorrect data are written to the CRC bit of the SCOUT in the same frame. Then the micro controller detects a CRC error. Fig.9-e CRC error in the case of read operation <In the case of Vcc under voltage detection> The SPI communication cannot perform when Vcc under voltage is detected. And then, the SDOUT is fixed to 'L' (at the write and the read operation). <Fail judgment> In the following cases at the SPI communication, the IC judges it as a communication error, and 1 is written to err_spi which is the register of the SPI communication error. (1) Access to the address which has no register (2) When data length is except 40 bits R Adr1 CRC CRCDum /CS SDIN SDOUT Dum Data R Adr2 CRC Bad CRCDum Dum Data Address determined CRC error Dum Dum Dum Dum When CRC error, IC returns the wrong CRC deliberately W Adr1 Adr1 Data CRC Dum Dum /CS SDIN SDOUT W Adr2 Adr2 Data CRC Dum CRC error Dum When CRC error, data is not written in the IC RW Address (5bit) Data (8bit) CRC (8bit) Dummy（16bit） CRC (8bit)Dummy（16bit） SDIN SDOUT SCK /CS Dummy (8bit) Dummy（10bit）

2019-02-27 37 ©2015-2019 Toshiba Electronic Devices & Storage Corporation (9-2) SPI Register Map Table 9- 2a config 1 ( Address : 0x01) bit 7 6 5 4 3 2 1 0 Symbol df_alm1 df_alm2 sh_op - DEFAULT 1 1 1 1 0 1 0 0 Table 9- 2b config2 (Address : 0x02) bit 7 6 5 4 3 2 1 0 Symbol - - - ovc_op tsd_op pl_op DEFAULT 0 0 0 0 1 1 0 0 Prohibit Pre-Driver Output Setting : In case that High-side and Low-side Input of the same Phase are “H”, the both High-side and Low-side Output are forced to be “L” (Input) HUI=LUI=”H” → HUO=LUO=”L” HVI=LVI=”H” → HVO=LVO=”L” HWI=LW I=”H” → HWO=LWO=“L” setting of ALARM1 Digital Filtering Time （H-side/L-side ） (Fc=4MHz typ.) setting of ALARM2 Digital Filtering Time （H-side/L-side ） (Fc=4MHz(typ.) Response of Short circuit Detection "000" = NDIAG：L (Hold) "001" = NDIAG：L (Hold), Detected Phase Pre-Driver OFF (During detection) "010" = NDIAG：L (Hold), Detected Phase Pre-Driver OFF(Hold) "011" = NDIAG：L (hold), All (eleven) Pre-Driver OFF (During detection) "100" = NDIAG：L (Hold), All (eleven) Pre-Driver OFF (Hold) "101" = NDIAG：L (Hold), All (eleven) Pre-Driver and Charge Pump OFF (During detection) "110" = NDIAG：L (Hold), All (eleven) Pre-Driver and Charge Pump OFF (Hold) "111" = Detection disable 3:1 sh_op R/W 5:4 df_alm2 R/W FunctionSymbolbit R/W df_alm1 R/W7:6 Response of VCC1/VCC2 Over Voltage Detection "00" = NDIAG：output "L" (Hold) "01" = NDIAG：output "L" (Hold), All (eleven) Pre-Driver OFF "10" = NDIAG：output "L" (Hold), All (eleven) Pre-Driver and Charge Pump OFF (During detection) "11" = NDIAG：output "L" (Hold), All (eleven) Pre-Driver and Charge Pump OFF (Hold) Response of Over Temperature Detection "00" = NDIAG：output "L" (Hold) "01" = NDIAG：output "L" (Hold), All (eleven) Pre-Driver OFF (During detection) "10" = NDIAG：output "L" (Hold), All (eleven) Pre-Driver and Charge Pump OFF (During detection) "11" = NDIAG：output "L" (Hold), All (eleven) Pre-Driver and Charge Pump OFF (Hold) Response of Prohibit Pre-Driver Output setting Detection "0" = NDAIG：no outpu , During Prohibit input, Detected Phase Pre-Driver OFF "1" = NDIAG：output "L" (Hold), During Prohibit input, Detected Phase Pre-Driver OFF tsd_op R/W2:1 0 pl_op R/W ovc_op R/W4:3 FunctionSymbolbit R/W

2019-02-27 38 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Table 9- 2c config3 (Address : 0x03) bit 7 6 5 4 3 2 1 0 Symbol uvb_op co_sel ferr_op - DEFAULT 0 1 0 0 1 0 0 0 * : don’t care Table 9- 2d config4 (Address : 0x04) bit 7 6 5 4 3 2 1 0 Symbol - df_sh vthh_sh vthl_sh DEFAULT 0 0 0 1 0 0 0 1 * : don’t care setting Digital Filtering Time of Short Circuit Detection (typ. at 4MHz) "000" = 6μs "001" = 8μs "010" = 10μs "011" = 12μs "1**" = no Filtering setting Threshold Voltage of Short Circuit Detection（Hi-side ） "00" = 0.5V "01" = 0.75V "10" = 1.0V "11" = 1.25V setting Threshold Voltage of Short Circuit Detection（Lo-side） "00" = 0.5V "01" = 0.75V "10" = 1.0V "11" = 1.25V Function df_sh R/W6:4 Symbolbit R/W vthh_sh R/W3:2 vthl_sh R/W1:0 Response of VB1/VB2 Low Voltage Detection "00" = NDIAG：output "L" (Hold), All (eleven) Pre-Driver OFF (During detection) "01" = NDIAG：output "L", All (eleven) Pre-Driver OFF (During detection) "1*" = NDIAG：output "H", All (eleven) Pre-Driver OFF (During detection) setting Monitoring Output Signal of "CLKOUT" "00" = output "L" "01" = clk4m 4MHｚ (typ.) "10" = clk500k 500kHz(typ.) "11" = clk16k 16kHz(typ.) Response of Internal OSC Over/Low Frequency Detectioin 000 = NDIAG：output "L" (Hold) 001 = NDIAG：output "L" (Hold), All (eleven) Pre-Driver OFF (During detection) 010 = NDIAG：output "L" (Hold), All (eleven) Pre-Driver and Charge Pump OFF(During detection) 011 = NDIAG：output "L" (Hold), All (eleven) Pre-Driver and Charge Pump OFF (Hold) 1** = nop 3:1 ferr_op R/W FunctionSymbolbit R/W uvb_op R/W7:6 5:4 co_sel R/W

2019-02-27 39 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Table 9- 2e config5 (Address : 0x05) bit 7 6 5 4 3 2 1 0 Symbol rebst diag_dg shuh_dg shul_dg shvh_dg shvl_dg shwh_dg shwl_dg DEFAULT 0 0 0 0 0 0 0 0 ・ BIST restart by SPI Reg. “rebst” is enable when LBIST or ABIST is failure. In normal operation and LBIST/ABIST passed, the Write ”rebst”=1 is ignored and do not restart BIST. ・ Forced Short Circuit Detection: - Output “L” from PIN ”NDIAG” - each detected Phase Pre-Driver OFF according to the setting by SPI Reg. “sh_op”(address 0x01 bit1-3) - Charge Pump OFF according to the setting by SPI Reg. “sh_op”(config1) ・ To write “0” into the SPI Reg. ”sh**_dg”, the above detection response are reset and return to normal operation. ・ In case of SPI Reg. “sh_op”=”111”(config1), the above Short Circuit Detection Diagnosis does not performed, even write “1” into the above each Short Circuit Detection Diagnosis register. BIST restart request by SPI Command "0"： nop "1"： restart BIST NDIAG Diagnosis Check by SPI Command "0"： nop (NDIAG normal Operation) "1"： Forced output "L" from PIN"NDIAG" Short Circuit Detection Diagnosis Check by SPI Command （U-Phase Lo-side） "0"： nop (Short Detection Norma Operation) "1"： Forced Short Circuit Detection (output "L" from PIN"NDIAG") Short Circuit Detection Diagnosis Check by SPI Command （U-Phase Hi-side） "0"： nop (Short Detection Norma Operation) "1"： Forced Short Circuit Detection (output "L" from PIN"NDIAG") Short Circuit Detection Diagnosis Check by SPI Command （V-Phase Lo-side）） "0"： nop (Short Detection Norma Operation) "1"： Forced Short Circuit Detection (output "L" from PIN"NDIAG") Short Circuit Detection Diagnosis Check by SPI Command （V-Phase Hi-side） "0"： nop (Short Detection Norma Operation) "1"： Forced Short Circuit Detection (output "L" from PIN"NDIAG") Short Circuit Detection Diagnosis Check by SPI Command （W-Phase Lo-side） "0"： nop (Short Detection Norma Operation) "1"： Forced Short Circuit Detection (output "L" from PIN"NDIAG") Short Circuit Detection Diagnosis Check by SPI Command （W-Phase Hi-side）） "0"： nop (Short Detection Norma Operation) "1"： Forced Short Circuit Detection (output "L" from PIN"NDIAG") shuh_dg5 R/W Function diag_dg6 Symbolbit R/W R/W 7 rebst R/W 4 shul_dg R/W 3 shvh_dg R/W R/W 2 shvl_dg R/W 1 shwh_dg R/W 0 shwl_dg

2019-02-27 40 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Table 9- 2f config6 (Address : 0x06) bit 7 6 5 4 3 2 1 0 Symbol - - - - - - t_ilim DEFAULT 0 0 0 0 0 0 0 0 The Current Limit is available for each Output of Pre-driver (HUO,HVO,HWO,LUO,LVO,LWO) (refer “Electrical characteristics”). These Current Limit are disabled the above period which is set by SPI Reg. “t_ilim”. For example, when ”t_ilim” is set “00”, during 8μs(typ.) after Turn On/Turn Off, there is no Current Limit and after 8μs(typ.) passed, the Current Limit which is shown in the spec. is enable. Current Limit of Turn On : Io_lmth = 1mA (typ.) Current Limit of Turn Off : Io_lmt l = 10mA (typ.) Table 9 -2g status1 (Address : 0x07) bit 7 6 5 4 3 2 1 0 NAME uvb - ovc - - - - - DEFAULT 0 0 0 0 0 0 0 0 ・ When the above each SPI Reg. is written “1” after return to normal condition, each detection Flag is reset and the SPI Reg. are "0" (Default). In this case, Output NDAIG=High, return to normal operation. “0” write into these SPI Reg. is ignored. When abnormal condition is kept, the write “1” is ignored and keep detection response. VB1/VB2 Low Voltage Detection Flag "0" = Normal "1" = Detected Low Volateg of VB1/VB2 VCC1/VCC2 Over Volatge Detection Flage "0" = Normal "1" = Detected Over Volateg of VB1/VB2 FunctionSymbolbit R/W uvb7 R/W ovc R/W seting time of Current Limit disable after Turn On/Off (typ. at 4MHz) "00" = 8μs "01" = 16μs "10" = 32μs "11" = Always Current Limit enable t_ilim R/W1:0 FunctionSymbolbit R/W

2019-02-27 41 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Table 9 -2h status2 (Address : 0x08) bit 7 6 5 4 3 2 1 0 Symbol - - tsd1det tsd2det tsd3det - - - DEFAULT 0 0 0 0 0 0 0 0 ・ When the above each SPI Reg. is written “1” after return to normal condition, each detection Flag is reset and the SPI Reg. are "0" (Default). In this case, Output NDAIG=High, return to normal operation. “0” write into these SPI Reg. is ignored. When abnormal condition is kept, the write “1” is ignored and keep detection response. Over Temperature Detection1 "0" = Mormal "1" = detected Over Temperature1 Over Temperature Detection2 "0" = Normal "1" = detected Over Temperature2 Over Temperature Detection3 "0" = Normal "1" = Over Temperature Detection3 FunctionSymbolbit R/W 5 tsd1det R/W tsd2det R/W R/Wtsd3det

2019-02-27 42 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Table 9- 2i status3 (Address : 0x09) bit 7 6 5 4 3 2 1 0 Symbol - - scuh scvh scwh scul scvl scwl DEFAULT 0 0 0 0 0 0 0 0 ・ When the above each SPI Reg. is written “1” after return to normal condition, each detection Flag is reset and the SPI Reg. are "0" (Default). In this case, Output NDAIG=High, return to normal operation. “0” write into these SPI Reg. is ignored. When abnormal condition is kept, the write “1” is ignored and keep detection response. Short Detection of external MOSFET（UPhase, GND Short ） "0" = Normal "1" = Detected Short Circuit Short Detection of external MOSFET（VPhase, GND Short） "0" = Normal "1" = Detected Short Circuit Short Detection of external MOSFET（WPhase, GND Short） "0" = Normal "1" = Detected Short Circuit Short Detection of external MOSFET（UPhase, VB Short） "0" = Normal "1" = Detected Short Circuit Short Detection of external MOSFET（VPhase, VB Short） "0" = Normal "1" = Detected Short Circuit Short Detection of external MOSFET（WPhase, VB Short） "0" = Normal "1" = Detected Short Circuit FunctionSymbolbit R/W 5 scuh R/W s cvh4 scwh R/W R/W scwl scul2 s cvl R/W R/W R/W

2019-02-27 43 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Table 9 -2j status4 (Address : 0x0A ) bit 7 6 5 4 3 2 1 0 Symbol err_of err_uf err_plu err_plv err_plw err_spi - - DEFAULT 0 0 0 0 0 0 0 0 ・ When the above each SPI Reg. is written “1” after return to normal condition, each detection Flag is reset and the SPI Reg. are "0" (Default). In this case, Output NDAIG=High, return to normal operation. “0” write into these SPI Reg. is ignored. When abnormal condition is kept, the write “1” is ignored and keep detection response. setting of Internal OSC Over Frequency Detection "0" = Normal "1" = Detected Over Frequency of internal OSC setting of Internal OSC low Frequency Detection "0" = Normal "1" = Detected Low Frequency of internal OSC setting of Prohibit U-Phase Pre-Driver Output setting Detection "0" = Normal "1" = Detected Prohibit setting of U-Phase setting of Prohibit V-Phase Pre-Driver Output setting Detection "0" = Normal "1" = Deteced Prohibit setting of V-Phase setting of Prohibit W-Phase Pre-Driver Output setting Detection "0" = Normal "1" = Detected Prohibit setting of W-Phase setting of SPI Transmission Failure Detection "0" = Normal "1" = Detected SPI Transmission Failure err_of7 R/W FUNCTIONSymbolbit R/W 4 err_plv R/W 6 err_uf R/W 5 err_plu R/W 3 err_plw R/W 2 err_spi R/W

2019-02-27 44 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Table 9 -2k status5 ( Address : 0x0B ) bit 7 6 5 4 3 2 1 0 Symbol abst_judge abst_pass lbst_pass abst_end lbst_end DEFAULT 0 0 0 0 0 0 0 0 When ABIST/LBIST is finished, SPI Reg.”abst_end” / ”lbst_end” is “1”. When ABIST/LBIST cannot be finished abnormally, SPI Reg. ”abst_end” / ”lbst_end” is “0”. After finish ABIST/LBIST normally and that result is passed, SPI Reg. ”abst_pass” / ”lbst_pass” is “1”. When ABIST/LBIST result is failure, SPI Reg. ”abst_pass” / ”lbst_pass” is “0”. ABIST counter value "11**" = ABIST error "101*" = ABIST error "1001" = ABIST error "1000" = No error ABIST Result Flag "0" = Result ”Failure” "1" = Result”PASS” LBIST Result Flag "0" = Result "Failure" "1" = Result”PASS” ABIST Finish Flag "0" =Irregular ABIST stop "1" = Finish LBIST Finish Flag "0" = Irregular LBIST stop "1" = Finish FunctionSymbolbit R/W abst_judge R7:4 0 lbst_end R 1 abst_end R R R abst_pass lbst_pass

2019-02-27 45 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Absolute maximum ratings (Ta = 25°C) Unless otherwise specified, all voltage is the AGND standard voltage Item Symbol Pin Rate Unit Condition Supply voltage Vb VB1,VB2 -0.3 to +28(DC) V - +28 to +40(≤1s) Vcpl VCPL -0.3 to +20 V - Vcph VCPH -0.3 to +40 V - Vcc VCC1,VCC2 -0.3 to +6 V - Vccop VCC_OP -0.3 to +6 V - Voltage between AGND and PGND terminals Vgnd AGND1,AGND2, PGND1,PGND2,PGND3 -0.3 to +0.3 V AGND: AGND1,2 PGND: PGND1,2,3 Input voltage Vin1 LUI, LVI, LWI, HUI, HVI, HWI, BR1I, BR2I, RUI, RVI, RWI, SCK, /CS, SDIN, ALARM1, ALARM2, EN_CP, TEST AMP1P, AMP1N, AMP2P, AMP2N, AMP3P, AMP3N,VRI -0.3 to Vcc +0.3 V Vin1≤6V Vin2 HS, SHU, SHV, SHW -0.3 to Vcph +0.3 V Vin2≤40V Vin3 BR1O, BR2O -18 to 0 V AGND1,2=PGND1,2,3=0V Terminals other than the above are open. Output voltage Vout1 CP1H, CP2H, HUO, HVO,HWO, BR1O, BR2O, RUO, RVO, RWO -0.3 to Vcph +0.3 V Vout1≤40V Vout2 CP1L, CP2L -0.3 to Vb +0.3 V Vout2≤28V(DC) Vout2≤40V(≤1s) Vout3 LUO, LVO, LWO -0.3 to Vcpl +0.3 V Vout3≤20V Vout4 AMP1O, AMP2O, AMP3O, VRO -0.3 to Vccop +0.3 V Vout4≤6V Vout5 NDIAG, CLKOUT, SDOUT -0.3 to Vcc +0.3 V Vout5≤6V Input current Iin1 SHU, SHV, SHW, (-10) mA External resistance :1kΩ Time ≤ 5µs The numerical value in a parenthesis means a design value. Iin2 AMP1P, AMP1N, AMP2P, AMP2N, AMP3P, AMP3N ±5 mA - Output current Iout1 HUO, HVO,HWO, LUO, LVO, LWO -5 to 20 mA - Iout2 ±1 A Time shorter than output current switching time(Tsw) PWM period: 50μs Iout3 AMP1O, AMP2O, AMP3O,VRO ±5 mA - Iout4 NDIAG, CLKOUT, SDOUT ±10 mA - Operating ambient temperature Ta - -40 to 125 °C - Storage temperature Tstg - -55 to 150 °C -

2019-02-27 46 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Power dissipation PD - 515 mW JEDEC 4 layer board, Ta=125°C, Thermal resistance 48.5°C/W * The numerical value in a parenthesis means a design value. The shipment test is not performed. <<User notes>> *Absolute maximum ratings represent the values which cannot be exceeded for any length of time. *The sink current to this IC is shown with '+', the sink current from this IC is shown with " -." *The value of absolute maximum ratings is limited by the range of condition column. *The symbols (Vb, Vcpl, Vcph, Vcc, and Vccop) shown in the above maximum ratings table mean the supply voltage and output voltage in each terminal (VB1/2, VCPL, VCPH, VCC1/2, and VCC_OP). *Use the through rate of Vb and Vcc in the following range. less than Vb=8V/μs, less than Vcc=0.3V/μs *This product is intended for use with a 12 V battery. Power dissipation curve 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -50 -25 0 25 50 75 100 125 150 Power Dissipation （W） Ta （℃） -40 (Reference) Board: JEDEC 4 layer board Thermal resistance: 48.5°C/W

2019-02-27 47 ©2015-2019 Toshiba Electronic Devices & Storage Corporation terminal Symbol Rating Unit Condition Input voltage VB1,VB2 Vb 4.5 to 28 V DC VCC1,VCC2 Vcc 3.0 to 5.5 V DC VCC_OP Vccop 3.0 to 5.5 V DC * This product is intended for use with a 12 V battery. Current consumption Unless otherwise specified, Vb=4.5 to 28V, Vcc=3 to 5.5V, Vccop=3 to 5.5V, Ta=-40 to 125°C Item Applied terminal Symbol Measurement condition Min Typ. Max Unit stand-by current (Vb) VB1,VB2 Ib1 Vb=12V ,Vcc=Vccop=0V - 0.01 2.0 μA Current consumption (Vb) VB1,VB2 Ib2 Vb=13.5V HUO,HVO,HWO=20kHz LUO,LVO,LWO=20kHz Cload=10000pF, Rload=33Ω - 100 200 mA Ib3 Vb=17V HUO,HVO,HWO=20kHz LUO,LVO,LWO=20kHz Cload=10000pF, Rload=33Ω - 120 250 mA Ib4 Vb=28V HUO,HVO,HWO=20kHz LUO,LVO,LWO=20kHz Cload=10000pF, Rload=33Ω - 200 300 mA Current consumption (Vcc) VCC1,VCC2 Icc1 Vcc=5V 4.0 6.5 10.0 mA Icc2 Vcc=3.3V 3.0 5.5 9.0 mA Current consumption (Vccop) VCC_OP Iccop1 Vccop=5V 3.0 6.5 11.0 mA Iccop2 Vccop=3.3V 3.0 5.5 9.0 mA * Ib1, Ib2, Ib3, Ib4 is the current obtained by summing the current of VB1 and VB2. * Icc1, Icc2 is the current obtained by summing the current of VCC1 and VCC2. * When Vcc is lowered, IC will be the stand-by state. Current in the stand-by state has been defined by the Ib1. * The external constant of charge pump in Ib2, Ib3, Ib4 is the constant of the reference circuit example.

2019-02-27 48 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Charge pump circuit Unless otherwise specified, Vb=4.5 to 28V, Vcc=3 to 5.5V, Ta=-40 to 125°C, Fc=4MHz Item Applied terminal Symbol Measurement condition Min Typ. Max Unit Note Output voltage VCPL Vcpl Vb=4.5 to 5.5V (Output load=1.5kΩ) Vb+4 - - V - Vb=5.5 to 7V (Output load=1.5kΩ) Vb+6 - - V - Vb=7 to 28V (Output load=1.5kΩ) Vb+8 (Vcplcl) - - V - VCPH Vcph Vb=4.5 to 5.5V (Output load=1.5kΩ) Vb+4 - - V - Vb=5.5 to 7V (Output load=1.5kΩ) Vb+6 - - V - Vb=7 to 8V (Output load=1.5kΩ) Vb+8 - - V - Vb=8 to 28V (Output load=1.5kΩ) Vb+10 (Vcphcll) Vb+12 Vb+14 (Vcphclh) V - Clamp voltage VCPL Vcplcl - 14 16 18 V - VCPH Vcphclh - 34.5 37 40 V - Vcphcll - 34 36.5 39.5 V - * The following shows the reference values of the external capacitors and resistance of CP1H, CP1L, CP2H, CP2L, VCPH, and VCPL terminal; Ccp = 0.1 [μF], Rcp = 15 [Ω], Cvcph1 = 10 [μF], Cvcph2 = 0.1 [μF], Cvcpl1 = 4.7 [μF], Cvcpl2 = 0.1 [μF] The external circuit should be decided after certainly evaluating and confirming on the unit board supposing the usage environment.

2019-02-27 49 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Charge Pump1 CP1H CP1L VCPL Charge Pump2 VCPH CP2H CP2L Clamp （16V） Pre-drv. （Low-side） Pre-drv. （High-side） SR1 SR3 SR2 Vb Vb Vcc Vcc Vcc Vcc Vcc Fig.1-c Charge pump application circuit diagram Cvcph1=10 μF Cvcpl1=4.7 μF Cvcph2=0.1μF Cvcpl2=0.1μF Ccp=0.1 μF Ccp=0.1 μF Rcp=15Ω Rcp=15Ω

2019-02-27 50 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Pre-diver circuit Unless otherwise specified, Vb=4.5 to 28V, Vcc=3 to 5.5V, Ta=-40 to 125°C, Fc=4MHz Item Applied terminal Symbol Measurement condition Min Typ. Max Unit Note High level input current HUI, HVI, HWI, LUI, LVI, LWI, RUI, RVI, RWI, BR1I, BR2I Iih Vcc= 5.0V, Vin = 5.0V 50 100 200 μA - Low level input current Iil Vcc = 5.0V, Vin = 0V -5 - 5 μA - High level input detection voltage HUI, HVI, HWI, LUI, LVI, LWI, RUI, RVI, RWI, BR1I, BR2I Vih 0.75× Vcc - - V - Low level input detection voltage Vil - - 0.25× Vcc V - Output voltage 1 HUO,HVO,HWO Voh1 Iload=-100μA Vcph-0.1 - Vcph V - Vol1 Iload=100μA - - 0.5 V - Output voltage 2 LUO,LVO,LWO Voh2 Iload=-100μA Vcpl-0.1 - Vcpl V - Vol2 Iload=100μA - - 0.5 V - Output voltage 3 BR1O,BR2O Voh3 Iload=-100μA Vcph-0.2 - Vcph V - Vol3 Iload=10μA - - 0.9 V - Output voltage 4 RUO,RVO,RWO Voh4 Iload=-100μA Vcph-0.2 - Vcph V - Vol4 Iload=100μA - - 0.5 V - Output resistance1 HUO,HVO,HWO Rohh HUI,HVI,HWI = 5.0V Iload=-50mA 1.0 2.5 6.0 Ω Before passing Tsw Rohl HUI,HVI,HWI = 0V Iload=50mA 0.3 1.0 3.0 Ω Before passing Tsw Output resistance2 LUO,LVO,LWO Rolh LUI,LVI,LWI = 5.0V Iload=-50mA 1.0 2.5 6.0 Ω Before passing Tsw Roll LUI,LVI,LWI = 0V Iload=50mA 0.3 1.0 3.0 Ω Before passing Tsw Output resistance3 RUO,RVO,RWO Rorh RUI,RVI,RWI = 5.0V Iload=-5mA 0.8 1 1.2 kΩ - Rorl RUI,RVI,RWI = 0V Iload=5mA 0.8 1 1.2 kΩ - Output resistance4 BR1O,BR2O Robh BR1I,BR2I = 5.0V Iload=-5mA 0.8 1 1.2 kΩ - Robl BR1I,BR2I = 0V Robl=Vd/4mA 0.8 1 1.2 kΩ Refer to Fig.2-e. Leakage current at the time of VB reverse connection BR1O,BR2O Iol BR1O,BR2O =-18V , PGND1,2,3=0V 0 0.01 1.0 μA - * For the motor relay output, RUO, RVO, and RWO, connect the external series resistance more than 10 kΩ.

2019-02-27 51 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Unless otherwise specified, Vb=4.5 to 28V, Vcc=3 to 5.5V, Ta=-40 to 125°C, Fc=4MHz Item Applied terminal Symbol Measurement condition Min Typ. Max Unit Note Output limit current HUO,HVO,HWO LUO,LVO,LWO Io_lmth When turning on After passing Tsw -1.4 -1 -0.6 mA Refer to Fig.2-d. Io_lmtl When turning off After passing Tsw 6 10 14 mA Refer to Fig.2-d. Output current switching time HUO,HVO,HWO LUO,LVO,LWO Tsw - 5 8 14 μs t_ilim = “00” Refer to Fig.2-d - 10 16 28 μs t_ilim = “01” Refer to Fig.2-d - 20 32 56 μs t_ilim = “10” Refer to Fig.2-d Turn on input propagation delay time HUI,HVI,HWI, HUO,HVO,HWO Tdonh1 Ta=-40°C, VCC=3.0 to 3.5V , Rload=33Ω, Cload=10000pF 50 120 1200 ns Refer to Fig.2-d. Tdonh2 Ta=25/125°C, VCC=3.0 to 3.5V , Rload=33Ω, Cload=10000pF 50 120 250 ns Refer to Fig.2-d. Tdonh3 VCC=3.5 to 5.5V , Rload=33Ω, Cload=10000pF 50 120 250 ns Refer to Fig.2-d. LUI,LVI,LWI, LUO,LVO,LWO Tdonl1 Ta=-40°C, VCC=3.0 to 3.5V , Rload=33Ω, Cload=10000pF 50 120 1200 ns Refer to Fig.2-d. Tdonl2 Ta=25/125°C, VCC=3.0 to 3.5V , Rload=33Ω, Cload=10000pF 50 120 250 ns Refer to Fig.2-d. Tdonl3 VCC=3.5 to 5.5V , Rload=33Ω, Cload=10000pF 50 120 250 ns Refer to Fig.2-d. Turn off input propagation delay time HUI,HVI,HWI, HUO,HVO,HWO Tdoffh Rload=33Ω, Cload=10000pF 100 180 300 ns Refer to Fig.2-d. LUI,LVI,LWI, LUO,LVO,LWO Tdoffl Rload=33Ω, Cload=10000pF 100 180 300 ns Refer to Fig.2-d. Difference of input propagation delay time HUI,HVI,HWI, LUI,LVI,LWI, HUO,HVO,HWO LUO,LVO,LWO dTd1 Ta=-40°C, VCC=3.0 to 3.5V , Tdonh-Tdoffl, Tdonl-Tdoffh -125 - 1150 ns Difference between H or L side of the same phrases, U,V , and W dTd2 Ta=25/125°C, VCC=3.0 to 3.5V , Tdonh-Tdoffl, Tdonl-Tdoffh -125 - 125 ns Difference between H or L side of the same phrases, U,V , and W dTd3 VCC=3.5 to 5.5V , Tdonh-Tdoffl, Tdonl-Tdoffh -125 - 125 ns Difference between H or L side of the same phrases, U,V , and W * For the measurement circuit, refer to Fig.2-b and Fig.2-c.

2019-02-27 52 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Fig.2-b Measurement circuit diagram (High side/Low side) Fig.2-c Measurement circuit diagram (power supply relay/motor relay) 10000pF RUO,RVO,RWO BR1O,BR2O Cload measurement point HUO,HVO,HWO LUO,LVO,LWO 33Ω 10000pF measurement point Cload Rload

2019-02-27 53 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Fig.2-d Timing chart of output current switching time and input propagation delay time Fig.2-e Measurement method of BR1O and BR2O output resistance input signal Hi-side output signal Hi-side Tdonh Vcph×0.2 Vcph×0.8 input signal Lo-side output signal Lo-side Tdoffl Vcpl×0.8 Tdoffh Vcpl×0.2 Tdonl Vcc×0.25 Vcc×0.25 Vcc×0.75 Vcc×0.75 output current Hi-side Io_lmth Tsw output current Lo-side Io_lmtl Tsw Io_lmth TswIo_lmtl Tsw BR1O,BR2O output voltage Vd 1mA 5mA load current Iload

2019-02-27 54 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Current detection circuit Unless otherwise specified, Vb=4.5 to 28V, Vccop=3 to 5.5V, Ta=-40 to 125°C Item Applied terminal Symbol Measurement condition Min Typ. Max Unit Note Input voltage range VRI Vin1 - 0.5 - Vccop -1.4 V - Input offset voltage VRI Voff1 Vin1=0.5 to Vccop-1.4V -7 - 7 mV - AM P * P, AMP*M Voff2 Gain=5, Vinr =-0.5V to 0.5V , VRO=Vccop/2, Iload = 0, and 1mA -7 - 7 mV - Input offset voltage Temperature characteristic AM P * P, AMP*M VoffdT Gain=5, Vinr =-0.5V to 0.5V , VRO=Vccop/2, Iload = 0, and 1mA (-15) - (15) μV/°C The numerical value in a parenthesis means a design value. Input bias current VRI AM P * P, AMP*M Iin - -1 - 1 μA - Output voltage VRO Vo Iload = -2mA 0.5 - Vccop -1.4 V - AMP*O Voh Gain=5, Vinr=-0.1×Vccop, VRO=Vccop/2, Iload = -1mA Vccop -0.3 - Vccop V - Vol Gain=5, Vinr=0.1×Vccop, VRO=Vccop/2, Iload = 1mA 0 - 0.3 V - Slew rate AMP*O SR1 Gain=5 Rload=1kΩ, Cload=100pF 10 20 40 V/μs Refer to Fig.3-d. SR2 -40 -20 -10 V/μs Refer to Fig.3-d. * shows from 1 to 3 *The input resistance, R1 and R2 should be used in the range from 1.5 kΩ to 20kΩ, R3 should be used at 100 kΩ or less. *The Gain should be used in the range from 5 to 30 times. *The amplifier configuration should be used with the configuration shown in Fig.3 -c. * The numerical value in a parenthesis means a design value. The shipment test is not performed. Fig.3-c Measurement circuit diagram VRO AMP*P AMP*N AMP*O Rsh Vccop Vinr VRI Vccop Vccop

2019-02-27 55 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Fig.3-d Slew rate timing chart input voltage Vinr output voltage -0.5V 0.5V 0.8x(Vccop-0.3) ΔTrΔTf ※SR1 = 0.6x(Vccop-0.3)/ΔTr ※SR2 = -0.6x(Vccop-0.3)/ΔTf 0.2x(Vccop-0.3)

2019-02-27 56 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Oscillator / Divider Unless otherwise specified, Vb=4.5 to 28V, Vcc=3 to 5.5V, Ta=-40 to 125°C, Fc=4 MHz Item Applied terminal Symbol Measurement condition Min Typ. Max Unit Note Internal oscillation frequency - Fc - 2.6 4 5.4 MHz - Output voltage CLKOUT Voh Ioh=-2mA 0.85×Vcc - - V - Vol Iol=2mA - - 0.15×Vcc V - Division output CLKOUT Fco - - Fc - Hz co_sel = “01” (clk4m) - Fc/23 - co_sel = “10” (clk500k) - Fc/250 - co_sel = “11” (clk16k) * CLKOUT pin is connected to the internal resistance 100Ω (typ.).

2019-02-27 57 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Failure detection circuit Unless otherwise specified, Vb=4.5 to 28V, Vcc=3 to 5.5V, Ta=-40 to 125°C, Fc=4 MHz Item Applied terminal Symbol Measurement condition Min Typ. Max Unit Note Detection voltage of Vb under voltage VB1,VB2 Vthblh - 4.2 4.35 4.5 V - Vthbll - 3.9 4.05 4.2 V - Vthblhys - 0.2 0.3 0.4 V - Filtering time of Vb under voltage detection VB1,VB2 Tbl - 13 20 34 μs - Detection voltage of Vcc under voltage VCC1,VCC2 Vthclh - 2.7 2.85 3.0 V - Vthcll - 2.55 2.70 2.85 V - Vthclhys - 0.10 0.15 0.20 V - Replying time of Vcc under voltage detection VCC1,VCC2 Tcl - 10 20 40 μs - Detection voltage of Vcc over voltage VCC1,VCC2 Vthchh - 5.6 5.75 5.9 V - Vthchl - 5.5 5.65 5.8 V - Vthchhys - 0.05 0.10 0.15 V - Filtering time of Vcc over voltage detection VCC1,VCC2 Tch - 13 20 34 μs - Detection temperature of over temperature - Tsdh - (155) (170) (185) °C The numerical value in a parenthesis means a design value. Release temperature of over temperature detection The numerical value in a parenthesis means a design value. Filtering time of over temperature detection The numerical value in a parenthesis means a design value. * The numerical value in a parenthesis means a design value. The shipment test is not performed. * When Vcc is lower than the detection voltage of Vcc under voltage further, IC will be the stand-by state.

2019-02-27 58 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Unless otherwise specified, Vb=4.5 to 28V, Vcc=3 to 5.5V, Ta=-40 to 125°C, Fc=4 MHz Item Applied terminal Symbol Measurement condition Min Typ. Max Unit Note Filtering time of short-circuit detection - Tsf - 3.9 6 10.2 μs df_sh=000 5.2 8 13.6 df_sh=001 6.5 10 17.0 df_sh=010 7.8 12 20.4 df_sh=011 Short-circuit detection threshold voltage (High-side) - Vthh_sh - 0.4 0.5 0.6 V vthh_sh=00 0.6 0.75 0.9 vthh_sh=01 0.8 1 1.2 vthh_sh=10 1.0 1.25 1.5 vthh_sh=11 Short-detection threshold voltage (Low-side) - Vthl_sh - 0.4 0.5 0.6 V vthl_sh=00 0.6 0.75 0.9 vthl_sh=01 0.8 1 1.2 vthl_sh=10 1.0 1.25 1.5 vthl_sh=11 NDIAG output voltage NDIAG Voh Ioh = -5mA 0.9×Vcc - - V - Vol Iol = 5mA - - 0.1×Vcc V - L hold voltage NDIAG Vlk Vcc=1.1V to Vthcll Iol = 100μA 0 - 0.3 V Refer to Fig.5-2c. Frequency of high frequency detection - Fh - 6.4 8 9.6 MHz - Frequency of low frequency detection - Fl - 1.6 2 2.4 MHz - *The voltage between HS and SH* of the IC terminals has prescribed the short-circuit detection threshold voltage (High-side). *The voltage between SH* and PGND of the IC terminals has prescribed the s hort-circuit detection threshold voltage (Low-side). * Since current flows into HS terminal and SH* terminal, the short-detection threshold value is decided by the external resistance of a register, HS, and SH*. Fig.5-2c L hold voltage 2 1 0 Vcc [V] terminal voltage [V] Vthcll 0.3V L hold voltage 1.1V

2019-02-27 59 ©2015-2019 Toshiba Electronic Devices & Storage Corporation ALARM input circuit Unless otherwise specified, Vb=4.5 to 28V, Vcc=3 to 5.5V, Ta=-40 to 125°C, Fc=4 MHz Item Applied terminal Symbol Measurement condition Min Typ. Max Unit Note High level input current ALARM1 ALARM2 Iih Vcc = 5.0V, Vin = 5.0V 50 100 200 μA - Low level input current Iil Vcc = 5.0V, Vin = 0V -5 - 5 μA - High level input detection voltage ALARM1 ALARM2 Vih 0.75× Vcc - - V - Low level input detection voltage Vil - - 0.25× Vcc V - Pulse width of input detection ALARM1 ALARM2 Twmin H,L detection 16x22/Fc +1/Fc - - s df_alm1 = ”00” df_alm2 = ”00” 1000x22/Fc +1/Fc - - s df_alm1 = ”01” df_alm2 = ”01” 2000x22/Fc +1/Fc - - s df_alm1 = ”10” df_alm2 = ”10” 4000x22/Fc +1/Fc - - s df_alm1 = ”11” df_alm2 = ”11” Pulse width of input removal ALARM1 ALARM2 Twmax H,L detection - - 15x22/Fc -1/Fc s df_alm1 = ”00” df_alm2 = ”00” - - 999x22/Fc -1/Fc s df_alm1 = ”01” df_alm2 = ”01” - - 1999x22/Fc -1/Fc s df_alm1 = ”10” df_alm2 = ”10” - - 3999x22/Fc -1/Fc s df_alm1 = ”11” df_alm2 = ”11” <<User note>> *The pulse width of the input detection (Twmin) means the pulse width which passes through a digital filter and appears to an output. The pulse width of the input removal (Twmax) means the pulse width which is removed by the digital filter (Fig.6-b). Fig.6-b Pulse width of input removal (with filter) and pulse width of input detection (with filter) Pulse width of input removal (H side) Pulse width of input detection (H side) ALARM input signal digital filter output signal Pulse width of input detection (L side) Pulse width of input removal (L side)

2019-02-27 60 ©2015-2019 Toshiba Electronic Devices & Storage Corporation EN_CP Input circuit Unless otherwise specified, Vb=4.5 to 28V, Vcc=3 to 5.5V, Ta=-40 to 125°C Item Applied terminal Symbol Measurement condition Min Typ. Max Unit Note High level input current EN_CP Iih Vcc = 5.0V, Vin = 5.0V 50 100 200 μA - Low level input current Iil Vcc = 5.0V, Vin = 0V -5 - 5 μA - High level input detection voltage EN_CP Vih 0.75× Vcc - - V - Low level input detection voltage Vil - - 0.25× Vcc V -

2019-02-27 61 ©2015-2019 Toshiba Electronic Devices & Storage Corporation SPI Communication circuit Unless otherwise specified,Vb=4.5 to 28V, Vcc=3 to 5.5V, Ta=-40 to 125°C, Fc=4 MHz Item Applied termina l Symb ol Measuremen t condition Min Typ. Max Unit Note High level input current /CS Iih Vcc = 5.0V, Vin = 5.0V -5 - 5 μA - Low level input current Iil Vcc = 5.0V, Vin = 0V -200 -100 -50 μA - High level input current SCK, SDIN Iih Vcc = 5.0V, Vin = 5.0V 50 100 200 μA - Low level input current Iil Vcc = 5.0V, Vin = 0V -5 - 5 μA - High level input detection voltage /CS, SCK, SDIN Vthh 0.75× Vcc - - V - Low level input detection voltage Vthl - - 0.25× Vcc V - Output voltage SDOUT Vohso Iohso = -5mA 0.9×V cc - - V - Volso Iolso = 5mA - - 0.1×V cc V - Valid standby time /CS SCK Tcsck fop = 2MHz 250 - - ns Time from /CS falling edge to SCK rising edge. Invalid standby time Tckcs - 250 - - ns Time from the last SCK falling edge to /CS rising edge Delay time from /CS falling to SDOUT /CS SDOUT Tcsdo Cload=100pF - - 340 ns Time until SDOUT stops being the Tri State from /CS falling edge Delay time from SDOUT to /CS rising Tdocs Cload=100pF - - 100 ns Time until SDOUT becomes the Tri State from /CS rising edge SDIN setup time SCK SDIN Tdick - 120 - - ns Time when SDIN is valid before SCK falling edge SDIN hold time Tckdi - 120 - - ns Time when SDIN is valid after SCK falling edge SDOUT valid time SCK SDOUT Tckdo Cload=100pF - - 100 ns Time from SCK rising edge to valid output data /CS invalid time /CS Tcsh - 5 - - μs Invalid time between continuous /CS Operation frequency SCK fop - - - 2 MHz - SPI Timing chart SDOUT SDIN SCK /CS Tcsck Tcsdo Tdick Tckdi A39 A38 A1 A0 B39 B1 B0 Tcsh Tckcs Tdocs MSB LSB Vthl Vthh Vthl Vthh Vthl Vthh Volso Vohso Tckdo Tckdo Tckdo Vthl Vthh Vthh Volso Vohso Volso Vohso

2019-02-27 62 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Reference circuit diagram <Notes> * These circuit constants are reference circuit examples, and are not guaranteed. The external circuit should be decided after certainly evaluating and confirming on the unit board supposing the usage environment. * The smoothing capacitor connected externally to the power supply terminals (VB1, VB2, VCC1, VCC2 and VCC_OP) should be the layout on the IC as close as possible. *The power supply of the resistance partial pressure connected to the VRI terminal should be used as the same power supply as VCC_OP . * AGND1, 2 and PGND1, 2, and 3 should be the solid GND (potential ±0.3V) on the unit board. *Consider notes of each block at the time of a unit design. * Do not implement incorrectly. The destruction of the ICs or the damage to the devices may occur. VB1 VB2 Battery HUO HVO LUO LVO PGND1 PGND2 PGND3 VRI SDIN SDOUT SCK CP1H MCU Power supply IC TEST LWO /CS ALARM1 HWO BR1O RUO ALARM2 CLKOUT NDIAG VCC_OP CP1L VCPL CP2H CP2L VCPH BR2O RVO RWO BR1I BR2I RUI RVI RWI HUI HVI HWI LUI LVI LWI VRO AMP1P AMP1N AMP2N AMP2O AMP2P AMP3P AMP3N AMP3O AMP1O SHW SHV SHU HS AGND1 AGND2 VCC2 EN_CP M Each voltage det ection cir cuit Current sensor AMP1AMP3 V REF1 AMP2 Pre-Driver 11ch For Motor：6ch For Relay：5ch OSC SPI FET short detection TSD1 TSD2 TSD3 Charge pump ALA RM input circuit Error Logic BG1 BG2 EN_CP input circuit VCC_OP VCC1 100μF+0.1μF 0.1μF +15Ω 10μF+0.1μF 4.7μF+0.1μF 50kΩ 50kΩ 50kΩ 50kΩ 50kΩ 50kΩ 50kΩ 50kΩ 50kΩ 50kΩ 50kΩ 50kΩ 50kΩ 1.5kΩ 1.5kΩ 1.5kΩ 1.5kΩ 1.5kΩ 1.5kΩ 7.5kΩ 7.5kΩ 7.5kΩ 7.5kΩ 7.5kΩ 7.5kΩ 10kΩ 10kΩ 10kΩ 10kΩ 10kΩ 1kΩ 33Ω 33Ω 33Ω 1kΩ 1kΩ 1kΩ 33Ω 33Ω 33Ω 10μF 0.1μF +15Ω 0.1μF 10μF 0.1μF 0.1μF

2019-02-27 63 ©2015-2019 Toshiba Electronic Devices & Storage Corporation PACKAGE LQFP64-P-1010-0.50E Unit: mm Weight: 0.35 g (typ.)

2019-02-27 64 ©2015-2019 Toshiba Electronic Devices & Storage Corporation Version Item Contents (Changes) Modification date 1.0 - New release 2016-03-28 2.0 All chapter Modify the specification by corresponding to the ES2. 2017-04-28 Pre-driver circuit Modify the block diagram and review the explanation. Abnormal detection circuit Review the explanation of operation. Add Note4 / Note5 Change the word \Latch\ to \Hold\ in each timing chart of the abnormal detection. SPI Register Map Review the explanation. Modify the status5 [7:4] register. Reference circuit diagram Modify the reference circuit diagram 2.1 Abnormal detection circuit Explanation of operation of oscillation frequency monitoring function, revision of timing chart of oscillation frequency monitoring function . 2017-08-07 Absolute maximum ratings Change of absolute maximum ratings. 2.2 SPI Register Map Modify the config 1 [3:1], 2[4:0], 3[7:6] [3:1] register. 2018-04-02 2.3 Absolute maximum ratings Operating voltage range Delete time regulation of VB = 28 V. 2018-04-18 2.4 - Modify the text. 2018-05-07 2.5 - Add supplementary explanation 2019-02-27

2019-02-27 65 ©2015-2019 Toshiba Electronic Devices & Storage Corporation RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”. Hardware, software and systems described in this document are collectively referred to as “Product”.

• TOSHIBA reserves the right to make changes to the information in this document and related Product without notice.
• This document and any information herein may not be reproduced without prior written permission from TOSHIBA. Even with TOSHIBA's written permission, reproduction is permissible only if reproduction is without alteration/omission.
• Though TOSHIBA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. TOSHIBA ASSUMES NO LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS.
• PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MA Y CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT ("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, lifesaving and/or life supporting medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, and devices related to power plant. IF YOU USE PRODUCT FOR UNINTENDED USE, TOSHIBA ASSUMES NO LIABILITY FOR PRODUCT. For details, please contact your TOSHIBA sales representative or contact us via our website.
• Do not disassemble, analyze, reverse-engineer, alter, modify, translate or copy Product, whether in whole or in part.
• Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations.
• The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
• ABSENT A WRITTEN SIGNED AGREEMENT, EXCEPT AS PROVIDED IN THE RELEVANT TERMS AND CONDITIONS OF SALE FOR PRODUCT, AND TO THE MAXIMUM EXTENT ALLOWABLE BY LAW, TOSHIBA (1) ASSUMES NO LIABILITY WHATSOEVER, INCLUDING WITHOUT LIMITATION, INDIRECT, CONSEQUENTIAL, SPECIAL, OR INCIDENTAL DAMAGES OR LOSS, INCLUDING WITHOUT LIMITATION, LOSS OF PROFITS, LOSS OF OPPORTUNITIES, BUSINESS INTERRUPTION AND LOSS OF DATA, AND (2) DISCLAIMS ANY AND ALL EXPRESS OR IMPLIED WARRANTIES AND CONDITIONS RELATED TO SALE, USE OF PRODUCT, OR INFORMATION, INCLUDING WARRANTIES OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, ACCURACY OF INFORMATION, OR NONINFRINGEMENT.
• Do not use or otherwise make available Product or related software or technology for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). Product and related software and technology may be controlled under the applicable export laws and regulations including, without limitation, the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations.
• Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA ASSUMES NO LIABILITY FOR DAMAGES OR LOSSES OCCURRING AS A RESULT OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS. https://toshiba.semicon-storage.com/