TB62726ANG

TB62726ANG MARKTECH | Alldatasheet

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Technical content

Features

Output current capability and number of outputs: 90 mA × 16 outputs Constant current range: 2 to 90 mA Application output voltage: 0.7 V (output current 2 to 80 mA)

0.4 V (output current 2 to 40 mA)

Input signal voltage level: 3.3-V and 5-V CMOS level (Schmitt trigger input) Power supply voltage range VDD = 3.0 to 5.5 V Maximum output terminal voltage: 17 V Serial and parallel data transfer rate: 20 MHz (max, cascade connection) Operating temperature range Topr = −40 to 85°C Type AFG: SSOP24-P-300-1.00B Current accuracy (All output ON) Current Accuracy Output Voltage Between Bits Between ICs Output Current = 0.4 V ±15% 2 to 5 mA = 0.7 V ±4% ±12% 5 to 80 mA TB62726ANG TB62726AFG Weight SDIP24-P-300-1.78: 1.22 g (typ.) SSOP24-P-300-1.00B: 0.32 g (typ.) Web: www.marktechopto.com | Email: info@marktechopto.com Company Headquarters

3 Northway Lane North

Latham, New York 12110 Toll Free: 800.984.5337 Fax: 518.785.4725 California Sales Office:

950 South Coast Drive, Suite 225

Costa Mesa, California 92626 Toll Free: 800.984.5337 Fax: 714.850.9314

Pin Assignment (top view) Warnings: Short-circuiting an output terminal to GND or to the power supply terminal may broken the device. Please take care when wiring the output terminals, the power supply terminal and the GND terminals. Block Diagram Truth Table CLOCK LATCH ENABLE SERIAL-IN OUT0 … OUT7 … OUT15 SERIAL-OUT H L Dn Dn … Dn − 7 … Dn − 15 Dn − 15 L L Dn + 1 No change Dn − 14 H L Dn + 2 Dn + 2 … Dn − 5 … Dn − 13 Dn − 13 X L Dn + 3 Dn + 2 … Dn − 5 … Dn − 13 Dn − 13 X H Dn + 3 OFF Dn − 13 Note 1: OUT0 to OUT15 = On when Dn = H; OUT0 to OUT15 = Off when Dn = L. In order to ensure that the level of the power supply voltage is correct, an external resistor must be connected between R-EXT and GND. GND SERIAL-IN LATCH CLOCK OUT0 OUT1 OUT2 OUT3 VDD R-EXT SERIAL-OUT ENABLE OUT15 OUT14 OUT13 OUT12 OUT4 OUT5 OUT6 OUT7 OUT11 OUT10 OUT9 OUT8 SERIAL-IN LATCH OUT0 R-EXT ENABLE I-REG Q ST D Q ST D D Q CK Q ST D D Q CK D Q CK CLOCK OUT1 OUT15 SERIAL-OUT

Warning: Latch circuit is leveled-latch circuit. Be careful because it is not triggered-latch circuit. Note 2: The latches circuit holds data by pulling the LATCH terminal Low. And, when LATCH terminal is a High level, latch circuit doesn’t hold data, and it passes from the input to the output. When ENABLE terminal is a Low level, output terminal OUT0 to OUT15 respond to the data, and on and off does. And, when ENABLE terminal is a High level, it offs with the output terminal regardless of the data. SERIAL-IN LATCH CLOCK OUT0 OUT1 OUT3 SERIAL-OUT ENABLE OUT15

3.3 V/5 V

n = 0

Pin No. Pin Name Function GND GND terminal for control logic SERIAL-IN Input terminal for serial data for data shift register CLOCK Input terminal for clock for data shift on rising edge LATCH Input terminal for data strobe When the LATCH input is driven High, data is not latched. When it is pulled Low, data is latched. 5 to 20 OUT0 to OUT15 Constant-current output terminals ENABLE Input terminal for output enable. All outputs ( OUT0 to OUT15 ) are turned off, when the ENABLE terminal is driven High. And are turned on, when the terminal is driven Low. SERIAL-OUT Output terminal for serial data input on SERIAL-IN terminal R-EXT Input terminal used to connect an external resistor. This regulated the output current. VDD 3.3-V/5-V supply voltage terminal Equivalent Circuits for Inputs and Outputs 1. ENABLE terminal 2. LATCH terminal 3. CLOCK, SERIAL-IN terminal 4. SERIAL-OUT terminal 5. OUT0 to OUT15 terminals VDD ENABLE GND R (UP) VDD LATCH GND R (DOWN) CLOCK, SERIAL-IN VDD GND VDD GND Internal data SERIAL-OUT Parasitic Diode OUT0 to OUT15 GND

Maximum Ratings (Topr = 25°C) Characteristics Symbol Rating Unit Supply voltage VDD V Input voltage VIN −0.2 to VDD + 0.2 V Output current IOUT +90 mA/ch Output voltage VOUT −0.2 to 17 V ANG-type (when not mounted) 1.25 ANG-type (on PCB) Pd1 1.78 AFG-type (when not mounted) 0.83 Power dissipation (Note 3) AFG-type (on PCB) Pd2 1.00 W ANG-type (when not mounted) 104 ANG-type (on PCB) Rth (j-a) 1 AFG-type (when not mounted) 140 Thermal resistance (Note 3) AFG-type (on PCB) Rth (j-a) 2 120 °C/W Operating temperature Topr −40 to 85 Storage temperature Tstg −55 to 150 Note 3: ANG-Type: Powers dissipation is derated by 14.28 mW/°C if device is mounted on PCB and ambient temperature is above 25°C. AFG-Type: Powers dissipation is derated by 6.67 mW/°C if device is mounted on PCB and ambient temperature is above 25°C. With device mounted on glass-epoxy PCB of less than 40% Cu and of dimensions 50 mm × 50 mm × 1.6 mm. Recommended Operating Conditions (Topr = −40°C to 85°C unless otherwise specified) Characteristics Symbol Conditions Min Typ. Max Unit Supply voltage VDD 5.5 V Output voltage VOUT 0.7 V IOUT Each DC 1 circuit mA/ch IOH SERIAL-OUT Output current IOL SERIAL-OUT mA VIH 0.7 × VDD VDD + 0.15 Input voltage VIL −0.15 0.3 × VDD V Clock frequency fCLK MHz LATCH pulse width twLAT Cascade connected ns CLOCK pulse width twCLK ns Upper IOUT = 20 mA 2000 ENABLE pulse width (Note 4) twENA Lower IOUT = 20 mA 3000 ns Set-up time for CLOCK terminal tSETUP1 ns Hold time for CLOCK terminal tHOLD ns Set-up time for LATCH terminal tSETUP2 ns Note 4: When the pulse of the Low level is inputted to the ENABLE terminal held in the High level.

Electrical Characteristics (Topr = 25°C, VDD = 3.0 V to 5.5 V unless otherwise specified) Characteristics Symbol Conditions Min Typ. Max Unit Supply voltage VDD Normal operation 3.0 5.5 V IOUT1 VOUT = 0.4 V, VDD = 3.3 V 31.96 36.20 40.54 IOUT2 VOUT = 0.4 V, VDD = 5 V REXT = 490 Ω 31. 59 35.90 40.20 IOUT3 VOUT = 0.7 V, VDD = 3.3 V 63.63 72.30 80.97 Output current IOUT4 VOUT = 0.7 V, VDD = 5 V REXT = 250 Ω 62.75 71.30 79.95 mA ∆IOUT1 VOUT ≥ 0.4 V, All outputs ON REXT = 490 Ω Output current error between bits ∆IOUT2 VOUT ≥ 0.4 V, All outputs ON REXT = 250 Ω Output leakage current input voltage IOZ VOUT = 15.0 V µA 0.7 VDD VDD Input voltage VIN GND 0.3 VDD V IOL = 1.0 mA, VDD = 3.3 V 0.3 VOL IOL = 1.0 mA, VDD = 5 V 0.3 IOH = − 1.0 mA, VDD = 3.3 V SOUT terminal voltage VOH IOH = 1.0 mA, VDD = 5 V 4.7 V Output current Supply voltage Regulation %/VDD When VDD is changed 3 V to 5.5 V Pull-up resistor R (Up) ENABLE terminal Pull-down resistor R (Down) LATCH terminal 115 230 460 kΩ IDD (OFF) 1 VOUT = 15.0 V REXT = OPEN 0.1 0.5 IDD (OFF) 2 VOUT = 15.0 V, All outputs OFF REXT = 490 Ω 3.5 IDD (OFF) 3 VOUT = 15.0 V, All outputs OFF REXT = 250 Ω VOUT = 0.7 V, All outputs ON REXT = 490 Ω IDD (ON) 1 Same as the above, Topr = −40°C VOUT = 0.7 V, All outputs ON REXT = 250 Ω Supply current IDD (ON) 2 Same as the above, Topr = −40°C mA

Switching Characteristics (Topr = 25°C unless otherwise specifed) Characteristics Symbol Conditions Min Typ. Max Unit tpLH1 CLK- OUTn , LATCH = “H”, ENABLE = “L” 150 300 tpLH2 LATCH - OUTn , ENABLE = “L” 140 300 tpLH3 ENABLE - OUTn , LATCH = “H” 140 300 tpLH CLK-SERIAL OUT tpHL1 CLK- OUTn , LATCH = “H”, ENABLE = “L” 170 340 tpHL2 LATCH - OUTn , ENABLE = “L” 170 340 tpHL3 ENABLE - OUTn , LATCH = “H” 170 340 Propagation delay tpLH CLK-SERIAL OUT ns Output rise time tor 10 to 90% of voltage waveform 150 ns Output fall time tof 90 to 10% of voltage waveform 150 ns Maximum CLOCK rise time tr µs Maximum CLOCK fall time tf When not on PCB (Note 5) µs Conditions: (Refer to test circuit.) Topr = 25°C, VDD = VIH = 3.3 V and 5 V, VOUT = 0.7 V, VIL = 0 V, REXT = 490 Ω, VL = 3.0 V, RL = 60 Ω, CL = 10.5 pF Note 5: If the device is connected in a cascade and tr/tf for the waveform is large, it may not be possible to achieve the timing required for data transfer. Please consider the timings carefully. Test Circuit Logic input waveform VDD = VIH = 3.3 V VIL = 0 V tr = tf = 10 ns (10% to 90%) GND SERIAL-IN LATCH CLOCK OUT0 VDD R-EXT SERIAL-OUT ENABLE OUT15 Function generator IOL VIH, VIL Iref CL VL RL CL IDD

1. CLOCK, SERIAL-IN, SERIAL-OUT 2. CLOCK, SERIAL-IN, LATCH, ENABLE, OUTn 3. OUTn tHOLD tpLH/tpHL twCLK 50% 50% 50% 50% tSETUP1 SERIAL-IN CLOCK SERIAL-OUT 50% twENA 50% tSETUP2 SERIAL-IN CLOCK 50% 50% 50% 50% tSETUP3 tpHL1/LH1 tpHL2/LH2 tpHL3/LH3 twLAT ENABLE LATCH OUTn 50% tof 10% 90% 10% 90% tor OUTn OFF ON

Output Current – Duty (LEDS turn-on rate) Output Current – REXT Resistor 100 1000 10000 Topr = 25°C VCE = 0.7 V 5000 500 Theoretical value: IOUT = (1.15 (V) ÷ R-EXT (Ω)) × 14.9 DUTY – Turn On Rate (%) IOUT (mA) DUTY – Turn On Rate (%) IOUT – DUTY On PCB IOUT (mA) IOUT – DUTY On PCB DUTY – Turn On Rate (%) IOUT (mA) IOUT – DUTY On PCB Ambient temperature Ta (°C) Pd – Topr Power dissipation PD (W/IC) REXT (Ω) IOUT (mA) IOUT – REXT 100 100 TB62726AFG TB62726ANG Topr = 25°C VDD = 3.3 V to 5.0 V VCE = 1.0 V Tj = 120°C (max) 100 100 TB62726AFG TB62726ANG Topr = 55°C VDD = 3.3 V to 5.0 V VCE = 1.0 V Tj = 120°C (max) 100 100 TB62726AFG TB62726ANG Topr = 85°C VDD = 3.3 V to 5.0 V VCE = 1.0 V Tj = 120°C (max) 100 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 NG (On PCB) FG (On PCB)

Application Circuit (example 1): The general composition in static lighting of LED. More than VLED (V) ≥ Vf (total max) + 0.7 is recommended with the following application circuit with the LED power supply VLED. r1: The setup resistance for the setup of output current of every IC. r2: The variable resistance for the brightness control of every LED module. 16-bit SIPO, Latches and Constant-sink-current drivers TB62726ANG/AFG 16-bit SIPO, Latches and Constant-sink-current drivers TB62726ANG/AFG SERIAL-IN ENABLE LATCH CLOCK C.U. SERIAL-IN CLOCK SCAN r1 = 100 Ω(min) VLED SERIAL-OUT SERIAL-OUT r1 = 100 Ω (min) Example) TD62M8600F: 8-bit multi-chip PNP transistor array, which is not used in static lighting system. ENABLE LATCH O13 O14 O15 O13 O14 O15

Application Circuit (example 2): When the condition of VLED is VLED > 17 V The unnecessary voltage is one effective technique as to making the voltage descend with the zenor diode. 16-bit SIPO, Latches and Constant-sink-current drivers TB62726ANG/AFG 16-bit SIPO, Latches and Constant-sink-current drivers TB62726ANG/AFG SERIAL-IN CLOCK C.U. SERIAL-IN CLOCK SCAN r1 = 100 Ω (min) VLED > 17 V SERIAL-OUT SERIAL-OUT r1 = 100 Ω (min) Example) TD62M8600F: 8-bit multi-chip PNP transistor array, which is not used in static lighting system. ENABLE LATCH ENABLE LATCH O13 O14 O15 O13 O14 O15

Application Circuit (example 3): When the condition of VLED is Vf +0.7 < VLED < 17 V VOUT = VLED-Vf = 0.7 to 1.0 V is the most suitable for VOUT. Surplus VOUT causes an IC fever and the useless consumption electric power. It is the one way of being effective to build in the r3 in this problem. r3 can make a calculation to the formula r3 Ω = surplus VOUT/IOUT. Though the resistance parts increase, the fixed constant current performance is kept 16-bit SIPO, Latches and Constant-sink-current drivers TB62726ANG/AFG 16-bit SIPO, Latches and Constant-sink-current drivers TB62726ANG/AFG SERIAL-IN CLOCK C.U. SERIAL-IN CLOCK SCAN r1 = 100 Ω (min) VLED = 15 V SERIAL-OUT SERIAL-OUT r1 = 100 Ω (min) Example) TD62M8600F: 8-bit multi-chip PNP transistor array, which is not used in static lighting system. ENABLE LATCH LATCH O13 O14 O15 O13 O14 O15

Operation may become unstable due to the electromagnetic interference caused by the wiring and other phenomena. To counter this, it is recommended that the IC be situated as close as possible to the LED module. If overvoltage is caused by inductance between the LED and the output terminals, both the LED and the terminals may suffer damage as a result. There is only one GND terminal on this device when the inductance in the GND line and the resistor are large, the device may malfunction due to the GND noise when output switchings by the circuit board pattern and wiring. To achieve stable operation, it is necessary to connect a resistor between the REXT terminal and the GND line. Fluctuation in the output waveform is likely to occur when the GND line is unstable or when a capacitor (of more than 50 pF) is used. Therefore, take care when designing the circuit board pattern layout and the wiring from the controller. This application circuit is a reference example and is not guaranteed to work in all conditions. Be sure to check the operation of your circuits. This device does not include protection circuits for overvoltage, overcurrent or overtemperature. If protection is necessary, it must be incorporated into the control circuitry. The device is likely to be destroyed if a short-circuit occurs between either of the power supply pins and any of the output terminals when designing circuits, pay special attention to the positions of the output terminals and the power supply terminals (VDD and VLED), and to the design of the GND line.

Weight: 1.22 g (typ.)

Weight: 0.32 g (typ.)

1. Block Diagrams Some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for explanatory purposes. 2. Maximum Ratings The absolute maximum ratings of a semiconductor device are a set of specified parameter values that must not be exceeded during operation, even for an instant. If any of these ratings are exceeded during operation, the electrical characteristics of the device may be irreparably altered and the reliability and lifetime of the device can no longer be guaranteed. Moreover, any exceeding of the ratings during operation may cause breakdown, damage and/or degradation in other equipment. Applications using the device should be designed so that no maximum rating will ever be exceeded under any operating conditions. Before using, creating and/or producing designs, refer to and comply with the precautions and conditions set forth in this document. 3. Recommended operating conditions The values of the conditions are applied within the range of the operating temperature and not guaranteed. 4. Test Circuits Components in test circuits are used only to obtain and confirm device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure in application equipment. 5. Graphics characteristics Graphics characteristics are reference ones and not guaranteed. 6. Timing Charts Timing charts may be simplified for explanatory purposes. 7. Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 8. Application Circuits The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially in the phase of mass production design. In furnishing these examples of application circuits, Toshiba does not grant the use of any industrial property rights. Handling of the IC Ensure that the product is installed correctly to prevent breakdown, damage and/or degradation in the product or equipment.