TB62725BPG MARKTECH | Alldatasheet
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Technical content
Features
Output current capability and number of outputs: 90 mA × 8 outputs Constant current range: 5 to 80 mA Application output voltage:
0.7 V (output current 5 to 80 mA)
0.4 V (output current 5 to 40 mA)
For anodecommon LEDs Input signal voltage level: 3.3V and 5V CMOS level (Schmitt trigger input) Maximum output terminal voltage: 17 V Serial data transfer rate: 20 MHz (max, cascade connection) Operating temperature range: Topr = −40 to 85°C Package: Type BPG: DIP16P3002.54A Type BFG: SSOP16P2251.00A Type BFNG: SSOP16P2250.65B Package and pin layout: Pin layout and functionality are similar to those of the TB62705C series and TB62725A series. (Each characteristic value is different.) Constantcurrent accuracy (all outputs on) Output Voltage Current Error between Bits Current Error between ICs Output Current = 0.4 V 5 to 40 mA = 0.7 V ±6% ±15% 5 to 90 mA TB62725BPG TB62725BFG TB62725BFNG Weight DIP16P3002.54A: 1.11 g (typ.) SSOP16P2251.00A: 0.14 g (typ.) SSOP16P2250.65B: 0.07 g (typ.) Web: www.marktechopto.com | Email: info@marktechopto.com Company Headquarters
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20050420 Pin Assignment (top view) Pin layout and functionality are similar to those of the TB62705C. (each characteristic value is different.) Block Diagram Truth Table CLOCK LATCH ENABLE SERIALIN SERIALOUT H L Dn Dn − 7 L L Dn + 1 No change Dn − 6 H L Dn + 2 Dn − 5 X L Dn + 3 Dn − 5 X H Dn + 3 Off Dn − 5 Note 1: OUT0 to OUT7 = On when Dn = H; to OUT0 to OUT7 = Off when Dn = L. In order to ensure that the level of the power supply voltage is correct, an external resistor must be connected between REXT and GND. SERIALIN LATCH OUT0 REXT ENABLE IREG Q L D Q L D D Q CK Q L D D Q CK D Q CK CLOCK OUT1 OUT7 SERIALOUT GND SERIALIN LATCH CLOCK OUT0 OUT1 OUT2 OUT3 VDD REXT SERIALOUT ENABLE OUT7 OUT6 OUT5 OUT4
20050420 Timing Diagram Warning: Latch circuit is leveledlatch circuit. Be careful because it is not triggeredlatch circuit. Note 2: The latches circuit holds data by pulling the LATCH terminal Low. And, when LATCH terminal is a highlevel, latch circuit doesn’t hold data, and it passes from the input to the output. When ENABLE terminal is a lowlevel, output terminal OUT0 to OUT7 respond to the data, and on and off does. Attention: This IC can be used in 3.3 V or 5.0 V. However, use the VDD power supply and the input level in the same voltage system. SERIALIN LATCH CLOCK OUT0 OUT1 OUT3 SERIALOUT ENABLE OUT7
3.3 V/5 V
n = 0
20050420 Terminal Description Pin No. Pin Name Function GND GND terminal for control logic. SERIALIN Input terminal for serial data for data shift register. CLOCK Input terminal for clock for data shift on rising edge. LATCH Input terminal for data strobe. When the LATCH input is driven High, data is latched. When it is pulled Low, data is hold. 5 to 12 OUT0 to OUT7 Constantcurrent output terminals. ENABLE Input terminal for output enable. All outputs ( OUT0 to OUT7 ) be turned off, when the ENABLE terminal is driven High. And are turned on, when the terminal is driven Low. SERIALOUT Output terminal for serial data input on SERIALIN terminal. REXT Input terminal used to connect an external resistor. This regulated the output current. VDD 3.3V and 5V supply voltage terminal. Equivalent Circuits for Inputs and Outputs ENABLE Terminal LATCH Terminal CLOCK, SERIALIN Terminal SERIALOUT Terminal OUT0 to OUT7 Terminals VDD ENABLE GND 200 kΩ 100 Ω R (UP) VDD LATCH GND 100 Ω R (DOWN) 250 kΩ CLOCK, SERIALIN VDD GND 100 Ω VDD GND 100 Ω SERIALOUT Parasitic Diode OUT0 to OUT7 GND
20050420 Maximum Ratings (Topr = 25°C) Characteristics Symbol Rating Unit Supply voltage VDD V Input voltage VIN −0.2 to VDD + 0.2 V Output current IOUT mA/ch Output voltage VOUT −0.2 to 17 V BPGtype (when not mounted) Pd1 1.47 BFG/BFNGtype (when not mounted) 0.37 Power dissipation (Note 3) BFG/BFNGtype (on PCB) Pd2 0.78 W BPGtype (when not mounted) Rth (ja) 1 BFG/BFNGtype (when not mounted) Rth (ja) 2 330 Thermal resistance (Note 3) BFG/BFNGtype (on PCB) Rth (ja) 3 160 °C/W Operating temperature Topr −40 to 85 Storage temperature Tstg −55 to 150 Note 3: BPGtype: Power dissipation is delated by 11.76 mW/°C if device is mounted on PCB and ambient temperature is above 25°C. BFG and BFNGtype: Power dissipation is delated by 7.69 mW/°C if device is mounted on PCB and ambient temperature is above 25°C. With device mounted on glassepoxy PCB of less than 40% Cu and of dimensions 50 mm × 50 mm × 1.6 mm Recommended Operating Conditions (Topr = −40°C to 85°C unless otherwise specified) Characteristics Symbol Test Condition Min Typ. Max Unit Supply voltage VDD 5.5 V Output voltage VOUT 0.7 V IOUT Each DC 1 circuit mA/ch IOH SERIALOUT Output current IOL SERIALOUT mA VIH 0.7 × VDD VDD + 0.15 Input voltage VIL −0.15 0.3 × VDD mA Clock frequency fCLK Cascade Connected MHz LATCH pulse width LATCH w t ns IOUT > = 20 mA 2000 ENABLE pulse width (Note 4) ENABLE w t IOUT < 20 mA 3000 ns CLOCK pulse width twCLOCK Setup time for CLOCK terminal tSETUP1 Hold time for CLOCK terminal tHOLD Setup time for LATCH terminal tSETUP2 ns Note 4: When the pulse of the low level is inputted to the ENABLE terminal held in the high level.
20050420 Electrical Characteristics (VDD = 5 V, Ta = 25°C unless otherwise specified) Characteristics Symbol Test Condition Min Typ. Max Unit Supply voltage VDD Normal operation 4.5 5.5 V IOUT1 VOUT = 0.4 V, VDD = 3.3 V REXT = 490 Ω 29.84 35.10 40.36 IOUT2 VOUT = 0.4 V, VDD = 5 V REXT = 250 Ω 29.58 34.80 40.02 IOUT3 VOUT = 0.7 V, VDD = 3.3 V REXT = 490 Ω 58.40 68.70 79.00 Output current IOUT4 VOUT = 0.7 V, VDD = 5 V REXT = 250 Ω 57.55 67.70 77.85 mA ∆IOUT1 VOUT = 0.4 V, All outputs ON REXT = 490 Ω ±1.5 Output current Error between bits ∆IOUT2 VOUT = 0.7 V, All outputs ON REXT = 250 Ω ±1.5 Output leakage current IOZ VOUT = 15 V µA VIH 0.7 VDD VDD Input voltage VIL GND 0.3 VDD V IOH = 1.0 mA, VDD = 3.3 V 0.3 SOUT terminal VOL IOH = 1.0 mA, VDD = 5 V 0.3 V IOL = −1.0 mA, VDD = 3.3 V Output voltage VOH IOH = 1.0 mA, VDD = 5 V 4.7 V Output current Supply voltage Regulation %/VDD VDD = 3 V → 5.5 V ±1.5 ±5.0 Pullup resistor R (Up) ENABLE terminal 100 200 400 kΩ Pulldown resistor R (Down) LATCH terminal 125 250 500 kΩ IDD (OFF) 1 VOUT = 15.0 V REXT = OPEN 0.1 0.5 IDD (OFF) 2 VOUT = 15.0 V, All outputs OFF REXT = 490 Ω IDD (OFF) 3 VOUT = 15.0 V, All outputs OFF REXT = 250 Ω VOUT = 0.7 V, All outputs ON REXT = 490 Ω IDD (ON) 1 Same as the above, Topr = −40°C VOUT = 0.7 V, All outputs ON Supply current IDD (ON) 2 Same as the above, Topr = −40°C REXT = 250 Ω mA
20050420 Switching Characteristics (Topr = 25°C unless otherwise specified) Characteristics Symbol Test Condition Min Typ. Max Unit tpLH1 CLK to OUTn , LATCH = “H”, ENABLE = “L” 150 300 tpLH2 LATCH to OUTn , ENABLE = “L” 140 300 tpLH3 ENABLE to OUTn , LATCH = “H” 140 300 tpLH CLK to SERIAL OUT tpHL1 CLK to OUTn , LATCH = “H”, ENABLE = “L” 170 340 tpHL2 LATCH to OUTn , ENABLE = “L” 170 340 tpHL3 ENABLE to OUTn , LATCH = “H” 170 340 Propagation delay time tpHL CLK to SERIAL OUT ns Output rise time tor 10 to 90% of voltage waveform 150 ns Output fall time tof 90 to 10% of voltage waveform 150 ns Maximum clock rise time tr us Maximum clock fall time tf Cascade connection isn’t guarantee. (Note 5) us Conditions: (refer to test circuit.) Topr = 25°C, VDD = VIH = 5 V, VOUT = 0.7 V, VIL = 0 V, REXT = 490 Ω, VL = 5.0 V, RL = 100 Ω, CL = 10.5 pF Note 5: If the device is connected in a cascade and tr/tf for the waveform is large, it may not be possible to achieve the timing required for data transfer. Please consider the timings carefully. Test Circuit GND SERIALIN LATCH CLOCK OUT0 VDD REXT SERIALOUT ENABLE OUT7 Function generator IOL VIH, VHL Iref CL VL RL CL Logic input waveform VDD = VIH = 5 V VIL = 0 V tr = tf = 10 ns (10% to 90%) IDD
20050420 Timing Waveforms 1. CLOCK, SERIALIN, SERIALOUT 2. CLOCK, SERIALIN,LATCH ,ENABLE , OUTn 3. OUTn tof 10% 90% 10% 90% tof OUTn OFF ON tHOLD tpLH/tpHL twCLK 50% 50% 50% 50% tSETUP1 SERIALIN CLOCK SERIALOUT 50% twENA 50% tSETUP2 SERIALIN CLOCK 50% 50% 50% 50% 50% tSETUP3 tpHL1/LH1 tpHL2/LH2 tpHL3/LH3 twLAT ENABLE LATCH OUTn
20050420 Output Current – Duty (LED turnon rate) DUTY – Turn on rate (%) IOUT (mA) DUTY – Turn on rate (%) IOUT – DUTY On PCB (recommended) IOUT (mA) IOUT – DUTY On PCB ( recommended ) 100 100 BFG/BFNG BPG Topr = 55°C VDD = 5.0 V VCE = 1.0 V Tj = 120°C (max) 100 100 Topr = 25°C VDD = 5.0 V VCE = 1.0 V Tj = 120°C (max) BFG/BFNG BPG DUTY – Turn on rate (%) IOUT (mA) IOUT – DUTY On PCB (recommended) 100 100 Topr = 85°C VDD = 5.0 V VCE = 1.0 V Tj = 120°C (max) BFG/BFNG BPG REXT (Ω) IOUT (mA) IOUT – REXT 100 1000 10000 Topr = 25°C VCE = 0.7 V 5000 500 IOUT (mA) = (1.15 ÷ REXT (Ω)) × 14.9 Ambient temperature Ta (°C) Pd –Topr Power dissipation PD (W/IC) 1.6 1.2 1.0 0.6 100 1.4 0.8 0.2 0.4 BFG/BFNG (mounted PCB) BPG (Free air)
20050420 Application Circuit (example 1): The general composition in static lighting of LED. More than VLED (V) > = Vf (total max) +0.7 is recommended with the following application circuit with the LED power supply VLED. r1: The setup resistance for the setup of output current of every IC. r2: The variable resistance for the brightness control of every LED module. VLED 8bit SIPO, Latches and Constantsinkcurrent drivers TB62725BPG/BFG/BFNG 8bit SIPO, Latches and Constantsinkcurrent drivers TB62725BPG/BFG/BFNG C.U. SERIALIN ENABLE LATCH CLOCK SCAN r1 = 100 Ω (min) SERIALOUT SERIALOUT r1 = 100 Ω (min) Example) TD62M8600: 8bit multichip PNP transistor array, which is not used in static lighting system. SERIALIN ENABLE LATCH CLOCK
20050420 Application Circuit (example 2): When the condition of VLED is VLED > 17 V. The unnecessary voltage is one effective technique as to making the voltage descend with the zennor diode. 8bit SIPO, Latches and Constantsinkcurrent drivers TB62725BPG/BFG/BFNG 8bit SIPO, Latches and Constantsinkcurrent drivers TB62725BPG/BFG/BFNG C.U. SERIALIN ENABLE LATCH CLOCK SCAN r1 = 100 Ω VLED SERIALOUT SERIALOUT r1 = 100 Ω Example) TD62M8600: 8bit multichip PNP transistor array, which is not used in static lighting system. SERIALIN ENABLE LATCH CLOCK
20050420 Application Circuit (example 3): When the condition of VLED is Vf + 0.7 < VLED < 17 V. VOUT = VLED − Vf = 0.7 to 1.0 V is the most suitable for VOUT. Surplus VOUT causes an IC fever and the useless consumption electric power. It is the one way of being effective to build in the r3 in this problem. r3 can make a calculation to the formula r3 (ohms) = surplus VOUT/IOUT. Though the resistance parts increase, the fixed constant current performance is kept. 8bit SIPO, Latches and Constantsinkcurrent drivers TB62725BPG/BFG/BFNG C.U. SERIALIN ENABLE LATCH CLOCK SCAN r1 = 100 Ω VLED = 15 V SERIALOUT SERIALOUT r1 = 100 Ω Example) TD62M8600: 8bit multichip PNP transistor array, which is not used in static lighting system. SERIALIN ENABLE LATCH CLOCK 8bit SIPO, Latches and Constantsinkcurrent drivers TB62725BPG/BFG/BFNG
20050420 Notes Operation may become unstable due to the electromagnetic interference caused by the wiring and other phenomena. To counter this, it is recommended that the IC be situated as close as possible to the LED module. If overvoltage is caused by inductance between the LED and the output terminals, both the LED and the terminals may suffer damage as a result. There is only one GND terminal on this device when the inductance in the GND line and the resistor are large, the device may malfunction due to the GND noise when output switching by the circuit board pattern and wiring. To achieve stable operation, it is necessary to connect a resistor between the REXT terminal and the GND line. Fluctuation in the output waveform is likely to occur when the GND line is unstable or when a capacitor (of more than 50 pF) is used. Therefore, take care when designing the circuit board pattern layout and the wiring from the controller. This application circuit is a reference example and is not guaranteed to work in all conditions. Be sure to check the operation of your circuits. This device does not include protection circuits for over voltage, over current or over temperature. If protection is necessary, it must be incorporated into the control circuitry. The device is likely to be destroyed if a shortcircuit occurs between either of the power supply pins and any of the output terminals when designing circuits, pay special attention to the positions of the output terminals and the power supply terminals (VDD and VLED), and to the design of the GND line.
20050420 Package Dimensions Weight: 1.11 g (typ.)
20050420 Package Dimensions Weight: 0.14 g (typ.)
20050420 Package Dimensions Weight: 0.07 g (typ.)
20050420 TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice. 000707EBA RESTRICTIONS ON PRODUCT USE About solderability, following conditions were confirmed Solderability Use of Sn63Pb solder Bath ∙ solder bath temperature = 230°C ∙ dipping time = 5 seconds ∙ the number of times = once ∙ use of Rtype flux Use of Sn3.0Ag0.5Cu solder Bath ∙ solder bath temperature = 245°C ∙ dipping time = 5 seconds ∙ the number of times = once ∙ use of Rtype flux