TB62718AFG

TB62718AFG MARKTECH | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 31

Technical content

Input signal voltage level: CMOS level (Schmitt trigger input) Power supply voltage range VDD = 4.5 V~5.5 V Maximum output pin voltage: 26 V Serial and parallel data transfer rate: 20 MHz (max, cascade connection) Operating temperature range Topr = −40°C~85°C Warnings Short-circuiting an output pin to GND or to the power supply pin may destroy the device. Take care when wiring the output pins, the power supply pin and the GND pins (VSS, VSS2). Do not apply either positive or negative voltages to the heat sink on the surface of the IC. In addition, do not solder anything to the heat sink.

Pin Assignment (top view) and Markings Note: Indicates device name on the upper surface of the package. Indicates weekly code on the lower surface of the package. Details of weekly code on lower surface: From left, 1st character = rightmost digit of year 0 for 2000, 1 for 2001 2nd and 3rd characters = week of manufacture during year: maximum value = 52. 4th characters = manufacturing factory (‘K’ means the Kita Kyushu factory.) 5th to 7th characters = lot number within week 1st lot is A11, 2nd lot is A1 and 3rd lot is A. 4th lot is B11, 5th lot is B1 and 6th lot is B. 64th lot is Z11, 65th lot is Z1 and 66th lot is Z. The four characters of ‘I’, ‘M’, ‘O’ and ‘W’ are not used. OUT 01 OUT 02 OUT 03 OUT 04 OUT 05 OUT 06 OUT 07 VSS2 VSS2 OUT 08 OUT 09 OUT 10 OUT 11 OUT 12 OUT 13 OUT 14 VSS SO DATA TSENA TEST0 RESET LED TEST BLANK REXT SI SEL PWMCLK BCEN DCEN DOE SI DATA SI CLK SI LATCH PI SEL PI LATCH PI CLK VSS PI DATA 01 PI DATA 02 PI DATA 03 PI DATA 04 PI DATA 05 PI DATA 06 PI DATA 07 PI DATA 08 VDD NC VSS2 OUT 00 TEST1 ALARM1 ALARM2 VSS PO DATA 00 PO DATA 01 PO DATA 02 PO DATA 03 PO DATA 04 PO DATA 05 PO DATA 06 PO DATA 07 VDD NC VSS2 OUT 15 TB62718AFG 5WWKA**

Block Diagram (entire device) 3-bit Clock counter 8-bit clock counter PWM pulse generator circuit (8 bits) V/I conversion circuit TSD2 circuit TSD1 circuit Output-open detection circuit 128 16 × 6 bit DACs and 16 constant-current outputs DAC4 1 × 5-bit DAC DAC3 1 × 2-bit DAC DAC1 1 × 6-bit DAC DAC2 Each dot adjustment data register & latch (1 × 128 bits) SI REG2 Standard current adjustment data register & latch (1 × 8 bits) SI REG1 All dot adjustment data register & latch (1 × 8 bits) PI REG1 PWM data register & latch (16 × 8 bits) PI REG2 BCEN PI CLK PI SEL PI DATA 00 ~PI DATA 07 PWMCLK SI DATA PI LATCH DCEN DOE PO DATA 00 ~PO DATA 07 OUT 00~OUT 15 BLANK LED TEST ALARM2 ALARM1 TSENA SI CLK For PI REG1, PI REG2, SI REG1 and SI REG2 SI LATCH SO DATA REXT RESET SI SEL

Constant Current Adjustment Range (graph) This graph shows how current may be adjusted to a fraction of its full-scale value. Note 1: In each case, the value input to each DAC is the value output from the previous DAC. Reference: Current adjustment functions DAC1 to DAC3 are the current adjustment functions for all outputs. The adjustment width of DAC1 is large and approximate (1 LSB − 25%). The adjustment width of DAC2 is the smallest and has a large error (1 LSB ∼ − 0.9%). The adjustment width of DAC3 is small. DAC3 is a high-performance DAC with a small error (1 LSB ∼ − 1.61%). Therefore, It is recommended that DAC1 and DAC2 be used for adjusting the REXT resistance. It is recommended that DAC3 be used for adjusting brightness between module. (after it was set and it had DAC4 adjusted to the dot.) The beginning is set in about 75% of the middle value, after that, it is effective to use ±25% of set width. DAC4 is the current adjustment function for all outputs. The adjustment width of DAC4 is small. But it is a high-performance DAC with a small error (1 LSB ∼ − 1.27%). And also, DAC4 has a very wide setting range. Therefore, DAC4 can be used to adjust the brightness of LEDs without a rank classification. This method allows brightness to be adjusted with a degree of accuracy of 1.27% of full scale. Note 2: Assuming precise linear correlation between output current and LED brightness

Equivalent Input and Output Circuits (resistance values are typical values.) Input pins with pull-up resistor TSENA, BLANK, BC/DCEN Input pins with pull-down resistor. SI/PI LATCH, PI DATA 00~PI DATA 07, LED TEST Input terminals (A) SI DATA, SI CLK, PI CLK, PWMCLK (B) RESET , DOE , PI SEL, SI SEL Output terminals PO DATA 00~PO DATA 07, SO DATA (A) Rin = 250 Ω (B) Rin = 1 kΩ Protection circuit monitor terminals Constant-current output terminals VDD IN GND 1 kΩ R (DOWN) = 300 kΩ VDD IN GND 1 kΩ R (UP) = 300 kΩ VDD GND 100 Ω OUT Parasitic diode OUT 00~OUT 15 VSS2 VSS Parasitic diode ALARM1 & ALARM2

Explanation of Pin Functions Table No. Name I/O Function Explanation 4, 45 VSS P Logic ground pins. Be sure to use all. 35, 14 NC Unused TSENA I Pull- up This pin is used to reset the IC’s built-in temperature monitoring circuit (TSD). Rising edge of input signal re-enables outputs which had been forced to OFF. The latched data as the setting is not reset. Either in case of H- or L-level of this terminals can be operated TSD circuit. 15, 24, 25, 34 VSS2 P Ground pin for output. Be sure to use all. 13, 36 VDD P Logic power supply input pins. Be sure to use all. 16~23, 26~33 OUT 00~ OUT 15 O LED drive output pins. Connect to cathode of LED. SI DATA I Serial data input pin. Used for input of standard current adjustment data and dot adjustment data SI CLK I Serial data transfer clock input pin. Data is transferred positive edge. SI LATCH I Pull- down Serial data latch signal input pin. Data is held on positive edge. SI SEL I Serial data selection pin. Either standard current adjustment data or dot adjustment data may be selected. SO DATA O Serial data output pin. The output data type is selected using SI SEL. 37~44 PI DATA 00~ PI DATA 07 I Pull- down Input pins for parallel data. Inputs for all output adjustment data and PWM data PI CLK I Input pin for parallel data transfer clock. Data is transferred on positive edge. PI LATCH I Pull- down Input pin for parallel data latch signal. Data is held on rising positive edge. PI SEL I Parallel data selection pin. Either all output adjustment data or PWM data may be selected. 5~12 PO DATA 00~ PO DATA 07 O Output pin for parallel data. The output data type is selected using PISEL. DOE I Control pin for parallel data output PODATA. PIDATA is out on input of an H-level signal. PIDATA is set to High-impedance by input of an L-level signal. BLANK I Pull- up PWM circuit control signal input pin. Output is turn OFF by input of an H-level signal. PWM output is initiated by input of an L-level signal accordingly to the input data. PWMCLK I Standard clock input pin for PWM circuit. One clock cycle is equivalent to the minimum pulse width of the PWM output. BCEN I Pull- up Selection signal input pin for all output adjustment functions. All output adjustment is fixed to 100% when this signal is Low. All bit adjustments become effective when it is High. It isn’t influent anything to all output adjustment by PWMCLK. DCEN I Pull- up Selection signal input pin for dot adjustment function. Dot adjustment value is fixed to 100% when this signal is Low. Dot adjustment becomes effective when it is High. RESET I Reset signal input pin. Setting and registered data are reset when it is Low. A reset also releases TSD. LED TEST I Pull- down Connection confirmation signal input pin for an LED. When this signal is High, all outputs are ON. This signal should normally be kept Low. REXT P Connection pin of resistor for setting for the current. ALARM1 O Open-drain monitor pin for TSD circuit. When the TSD circuit detects an abnormal temperature, this signal is turned ON. IO monitor the TSD circuit connect this pin to a pull-up resistor. ALARM1 is independent of the RESET signal. ALARM2 O Open-drain monitor pin for output-open detection circuit. When an open output is detected, this signal is turned ON. 1, 64 TEST 0, TEST 1 I Pins for the device testing. Connect all these pins to ground. Pin attributes P: power supply/ground/other, I: input pin, O: output pin Note 3: It is recommended that pins with pull-up or pull-down resistors not be left open. Ambient noise may cause malfunction of the device.

Absolute Maximum Ratings (Topr = 25°C unless otherwise specified) Characteristics Symbol Rating Unit Supply voltage VDD −0.3~7 V Constant-current output voltage VO −0.3~26 V Output current IOUT mA/bit Logic output voltage VOUT −0.3~ VDD + 0.3 V Logic input voltage VIN −0.3~VDD + 0.3 V Total VSS2 current (Note 5) IVSS2 1.44 A When device mounted on PCB (Note 6) 1.19 Power dissipation When device mounted on PCB of any size Pd (Note 4) 5.0 W When device mounted on PCB (Note 6) θ (j-a) 102 Saturation heat resistance of package When device mounted on PCB of any size θ (j-c) °C/W Operating temperature Topr −40~85 Storage temperature Tstg −55~150 Note 4: If the operating temperature exceeds 25°C, derate the power dissipation rating by 0.95 mW/°C. Note 5: All four VSS2 pins must be connected. If not, device characteristics cannot be guaranteed. Note 6: When device mounted on PCB with dimensions 100 mm × 100 mm × 1.6 mm Recommended Operating Conditions (VDD = 4.5 V~5.5 V, Topr = −40°C~85°C unless otherwise specified) Characteristics Symbol Conditions & Pins Min Typ. Max Unit Supply voltage VDD 4.5 5.0 5.5 V High-level input voltage VIH PI DATA, PI CLK, PI SEL, PI LATCH, SI DATA, SI CLK, SI SEL, SI LATCH, PWM CLK 0.7 VDD VDD V Low-level input voltage VIL BLANK, LED TEST, TSENA, DOE, DCEN, BCEN VSS 0.3 VDD V High-level output current IOH PO DATA 00~PO DATA 07, SO DATA mA Low-level output current IOL VDD = 4.5 V, ALARM1, ALARM2 mA Constant-current output IOUT OUT 00~OUT 15 mA/bit VOUT OUT 00~OUT 15 OFF V Output voltage VOH ALARM1, ALARM2 OFF V Operating temperature Topr −40

Recommended Operating Conditions (continue) (VDD = 4.5 V~5.5 V, Topr = −40°C~85°C unless otherwise specified) Characteristics Symbol Condition & Terminals Min Typ. Max Unit fPWM Ratio of High-level: Low level = 50%, PWM CLK fPI1 PI CLK, fPI2 PI CLK, connected in cascade fSI1 SI CLK Clock frequency fSI2 SI CLK, connected in cascade MHz PWM CLK twH/twL PI CLK, SI CLK twltH/twltL PI LATCH, SI LATCH twrstH/twrstL RESET twblkH/twblkL BLANK 400 Minimum pulse width twledH/twledL LED TEST 400 ns PI DATA → PI CLK PI LATCH → PI CLK SI DATA → SI CLK SI LATCH → SI CLK Set-up time tsetup SI LATCH → SI CEL ns PI DATA → PI CLK PI LATCH → PI CLK SI DATA → SI CLK SI LATCH → SI CLK Hold time thold SI LATCH → SI CEL ns

Electrical Characteristics 1 (VDD = 4.5 V~5.5 V, Topr = −40°C~85°C, typ: VDD = 5.0 V, Topr = 25°C) Parameter Symbol Test conditions & Terminals Min Typ. Max Unit High-level output voltage VOH IOH = −1.0 mA, PO DATA 00~PO DATA 07, SO DATA VDD −0.4 V IOL = 1.0 mA, PO DATA 00~PO DATA 07, SO DATA 0.4 Low-level output voltage VOL IOL = 1.0 mA, ALARM1, ALARM2 0.3 V Tri-state output leakage current IOZ VOUT = VDD or VSS, PO DATA 00~PO DATA 07 ±0.5 µA Input current II All pins without pull-up/pull-down resistors µA IDD1 PI DATA = 1/2 PI CLK SI DATA = 1/2 SI CLK PI CLK = SI CLK = 20 MHz PWMCLK = L, BLANK = H Settings: *1 IDD2 PI DATA = SI DATA = L PI CLK = SI CLK = L PWMCLK = 20 MHz Settings: *5a 105 IDD3 PI DATA = 1/2 PI CLK SI DATA = 1/2 SI CLK PI CLK = SI CLK = PWMCLK = 20 MHz Settings: *5a 115 IDD4 PI DATA = SI DATA = L PI CLK = SI CLK = L PWMCLK = 20 MHz Settings: *6a 140 Supply current IDD5 PI DATA = 1/2 PI CLK SI DATA = 1/2 SI CLK PI CLK = SI CLK = PWMCLK = 20 MHz Settings: *6a 150 mA Electrical Characteristic Settings (OUT 00~OUT 15 all on, VOUT = 0.7 V and REXT = 2.7 kΩ unless otherwise specified) No. DAC Settings Surface Brightness Adjustment (DAC3) Constant Output Current (typ.) Outputs all OFF, VOUT = 26 V, DAC1, 2, 4 = MSB, BLANK = H IOUT = 0 mA DAC1 = 0, DAC2 = 0, DAC4 = 63, BLANK = L IOUT = 7.10 mA ∗3a DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L IOUT = 10.0 mA ∗4a DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L IOUT = 19.9 mA ∗5a DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L IOUT = 40.1 mA ∗6a DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L IOUT = 60.2 mA DAC1 = 3, DAC2 = 63, DAC4 = 63, BLANK = L DAC3 = 31 IOUT = 71.0 mA ∗3b DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L IOUT = 5.0 mA ∗4b DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L IOUT = 10.0 mA ∗5b DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L IOUT = 20.0 mA ∗6b DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L DAC3 = 00 IOUT = 30.1 mA

Electrical Characteristics 2 (VDD = 4.5 V~5.5 V, Topr = −40°C~85°C, typ: VDD = 5.0 V, Topr = 25°C) Parameter Symbol Test Conditions Min Typ. Max Unit IOUT1 Settings *7 60.4 71.0 81.6 IOUT2 Settings *6a 51.2 60.2 69.2 IOUT3 Settings *5a 34.1 40.1 46.1 IOUT4 Settings *4a 16.5 19.9 23.2 IOUT5 Settings *3a 7.8 10.0 12.2 Constant-current output IOUT6 Settings *2 4.54 7.1 9.65 V %TOPR1 Settings *6a, VOUT = 1.0 V, Topr is varied in the range −40°C~85°C. ±50 ±80 Constant-current output Depends on temperature %TOPR2 Settings *4a, VOUT = 1.0 V, Topr is varied in the range −40°C~85°C. ±25 ±50 µA/°C Leakage current for constant-current output IOLK Settings *1, VOUT = 26 V 0.05 0.1 µA ∆IOUT1 Settings *6a, VOUT = 0.7 V ±2.5 ∆IOUT2 Settings *5a, VOUT = 0.7 V ±3.5 ∆IOUT3 Settings *4a, VOUT = 0.7 V ±5.5 Constant current accuracy between bits ∆IOUT4 Settings *3a, VOUT = 0.7 V ±12 %IOUT1 Settings is changed from *6a to *6b. %IOUT2 Settings is changed from *5a to *5b. ±1.5 %IOUT3 Settings is changed from *4a to *4b. ±3.5 Dot adjustment deviation between bits (when DAC3 data were changed from MSB to LSB.) %IOUT4 Settings is changed from *3a to *3b. ±12 Settings *6a, VOUT is varied in the range 0.7 V~3 V. Constant-current output depends on output voltage %VOUT Settings *4a, VOUT is varied in the range 0.7 V~3 V. Constant-current output depends on supply voltage %VDD Settings *6a, VDD is varied in the range 4.5 V~5.5 V. Tsd1 120 140 160 TSD detection temperature Tsd2 140 160 180 Output-open detection voltage VARL ALARM2 0.04 VDD V Pull-up/down resistor Rup/Rdw 150 300 600 kΩ Electrical Characteristic Settings (OUT 00~OUT 15 all on, VOUT = 0.7 V and REXT = 2.7 kΩ unless otherwise specified) No. DAC Settings All Dot Adjustment (DAC3) Constant Output Current (typ.) OUT00~15 OFF, VOUT = 26 V, DAC1~4 = MSB, BLANK = H IOUT = 0 mA DAC1 = 0, DAC2 = 0, DAC4 = 63, BLANK = L IOUT = 7.10 mA ∗3a DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L IOUT = 10.0 mA ∗4a DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L IOUT = 19.9 mA ∗5a DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L IOUT = 40.1 mA ∗6a DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L IOUT = 60.2 mA DAC1 = 3, DAC2 = 63, DAC4 = 63, BLANK = L DAC3 = 31 IOUT = 71.0 mA ∗3b DAC1 = 0, DAC2 = 17, DAC4 = 63, BLANK = L IOUT = 5.0 mA ∗4b DAC1 = 1, DAC2 = 17, DAC4 = 63, BLANK = L IOUT = 10.0 mA ∗5b DAC1 = 2, DAC2 = 37, DAC4 = 63, BLANK = L IOUT = 20.0 mA ∗6b DAC1 = 3, DAC2 = 51, DAC4 = 63, BLANK = L DAC3 = 00 IOUT = 30.1 mA

(VDD = 4.5 V~5.5 V, Topr = −40°C~85°C, CL = 50 pF unless otherwise specified, typ: VDD = 5.0 V, Topr = 25°C, CL = 50 pF) Parameter Symbol Test Conditions Min Typ. Max Unit Tri-state output enable propagation delay tpZH/ZL DOE → PO DATA0~ PO DATA 7 ns Tri-state output disable propagation delay tpHZ/LZ DOE → PO DATA0~ PO DATA 7 ns OUT00~ OUT 15 µs Rise time tr ALARM1, ALARM2 0.2 0.4 0.8 ns OUT00~ OUT 15 Fall time tf ALARM1, ALARM2 ns tpHL BLANK → OUT00~ OUT 15 120 tpLH PWM CLK → OUT00~ OUT 15 120 200 tpHL PWM CLK → OUT00~ OUT 15 140 tpLH 110 190 tpHL LED TEST → OUT00~ OUT 15 130 tpHL RESET → OUT00~ OUT 15 130 PI CLK → PO DATA0~ PO DATA 7 PI SEL → PO DATA0~ PO DATA 7 SI SEL → SO DATA Propagation delay tpd SI SEL → SO DATA ns

Explanation of Operation and Truth Tables Serial data transfer: standard current adjustment using DAC1 and DAC2 (data register SI REG [7:0]) Process SI DATA SI CLK SI LATCH SI SEL SO DATA Operation and Function (×8) L H H or L Selects standard current adjustment (8 bits, 2 bits and 6 bits) for input data when SI SEL is high. Data is transferred to SI REG [1] on 8th positive edge of SI CLK input. H or L L (×1) H No change Holds the data transferred to SI REG [1] on positive edge of SI LATCH. Set is reflected on standard current adjustment from the moment when it is held. Serial data transfer timing (standard current adjustment, SI SEL = H, single device) Serial data transfer timing (standard current adjustment, SI SEL = H, two devices connected in cascade) RESET SI SEL SI DATA SI CLK SI LATCH SO DATA (1st device) Data reset by RESET = L Data held on positive edge of SI LATCH after the data transfer by single device (after 8 clock cycles) SODATA is synchronized with 8th clock cycle after reset, and the first data is output. Indicates undefined logic state after reset and before input. RESET SI SEL SI DATA SI CLK SI LATCH SO DATA (1st device) Data reset by RESET = L Data held on positive edge of SI LATCH after the data transfer by two devices (after 16 clock cycles) SODATA is synchronized with 8th clock cycle after reset, and the first data is output. Indicates undefined logic state after reset and before input.

Serial data transfer: dot adjustment DAC4. (data register SI REG2 [127:0]) Process SI DATA SI CLK SI LATCH SI SEL SO DATA Operation and Function (×128) L L H or L Selects dot adjustment (128 bits) for input data. Data is transferred to SI REG2 on 128th positive edge of SI CLK. H or L L (×1) L No change Holds the data transferred to SI REG2 on positive edge of SILATCH. Set is reflected on dot adjustment from the moment when it is held. Serial data transfer timing (dot adjustment, SI SEL = L, single device) Serial data transfer timing (dot adjustment, SI SEL = L, two devices connected in cascade) RESET SI SEL SI DATA SI CLK SI LATCH SO DATA (1st device) Data reset by RESET = L Data held on positive edge of SI LATCH after data transfer by two devices (after 256 clock cycles) SODATA is synchronized with 128th clock cycle after reset, and the first data is output. Indicates undefined logic state after reset and before input. There pairs of bits are Don’t care. Dot adjustment data for OUT 15 (1st device). Dot adjustment data for OUT 00 (1st device). Dot adjustment data for OUT 15 (2nd device). Dot adjustment data for OUT 00 (2nd device). RESET SI SEL SI DATA SI CLK SI LATCH SO DATA (1st device) Data reset by RESET = L Data held on positive edge of SI LATCH after data transfer by single device (after 128 clock cycles) SODATA is synchronized with 128th clock cycle after reset, and the first data is output. Indicates undefined logic state after reset and before input. There pairs of bits are Don’t care. Dot adjustment data for OUT 15 (1st device). Dot adjustment data for OUT 00 (1st device).

DAC1: Standard current adjustment settings for DAC1 (SI REG1 [7:6]) RESET SI SEL SI REG (7:6) SI REG (5:0) Current Rate Operation and Function Notes H H HH XXXXXX 100% (1.0) 100% of base current setting as determined by REXT (Ω) H H HL XXXXXX 75% (0.75) 75% of base current setting as determined by REXT (Ω) H H LH XXXXXX 50% (0.5) 50% of base current setting as determined by REXT (Ω) H H LL XXXXXX 25% (0.25) 25% of base current setting as determined by REXT (Ω) X LL LLLLLL 25% (0.25) Initial state after input of reset signal: 25% of base current setting as determined by REXT (Ω) (as described above) When SI SEL = H, 2 bits on MSB sides are corresponding to set of standard current adjustment DAC1. The output current can be set to one of 4 levels. DAC2: Standard current adjustment settings for DAC2 (SI REG1 [5:0]) RESET SI SEL SI REG (7:6) SI REG (5:0) Current Rate Operation and Function Notes H H XX XXXXXX 100% (1.0) 100% of base current value as set using DAC1 base current adjustment H H XX HHHHHL LLLLLH (0.9905) 1LSB = ±0.95% (±0.0095) (0.4095) Any one or 64 levels in the range 40%~100% of the current can be set. (1 LSB = 0.95%) 6-bit DAC performance 1LSB variation: ±0.95% Non linearity error: ±1/2LSB Differential non linearity error: ±3/4LSB H H XX LLLLLL 40% (0.4) 40% of base current value as set using DAC1 base current adjustment X LL LLLLLL 40% (0.4) Initial state after input of reset signal: 40% of base current value set as described above When SI SEL = H, 6 bits on MSB sides are corresponding to set of standard current adjustment DAC2. The output current can be set to one of 64 levels. DAC4: Set details of dot adjustment DAC4 (SI REG2 [127:0]) RESET SI SEL DCEN About 8 bits Unit of SI REG2 [127:0] Current Rate Operation and Function Notes H L H XXHHHHHH 100% (1.0) Output current is 100% of base current value as set using DAC1 and DAC2 base current adjustment and DAC3 surface brightness adjustment H L H XXHHHHHL XXLLLLLH (0.9874) 1LSB = ±1.269% (±0.0126) (20.0126) Any one of 64 levels in the range 20%~100% of the current can be set. (1LSB ∼ − 1.27%) 6-bit DAC performance 1LSB variation: ±1.269% Non linearity error: ±1/2LSB Differential non linearity error: ±1/2LSB H L H XXLLLLLL 20% (0.2) 20% of base current value as set using DAC3 surface brightness adjustment X H XXLLLLLL 20% (0.2) Initial state after input of reset signal: 20% of base current value set as described above When SI SEL = L 8 bits out of 128 bits are corresponding to set of each output, and the 6 bits on MSB sides of 8 bits are data on dot adjustment. The output current can be set to one of 64 levels. SI REG2 [7:0] → adjustment data for OUT 00. SI REG2 [15:8] → adjustment data for OUT 01. SI REG2 [127:120] → adjustment data for OUT 15. H X L XXHHHHHH 100% (1.0) Output current is 100% of base current value set as described above. Data input is still enabled if DCEN = L. If DCEN = H, adjustment is performed at the same time.

Polarity of serial input data for standard current adjustment (SI REG1 [7:0]) and dot adjustment (SI REG2 [127:0]) Serial data transfer timing (SI SEL = H, input of standard current adjustment data for DAC1 and DAC2) Serial data transfer timing (SI SEL = L, input of dot adjustment data for DAC4) SI REG2 (127) MSB SO DATA Dot adjustment data (6 bits) × × SI DATA SI LATCH SI REG2 (0) LSB DAC4 (6-bit DAC) OUT 00 × × DAC4 (6-bit DAC) OUT 15 SI REG2 (7) SI REG2 (120) Not used Dot adjustment data (6 bits) Not used D-F/F D-LAT D-F/F D-LAT D-F/F D-LAT D-F/F D-LAT D-F/F D-LAT D-F/F D-LAT D-F/F D-LAT D-F/F D-LAT SI DATA SI LATCH SI REG1 (0) LSB SI REG1 (7) MSB SO DATA Standard current adjustment data (6 bits) Standard current adjustment data (2 bits)

Parallel data transfer: All dot adjustment DAC3. (data register PI REG1 [7:0]) Process PI DATA [7:0] PI CLK PI LATCH PI SEL PO DATA [7:0] Operation and Function (×1) L H H or L Selects total dot adjustment (8-bit, 3-bit and 5-bit) for input data. Data is transferred to PI REG1 on 128th positive edge of PI CLK. H or L L (×1) H No change Holds the data transferred to PI REG1. Set is reflected on all dot adjustment from the moment when it is held. Parallel data transfer timing (all dot adjustment, PI SEL = H, single device) Parallel data transfer timing (all dot adjustment, PI SEL = H, two devices connected in cascade) RESET PI SEL PI DATA [7:0] PI CLK PI LATCH PO DATA [7:0] Data held on positive edge of PI LATCH after data transfer by single device (after 1 clock cycle) PO DATA is synchronized with 1st clock cycle after reset, and the first data is output. Indicates undefined logic state after reset and before input. 111_11111 000_00000 111_11111 RESET PI SEL PI DATA [7:0] PI CLK PI LATCH PO DATA [7:0] (1st device) Data held on positive edge of PI LATCH after the data transfer by two devices (2 clock cycles) PO DATA is synchronized with 1st clock cycle after reset, and the first data is output. Indicates undefined logic state after reset and before input. 110_11110 000_00000 110_11110 111_11111 111_11111 101_11101 PO DATA is synchronized with 2nd clock cycle after reset, and the second data is output.

Parallel data transfer PMW display data (data register PI REG2 [127:0]) Process PI DATA PI CLK PI LATCH PI SEL PO DATA Operation and Function (×16) L L H or L Selects for input data of PWM display data (8 bit × 16). Data is transferred to PI REG2 on 16th positive edge of PI CLK. H or L L (×1) L No change Holds the data transferred to PI REG2. Set is reflected on PWM 256 grayscales from the next BLANK = L when it is held. Parallel data transfer timing (PWM data PI SEL = L, single device) Parallel data transfer timing (PWM data PI SEL = L, two devices connected in cascade) PO DATA [7:0] RESET PI SEL PI DATA [7:0] PI CLK PI LATCH Data held on positive edge of PI LATCH after data transfer by single device (after 1 clock cycle) PO DATA is synchronized with 16th clock cycle after reset, and is output. Indicates undefined logic state after reset and before input. PWM data for OUT 15 01H 02H 01H 00H 00H PWM data for OUT 00 0EH 0FH RESET PI SEL PI DATA [7:0] PI CLK PI LATCH Data held on positive edge of PI LATCH after data transfer by two devices (32 clock cycles) PO DATA is synchronized with 16th clock cycle after reset, and the first data is output. Indicates undefined logic state after reset and before input. PWM data for OUT 15 (1st device) 02H 00H 00H 0EH 0FH 00H 01H 02H 0EH 0FH 10H 01H 10H 02H 01H 0FH 10H 01H PO DATA [7:0] (1st device) PWM data for OUT 00 (1st device)

Details all dot adjustment setting using PWMCLK division (PI REG1 [7:5]) RESET PI SEL BCEN PI REG1 [7:5] PWMCLK Divisor Operation and Function Notes H H H LLL PWM CLK = 8/8 PWMCLK (Hz) The period of PWMCLK is set to equal the change in the PWM pulse width data. 1LSB. H H H LLH HHL 7/8 PWMCLK to 2/8 PWMCLK Variable does the frequency of PWMCLK to 1/8 of the minimal. It is set in 8 levels. 6-bit DAC performance Maximum input: PWMCLK = 20 MHz H H H HHH PWMCLK = 1/8 PWMCLK (Hz) The period of PWMCLK is set to one-eighth the change in the PWM pulse width data. 1 LSB. X H LLL PWMCLK = 8/8 PWMCLK (Hz) The period of PWMCLK is set to equal the change in the PWM pulse width data. 1 LSB. When PI SEL = H is selected, 3 bits on MSB sides are corresponding to set of standard current adjustment by PWM frequency dividing. PI REG [7:5] varies the pulse width of PWM data corresponding to 1 LSB for eight levels and adjusts brightness. This setting values affects pulse widths on all outputs. H H L XXX Unchanged BCEN signal does not affect PWMCLK frequency dividing. Data input is still enabled if BCEN = L. Output current level reflects input settings. DAC3: Details of all dot adjustment setting for DAC3 (PI REG2 [4:0]) RESET PI SEL PI REG1 [4:0] BCEN Current Rate Operation and Function Notes H H HHHHH H 100% (1.0) 100% of base current value as set using DAC1 and DAC2 current adjustment and DAC4 dot adjustment H H HHHHL LLLLH H (0.9839) 1LSB = ±1.61% (±0.0161) (0.5161) Any one of 32 levels in the range 50%~100% of the current can be set. (1 LSB = 1.61%) 5-bit DAC performance 1LSB variation: ±1.61% Non linearity error: ±1/2LSB Differential non linearity error: ±1/2LSB (No guarantee for monotonicity) H H LLLLL H 50% (0.5) 50% of base current value as set using DAC1 and DAC2 current adjustment and DAC4 dot adjustment X HHHHH H 100% (1.0) Initial state after input of reset signal: 100% of base current value set as described above When PI SEL = H is selected, 5 bits on LSB side are corresponding to set of surface brightness adjustment. The output current can be set to one of 32 levels. H X HHHHH L 100% (1.0) Initial state after input of DCEN signal: 100% of base current value set as described above Data input is still enabled if BCEN = L. If BCEN = H, adjustment is performed at the same time.

Detailed PWM 256 grayscales setting (PI REG2 [127:0], 16 × 8 bits) RESET PI SEL 1 word (8 bits) of PI REG2 Output Pulse Rate Operation and Function Notes H L HHHHHHHH 100% Output pulse width is at its maximum value when input data is FF. H L HHHHHHHL LLLLLLLH The input data can be used to control the PWM pulse width and hence generate 256 grayscales. H L LLLLLLLL Outputs are OFF when the input data is 00. X LLLLLLLL Early condition after the reset signal input is set in 0/256 (output off). When PI SEL = L, The PWM grayscale controls the output pulse width. 16 × 8-bit words are transferred in parallel. 1 word is the PWM data of each output pulse width is set in 256 step. PI REG2 [7:0] → PWM data for OUT 00. PI REG2 [15:8] → PWM data for OUT 01. PI REG2 [127:120] → PWM data for OUT 15. Minimum output pulse width is 1/PWMCLK. Polarity of serial input data for all dot adjustment (PI REG [7:0]) and PWM 256 grayscales (PI REG2 [127:0]) Parallel data transfer timing (PI SEL = H, selects data input for all dot adjustment for DAC3.) (PI SEL = L, selects data input for PWM 256 grayscales.) PI DATA [7] PO DATA [7] PI REG1 [7] MSB LSB PI REG1 [0] PI DATA [0] PI LATCH PO DATA [0] All dot adjustment by division by PWMCLK All dot adjustment by DAC3 PI DATA [7] PI REG2 [7] MSB LSB PI REG2 [0] PI DATA [0] PI LATCH PWM pulse data PWM pulse generator circuit PO REG2 [127] MSB PWM pulse data PWM pulse generator circuit LSB PI REG2 [120] PO DATA [7] PO DATA [0] OUT 00 OUT 15

Reference table: output current setting vales (1) DAC1 (2-bit) DAC2 (6-bit) DAC3 (5-bit) DAC4 (6-bit) No. Input Data Current Rate1 No. Input Data Current Rate2 No. Input Data Current Rate3 No. Input Data Current Rate4 1.00 111111 1.000 11111 1.000 111111 0.75 111110 0.990 11110 0.984 111110 0.50 111101 0.981 11101 0.968 111101 00 0.25 111100 0.971 11100 0.952 111100 111011 0.962 11011 0.936 111011 111010 0.952 11010 0.919 111010 111001 0.943 11001 0.903 111001 111000 0.933 11000 0.887 111000 110111 0.924 10111 0.871 110111 110110 0.914 10110 0.855 110110 110101 0.905 10101 0.839 110101 110100 0.895 10100 0.823 110100 110011 0.886 10011 0.807 110011 110010 0.876 10010 0.790 110010 110001 0.867 10001 0.774 110001 110000 0.857 10000 0.758 110000 101111 0.848 01111 0.742 101111 101110 0.838 01110 0.726 101110 101101 0.829 01101 0.710 101101 101100 0.819 01100 0.694 101100 101011 0.820 01011 0.677 101011 101010 0.800 01010 0.661 101010 101001 0.791 01001 0.645 101001 101000 0.781 01000 0.629 101000 100111 0.771 00111 0.613 100111 100110 0.762 00110 0.597 100110 100101 0.752 00101 0.581 100101 100100 0.743 00100 0.565 100100 100011 0.733 00011 0.549 100011 100010 0.724 00010 0.532 100010 100001 0.714 00001 0.516 100001 100000 0.705 00000 0.500 100000 011111 0.695 011111 011110 0.686 011110 011101 0.676 011101 011100 0.667 011100 011011 0.657 011011 011010 0.648 011010 011001 0.638 011001 011000 0.629 011000 010111 0.619 010111 010110 0.610 010110 010101 0.600 010101 010100 0.591 010100 010011 0.581 010011 010010 0.571 010010 010001 0.562 010001 010000 0.552 010000 001111 0.543 001111 001110 0.533 001110 001101 0.524 001101 001100 0.514 001100 001011 0.505 001011 001010 0.495 001010 001001 0.486 001001 001000 0.476 001000 000111 0.467 000111 000110 0.457 000110 000101 0.448 000101 000100 0.438 000100 000011 0.429 000011 000010 0.419 000010 000001 0.410 000001 000000 0.4 000000 Note 7: : Indicates post-reset initialization value ( = L). Note 8: The formula for calculating resistance settings is as follows: This value is theory value. Actual current value contains error and so on in this value. REXT [kΩ] = (1.9 × current rate 1 × current rate 2 × current rate 3 / output current [mA]) × (1 + (7 × current rate 4 / 105)) × 19.4 RESET

Reference table: output current setting value (2) Reference value for standard current adjustment under conditions: REXT = 2.7 kΩ (fixed), all dot adjustment = MSB and dot adjustment = MSB Unit: mA DAC2 7.1 7.3 7.4 7.6 7.8 7.9 8.1 8.3 8.5 8.6 8.8 9.0 9.1 9.3 9.5 9.6 14.2 14.5 14.9 15.2 15.6 15.9 16.2 16.6 16.9 17.2 17.6 17.9 18.3 18.6 18.9 19.3 21.3 21.8 22.3 22.8 23.3 23.8 24.3 24.9 25.4 25.9 26.4 26.9 27.4 27.9 28.4 28.9 DAC1 28.4 29.1 29.6 30.4 31.1 31.8 32.5 33.1 33.8 34.5 35.2 35.8 36.5 37.2 37.9 38.6 DAC2 9.8 10.0 10.1 10.3 10.5 10.7 10.8 11.0 11.2 11.3 11.5 11.7 11.8 12.0 12.2 12.3 19.6 19.9 20.3 20.6 21.0 21.3 21.6 22.0 22.3 22.7 23.0 23.3 23.7 24.0 24.3 24.7 29.4 29.9 30.4 30.9 31.4 32.0 32.5 33.0 33.5 34.0 34.5 35.0 35.5 36.0 36.5 37.0 DAC1 39.2 39.9 40.6 41.2 41.9 42.6 43.3 44.0 44.6 45.3 46.0 46.7 47.3 48.0 48.7 49.4 DAC2 12.5 12.7 12.9 13.0 13.2 13.4 13.5 13.7 13.9 14.0 14.2 14.4 14.5 14.7 14.9 15.0 25.0 25.4 25.7 26.0 26.4 26.7 27.0 27.4 27.7 28.1 28.4 28.7 29.1 29.4 29.8 30.1 37.5 38.0 38.6 39.0 39.6 40.1 40.6 41.1 41.6 42.1 42.6 43.1 43.6 44.1 44.6 45.1 DAC1 50.0 50.7 51.4 52.1 52.7 53.4 54.1 54.8 55.4 56.1 56.8 57.5 58.1 58.8 59.5 60.2 DAC2 15.2 15.4 15.6 15.7 15.9 16.1 16.2 16.4 16.6 16.7 16.9 17.1 17.2 17.4 17.6 17.8 30.4 30.8 31.1 31.4 31.8 32.1 32.5 32.8 33.1 33.5 33.8 34.1 34.5 34.8 35.2 35.5 45.6 46.1 46.7 47.2 47.7 48.2 48.7 49.2 49.7 50.2 50.7 51.2 51.7 52.2 52.7 53.2 DAC1 60.9 61.5 62.2 62.9 63.6 64.2 64.9 65.6 66.3 66.9 67.6 68.3 69.0 69.6 70.3 71.0

Temperature detection function (can be monitored via the ALARM1 pin.) Perform two-stage temperature detection as described in the table below (TSD1/TSD2). Junction Temperature [°C] ALARM1 OUT 00~OUT 15 Function −40~120 OFF Normal operation 120~ ON Normal operation When the chip temperature reaches the specified range the ALARM1 signal goes Low (TSD1), Other functions are not affected. 140~ ON OFF When the chip temperature reaches the specified range the ALARM1 signal goes Low and all output pins are turned OFF (TSD2). Outputs are re-enabled on the positive edge of TSENA or when the RESET signal goes Low. Neither of these causes the internal data to be reset. If RESET pin = L, all internal data is reset. Output-open detection function (can be monitored via the ALARM2 pin.) Reform output-open detection as described in the table below. Output Voltage [V] ALARM2 Function > = VDD × 0.04 OFF < = VDD × 0.04 ON The output-open condition is detected when the ARARM2 pin signal is ON and the specified voltage level is detected. (it is also detected when the output voltage falls to near GND for some reason) Pulse cancellation circuit (when monitored using output-open detection pin ARARM2.) PWMCLK ALARM2 Function Input signal Operating No input Always OFF The built-in pulse cancellation circuit is designed to prevent malfunction. However, if there is no input on PWMCLK, ALARM2 output will not be turned ON.

Block Diagram of Protection Circuit Protection circuit function Operating chart (terminal for TESNA, ALARM1 and outputs OUT 00~OUT 15) Junction Temperature (unit: °C) TSENA RESET Tj = 120°C TSD1 120 < = Tj = 160°C TSD2 140 < = Tj < = 180°C ALARM1 OUT 00 OUT 15 Function X L OFF ON Device reset X H OFF ON Outputs operate normally. X L ON ON Device reset X H ON Normal operation ALARM1 goes Low, indicating a rise in temperature. Outputs operate normally. X L ON OFF Even after a reset, if the junction temperature is high, outputs are turned OFF. X H ON OFF ALARM1 goes Low, indicating a rise in temperature. Outputs operate normally. Note 9: The internal operation of the TSD circuit is independent of the TSENA and RESET pin voltage levels. OUT00~OUT15 Constant- current output RESET LED TEST ALARM2 TSENA ALARM1 TSD2 TSD1 Output OFF Output ON Output-OFF condition is released and internal data is reset. Release of output OFF on positive edge Pulse cancel Output-open detection Continue one, open condition is detected.

Serial Data Input Timing Chart Note 10: Serial data input has no effect on the ON/OFF state of the outputs. When the SI LATCH signal holds the serial data, the output current values and output pulse width are affected. Parallel Data Input Timing Chart Note 11: The BLANK signal has not effect on parallel data input. The PWM pulse can be controlled using the BLANK signal. It is recommended that, on completion of data transfer, BLANK be set to High and outputs be turned OFF. Data of DAC3 for OUT 15 Output ON RESET SI DATA SI SEL SI LATCH SI CLK BLANK SO DATA Output OFF Data of DAC3 for OUT 00 Data of DAC1 to 2 The data read with 1st time Selects input of each dot adjustment data. Selects input of standard current adjustment data. The data read with 1st time SO DATA outputs standard current SO DATA outputs each dot adjustment data. Output ON & data transfer RESET PI DATA 00~ PI DATA 07 PI SEL PI LATCH PI CLK BLANK PO DATA 00~ PO DATA 07 Output OFF & data hold

1 Time

16 Times

The data read with 1st time Selects input of PWM data and output-ON data. Selects input of PWM data and output-ON data. The data read with 1st time DOE OUT 00~ OUT 15 High-Impedance High-Impedance OFF Output ON (output-OFF if PWM data = 0) PWM data for OUT 15 PWM data for OUT 00 for total dot adjustment Holds PWM data, output-ON data and total dot adjustment data. Selects input of total dot adjustment PO DATA 00~PODATA 07 output PWM data. PO DATA 00~PODATA 07 output PWM data. PO DATA 00~PODATA 07 output all bit adjustment data. Starts output of PWM data after synchronizing with rising edge of BLANK. Output ON & data transfer

PWM Operating Timing Chart and All Bit Adjustment Using Division by PWMCLK Note 12: PWM operation timing: PWM pulse output on the output pins is initiated when BLANK goes Low. (there is simultaneous output on all 16 pins) Output pulse only once toward BLANK signal’s changing once in L from H. Hence, if PWM data is to be re-used, BLANK must be pulled Low again. PWMCLK division: As shown in the central part of the upper figure, the brightness of the LED module can be set to any one of eight levels without adjusting the current value, simply by dividing by PWMCLK. For large-scale brightness adjustment, division by PWMCLK is recommended. Output can be turned ON. RESET BLANK Output can be turned ON. OUT 00~ OUT 15 tBLANK (1) tBLANK (2) tBLANK (3) tBLANK (4) tBLANK (5) tBLANK (6) tBLANK (7) tBLANK (8) OFF ON OFF ON Minimum PWM control time tBLANK (8) = (1/ (8/8PWMCLK) ) × 256 tBLANK (6) = (1/ (6/8PWMCLK) ) × 256 tBLANK (5) = (1/ (5/8PWMCLK) ) × 256 tBLANK (4) = (1/ (4/8PWMCLK) ) × 256 tBLANK (3) = (1/ (3/8PWMCLK) ) × 256 tBLANK (2) = (1/ (2/8PWMCLK) ) × 256 Maximum PWM control time tBLANK (1) = (1/ (1/8PWMCLK) ) × 256 tBLANK (7) = (1/ (7/8PWMCLK) ) × 256 OUT 00~OUT 15 PWM data = 00 H OUT 00~OUT 15 PWM data = 01 H PWMCLK8 OUT 00~OUT 15 PWM data = 80 H PWMCLK8 OUT 00~OUT 15 PWM data = FE H PWMCLK8 Output OFF because data is 00H though it can on. Because data is 01 H output is ON with 1/255 of tBLANK. Because data is 80 H output is ON with 128/255 of tBLANK. Because data is 80 H output is ON with 254/255 of tBLANK. Output OFF, data change & hold Output OFF, data hold PWMCLK division

Logic Input and Output Timing Waveforms 1. PI CLK (SI CLK) vs. PI DATA [7:0] (SI DATA) PI CLK (SI CLK) vs. PO DATA [7:0] (SO DATA) 2. PI SEL (SI SEL) vs. PI CLK (SI CLK) 50% 50% 50% twH twL 50% 50% 50% 50% thold tpd tpd tsetup PI CLK (SI CLK) PI DATA [7:0] (SI DATA) PO DATA [7:0] (SO DATA) 50% 50% 50% twH twL 50% tsetup PI CLK (SI CLK) PI DATA [7:0] (SI DATA) PI SEL (SI SEL) 50% thold tsetup 50% thold

1. PI LATCH (SI LATCH) vs. PI CLK (SI CLK) 4. PI SEL (SI SEL) vs. PO DATA 00~PO DATA 07 (SO DATA) 5. DOE vs. PO DATA 00~PO DATA 07 50% 50% 50% twH twL PI CLK (SI CLK) PI DATA [7:0] (SI DATA) 50% thold tsetup (Internal flip-flop data) PI LATCH (SI LATCH) 50% 50% twltH twltL 50% tpd PI SEL (SI SEL) 50% PO DATA [7:0] (SO DATA) 50% 50% tpd DOE PO DATA [7:0] 50% tpzH/zL 50% tpzH/zL

Logic Input and Constant-current Output Timing Waveforms 1. BLANK vs. OUT 00~OUT 15 with PWMCLK 2. RESET vs. OUT 00~OUT 15 3. LED TEST vs. OUT 00~OUT 15 50% 50% BLANK PWMCLK OUT 00~OUT 15 (current waveform) 50% 50% 50% 50% tpLH tpHL twblkL twblkH Maximum delay time is 1 PWMCLK cycle. Maximum delay time is 1 PMCLK cycle. BLANK RESET OUT [15:0] (current waveform) 50% 50% 50% tpHL twrstL 50% LED TEST OUT 00~OUT 15 (current waveform) 50% 50% 50% tpLH twledH

Weight: 0.26 g (typ.)

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.
• The information contained herein is subject to change without notice. 000707EBA RESTRICTIONS ON PRODUCT USE About solderability, following conditions were confirmed
• Solderability Use of Sn-63Pb solder Bath
• solder bath temperature = 230°C
• dipping time = 5 seconds
• the number of times = once
• use of R-type flux Use of Sn-3.0Ag-0.5Cu solder Bath
• solder bath temperature = 245°C
• dipping time = 5 seconds
• the number of times = once
• use of R-type flux

WWW.ALLDATASHEET.COM Copyright © Each Manufacturing Company. All Datasheets cannot be modified without permission. This datasheet has been download from : www.AllDataSheet.com 100% Free DataSheet Search Site. Free Download. No Register. Fast Search System. www.AllDataSheet.com