TB62715FN TOSHIBA | Alldatasheet
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TENTATIVE TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC
8 BIT SHIFT REGISTER, LATCHES & CONSTANT CURRENT DRIVERS
The TB62715FN is specifically designed for LED and LED DISPLAY constant current drivers. This constant current output circuits is able to set up external resistor (IQUT = 70~150 mA). This IC is monolithic integrated circuit designed to be used together with Bi-CMOS process. S yi! The devices consist of 8 bit shift register, latch, AND-GATE we WS & Constant Current Drivers. Wee FEATURES SSOP20-P-225-0.65A © Constant Current Output : Can set up all output current Weight : 0.14 (Typ.) with one resistor for 80 to 150 mA. @ Constant Output Current Matching : CURRENT CURRENT HIGH / Low | OUTPUT-GND | watcHiNG | MATCHING | OUTPUT CURRENT VOLTAGE (MAX.) BIT) LOT) 215.0% 270 mA @ Maximum Clock Frequency : f¢_K = 15 MHz (Cascade Connected Operate, Topr = 25°C) @ 5V C-MOS Compatible Input @ Package : SSOP20-P-225-0.65A 980910EBA1 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. sm products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1999-03-16 1/11
PIN CONNECTION (TOP VIEW) Oo LOGIC-GND 1 208 Vop SERIAL-N 2 19 BE R-EXT clock 3 18 ff SERIAL-OUT1 sLATCH 4 17 ISERIAL-uT2 HIGH/LOW 5 16 VENABLE 1B62715FN POWER-GND 6 15 fl POWER-GND ouTo 7 14 fl OUT7 ouTl is 13 §OuT6é ouT2 9 12 OUTS ouT3 J 10 a1 flouTa BLOCK DIAGRAM ouTo out ouT7 re) ° 2) REXT © O 0) a) JENABLE O <> 13 1 a 1 Q Q Q sto sto st _D /ATcH © d>— = an DQ O SERIAL-OUT2 SERIALIN © i> — © SERIAL-OUTI p CK p cK R p cK inl y TRUTH TABLE CLOCK /LATCH | /ENABLE | SERIAL-IN OUTO -- OUTS - OUT7 SERIAL-OUT Dn Dn - 5 Dn -7 No Change [Pn 6 a DOWN Dnt 2 Dn = 3 Dn=5 (Note) OUTO~OUT7 = on in case of Dy = H level and OUTO~7 = off in case of Dy = level. A resistor is connected with R-EXT and GND accompanied with outside, and it is necessary that a correct power supply voltage is supplied. 1999-03-16 2/11
SERIALN : : : l : * : : LS ev /LATCH i i i i i : i Lt ov ENABLE a a a a re a Oe bv outo ————. wmNee rT Sa Off our PoE PoE: rm On + + + + + — ott ours —_ tt : H H i H H : : On our7 aS a a ee es SERIALOUT! ov SERIAL-OUT2 bv (Note) Latches are level sensitive, not rising edge sensitive and not syncronus CLOCK. Input of LATCH-terminal to H Level, data passes latches, and input to L level, data hold latches. Input of ENABLE-terminal to H level, all output (OUTO~7) do off. TERMINAL DISCRIPTION | PIN No. | PIN NAME FUNCTION | 5 _|HIGH/LOW It is the terminal which does switching for the big current/low current. | 6,15 |POWER-GND |GND terminal for current output. LOGIC-GND [GND terminal for control logic. | 2 _|SERIAL-IN Input terminal of a serial-data for shift-register. ; 3 | CLOCK Input terminal of a clock for data shift to up-edge. /LATCH Input terminal of a data strobe. Latches passes data with “H” level input of LATCH-terminal, and hold data with “L” level input. 7~10, . 1~14 OUTO~7 Output terminals. / ENABLE Input terminal of output enable. All outputs (OUTO~7) do off with “H” level input of ENABLE-terminal, and do on with “L” level input. | 18 _[SERIAL-OUT1 | YU PU F—-2OWDIF CF 0 SERIAL-OUT2 | Output terminal of a serial-data for next SERIAL-IN terminal. | 19 | R-EXT Input terminal of connects with a resister for to set up all output current. 5V Supply voltage terminal. 1999-03-16 3/11
EQUIVALENT CIRCUIT OF INPUTS AND OUTPUTS 1. /ENABLE terminal 2. /LATCH terminal R(UP) Yoo Yoo TENABLE JLATCH GND GND R(DOWN) 3. CLOCK, SERIAL-IN terminal 4. SERIAL-OUT terminal Yoo Yoo cock, eth F/F ae SERIAL-OUT SERIALIN DATA GND GND 1999-03-16 4/11
MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING UNIT Supply voriage Input Voltage -0.4~Vpp + 0.4 +150 (HIGH/LOW = “H”) Output Voltage VouT -0.5~ + 17.0 Clock Frequency 7 Sr [GND Terminal Current | Ienp| 7200 ——S—*d ma ee FN-type : 0.71 (FREE AIR, Ta = 25°C) Power Dissipation [Popo | FN-type - 0.96 (ON PCB, Ta= 25) | Thermal Resistance Rth (j-a) 2 730 (ON PCB) Cc/W Operating Temperature —40~ +85 Storage Temperature -55~ +150 (Note) FN type : Ambient temperature delated above 25°C in the proportion of 7.69 mW/°C Condition = On PCB (50 x 50 x 1.6mm Cu = 40%) RECOMMENDED OPERATING CONDITION (Ta = 25°C unless otherwise noted) Supply Voltage | Vo ff TO TST Output Voltage | vour fo = = 5. \\ DC 1 circuit 130 ‘ouT1 (HIGH/ LOW = “H”) Alch oO c \\ DC 1 circuit 2 mare utput Current IOUT2 (HIGH/LOW = “L”) SERIAL-OUTH, 2 [= [= [=] SERIAL-OUTT, 2 = [=| _10 | [o7op| — |voo + 03 | Input Voltage [-03 | — | 03vpp | * LATCH Pulse Width [100 [=f |_| CLOCK Pulse Width Cs [— | — | as_| ENABLE Pulse Width Vpp = 45~55¥ [i000 [| — [= [as «0 | — [= [a5 Hold Time for DATA [20 f= [| ns _| Set-up Time for LATCH [100 [= [= [as _] Hold Time for ENABLE | thold (L [6 [= |= [as] Vpp = 4.5~5.5V, Power Dissipation | Pp [Ta = 85° (FN-type On POH) | — | — | 050 | w_| 1999-03-16 5/11
ELECTRICAL CHARACTERISTICS (Ta = 25°C unless otherwise noted) TEST CHARACTERISTIC | SYMBOL CONDITION jm |r. | a. UNIT cult Input po 7D = | Vo | mp 1 Vv Voltage ee ET Output Leakage _ Coment 1 |VoH = 15.0V uA Output [SERIAL ion = T0mA C= =a, Vottage -OUTt, 2 ioL= + 1.0mA a Output Current 1 Rext = 5200, [| 31.7| 37.5] 43.1 ma | 1 |VcE=07V ayn HigH/Low = "tt [=| =15[s60]_ | dlow2 CESS |HigH/Low =H" ("= [a7s[ t60[%_| Supply Voltage 9 = _A9~ ° 9 Regulation % VDD 1 |Ta = -40~ +85°C +15] 45.0] %/V Pull-up Resistor [Riv(up) | , | 100 200] 400 Po 100 200400 Reg = OPEN _OUTO-7= off | — | 10] 20] supply | “OFF” [IoD (off 2 Rext = 2600 OUTO~7 = off [| — | 10.0] 15.0] Current Ipp (of 3_| 1 [Rext = 1609 OUTO~7 = off [| — | 160] 21.0] [oD (on) 2_| Rext = 1600 OUTO~7 = on | — | 33.0] 62.1] SWITCHING CHARACTERISTICS (Ta = 25°C unless otherwise noted) TEST CHARACTERISTIC SYMBOL CONDITION ra ve [a UNIT cult ; SIN-OUTn | — | 500] 1000] Propagation = Tarci-OUTA | [= [500 1000] pLH [500] ("L" To “H") ENABLE-OUTn | — | 500] 1000 CLK-SOUTA [= 30) 79] voo=50V | = T5900} F000] Propagation LATCH-OUTn Vee = 1.0V [ — | 500] 1000 Delay Time ‘tpHL Vin = Vpp. To ML ENABLE-OUTA ’ | — | 500] 1000] ("H" To “L") ViL = GND CLK-SOUTh Row = 2600 [=| 30] 70] Pulse Width RL = 320 LATCH tw LAT, /LAT lout = 125mA, [— | 10] 25] LATCH/SIN & SIN tor : 10% to 90% |— | 25] 50] LATCH /SIN LAT/SIN tpn: 50% to 10% | — | 0] 15] Maximum CLOCK Rise Time [tL 2 |tp: 50% to 90% [| — [| — | 10] ps | Maximum CLOCK Fall Time [te 2 [=| =] 10] zs | JOutput Rise Time tor | 2 | 300 | 600] 1000] ns | Output Fall Time [300 | 600] 1000] ns | 1999-03-16 6/11
‘pp { b 4 Yoo ouro (Q— o—(C] ENABLE ' lot H hus o—(} ciock ' = o—C} Taran our7 (>— o—C] seniain SERIALOUT, 2 [)—e Vive Vin R-EXT. L-GND P-GND O OO iret $ AC characteristic © aL ev Vop outro —D He VIL . CQ) Enaate H ® ne TAT out [D Cy seravin seriacourt, 2 ED R-EXT L-GND P-GND a VL O Ome J J 1999-03-16 7/11
- CLOCK-SERIAL OUT, OUTn tr tf twek LF 50% k| | 90% clock 50% 50% 50% 10% 10% tsetup _thold SERIAL IN 50% 50% tof ‘90% 90% SERIAL OUT, 50% 50% OUTh (current) | 10% 1096 ‘tpLH ‘toHL 2. CLOCK-/LATCH Lock 50% SERIAL IN "U" level = DATA HOLD /LATCH 50% tsetup 3. /ENABLE-OUTn TENABLE 50% 50% ourn 50% r\\ 50% (Current Wave Form) 1999-03-16 8/11
‘eo lout - DUTY CYCLE lout - DUTY CYCLE a 129 wD ee ARS set op | tt Pt te rzof ++ VV tN 4 : ) | | | INT TNT a a eee SO a a a 2 +4 pee ro
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a ae ee a E oH _ | | eeerin ty ty a a a oT a ee Se a a 3 a ~ 20| Voo = 50V tt, escoap vo-sov{ [| {| | [| [ [| qe noe Ff pee sto yeroe [ Tot tt tt | ee, EE | eoeace [PP] I B be Actwe Pr aera oLYce= a 0 “EEE tT et et a a 9 0 0 50 00 DUTY CYCLE (%) DUTY CYCLE (%) Ta - Pp " TTT TTT deers, @ Dhe DOCCPTCT TT 2 et ae s amon a of PN & “UST N TTT TT 5 oe Pitti T NINE EE TT = LLU NINETEETET ry Se eS NE =e LTO TINNEY 8 of LUT TT TT NATTY ee Oe ee eee oLLLEL TTT ET TEN a ae AMBIENT TEMPERATURE Ta (°C) LED DRIVER TB6270X SERIES APPLICATION NOTE R-EXT - IQUT R-EXT - IOUT 300; N | rT TT] I\\ a sop TPT TTT Sad a > xe Sa = mph Se | a Or \\ a 2 ‘ @ tue
2 CR Aeon
5 uncom =e NHI TTT . OCCT on ESSE Noe bo co Ft NS NS nit ino “ER Ht LEH tren too 1000 70000 700000 foo 3000 70000 R-EXT (2) REXT (2) 7999-03-16 9/11
TOTAL SUPPLY VOLTAGE (VED) This device can operate 0.7~1.0 V (Vo). When a higher voltage is input to the device, the excess voltage is consumed inside the device, that leads to power dissipation. In order to minimize power dissipation and loss, we would like to recommend to set the total supply voltage as shown below, VLED (total supply voltage) = VcE (Tr Vsat) + V¢ (LED Forward voltage) + Vo (IC supply voltage) When the total supply is too high considering the power dissipation of this device, an additional R can decrease the supply voltage. R= VLED - Vf (LED) - Vo (Min.) ~ Iq (Max.) x BIT (Max.) PATTERN LAYOUT This device owns only one ground pin that means signal ground pin power ground pin are common. If ground pattern layout contains large inductance and impedance, and the voltage between ground and LATCH, CLOCK terminals exceeds 2.5 V by switching noise in operation, this device may miss-operated. So we would like you to pay attention to pattern layout to minimize inductance. APPLICATION CIRCUIT = 3~4(V) Vp VLED AV) i CTH ae CJseriat.in out7 —D REXT GND __SERIALOUTI, 2 O O O PU nme ENABLE ouro — Be cLock ' rg TATCH ' CJseriat.in out7 —D REXT _LGND _seRiaLouri, 2 ai ~ 1999-03-16 10/11
SSOP20-P-225-0.65A Unit : mm 20 1 UBBRAA OAD A NY all = fo} € gg 8 no) iw FRAG WEEERE >} 4 10 7.0MAX 6.5+0.2 Nx 2 NTN o SU 2 fc oi] =8 < a 0.45+0.2 o Weight : 0.14g (Typ.) 1999-03-16 11/11