Logic IC

TB62713N

Toshiba Semiconductor

7 x 5 DOT DISPLAY DECODER AND DRIVER (COMMON CATHODE ROW CAPABILITY)

Manufacturer: Toshiba Semiconductor

Document: 25 Pages / 1,020Kb

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TOSHIBA Bi-CMOS INTEGRATED CIRCUITS SILICON MONOLITHIC TB62713N, TB62713F 7x5 DOT DISPLAY DECODER AND DRIVER (COMMON CATHODE ROW CAPABILITY) The TB62713N and TB62713F are multifunctional, compact, 7B62713N 7x5 dot matrix LED display drivers. Each of these ICs can directly drive and control one 7x5 _ dot matrix LED display. < aa The display shows the common cathode rows. Wh J rH es Row output uses a constant current, which is set using an Ni i \\ external resistor. The column output is standard PNP output. ‘ DIP24-P-300-1.7 A synchronous serial port connects the IC to the CPU. 5 300-1.78 . ‘ . 862713F The different modes of control provided by this device, 62713 including Duty Control Register Set, Digit Set, Decode Set and Standby Set, are all based on every 16-bit of serial data. < —— No =x FEATURES. © Control circuit power supply voltage SSOP24-P-300-1.00. : Vpp =4.5 to 5.5V Weight SDIP24-P-300-1.78 : 1.62g (Typ.) © Digit output rating $SOP24-P-300-1.00 : 0.329 (Typ.) : -17V/ -350mA @ Row output rating : 17V/50mA @ Built-in decoder : Decoding based on ASCII code. © Digit control function : Automatically turns on column output OUT-Cg to OUT-Cq4 in sequence. 961001EBA1 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. Ste products described in this document are subject to foreign exchange and foreign trade control laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1998-04-21 1/25

@ Maximum transmission frequency (for serial data transmission) : fcLK = 15MHz @ Row output (OUT-Rg to OUT-R¢) Output current can be set to 50mA using an external resistor. © Constant current tolerance (Ta=25°C, Vpp =5.0V) : Variation between bits= +7%, variation between devices (including variation between bits) = +15%, @VcEz=0.7V @ Package : 24-pin SDIP (SDIP24-P-300-1.78) 24-pin SSOP (SSOP24-P-300-1.00) PIN ASSIGNMENT (Top view) Voo 41 24 [J L-Gno pataan I] 2 23 f] bata.out cock 3 22 [ext Loa 4 21] test-our our-Ro 5 20 fl our-cy ourr: 6 19M our-cs, our-R2 7 18M vec our-r3 8 17 fl our-cy our-ra 9 16H our-cy our-Rs [] 10 15 our-co our-eg I] 11 va] test-in2 pono [] 12 13 [I rest-in1 1998-04-21 2/25

EQUIVALENT CIRCUIT DIAGRAM / BLOCK DIAGRAM clock > DATA-OUT DATAIN—J D 16bit Shift Register LOAD > 16bit D-type Latch CHARACTER SELECT

128 CHARACTERS

& € gs € § 4 6 6 4 6 So 8 es Yo 8 9 8 4 555 5 5 Duty-Controller L 38 86 6 6 144 44 fi Toit Bipolar Sbit Bipolar Constant-Current Source Drive OUT-Co~Ca Sink Driver R-EXT — OUT-Ro~Rg 1998-04-21 3/25

Few veer [pana [Cid [71 op“ powerpinOOSOSOSC edge. Load signal input pin. The data in the Dg to D415 bits of the 16-bit shift register. Are read on the rising edge of the load signal and the current load LOAD (LD) register is selected from among the Duty Register, the Decode & Digit Register, or Data Registers 0 to 3. The Dg to D7 bits contain data corresponding to the same registers just described, which are read on the load signal's falling edge. Row output pins. These pins output constant sink current. Connect [72 |P-6ND__| Ground pin for row output. ———SOSCS—~—SCSY 15, 16, 17, Column output pins. These pins output the Vcc pin voltage as a 19 20 ‘ OUT-Co to C4 |source current output. Connect these pins to the LED common ' anodes. [78 [Vee | Power pin for column output ————SSSSOSCS—SCSY [21 [TesT-OUT | Product test pin. In normal use, be sure to leave this pin open. | | |e [rater setmen spin rd ND when sting the arent 22 R-EXT . one ; resistor between this pin and GND when setting the current. devices are cascade-connected. 1998-04-21 4/25

tost_ [tone] | ' >| t i t oe = *PDso| ; : fey 50% 50% tpp CO 30% 90% 50% | t, CO 50% t#.CO OUT-Co~Ca 10% 10% 90% 30% OUT-Ro~Re 10% 10% DATA INPUT @ Transfer data to the DATA-IN pin on every 16-bit including address (8bits) and data (8bits). After the 16th clock-signal input following this data transfer, input a load signal from the LD pin. @ Input the load signal using an Active High pulse. The register address is set on the rising edge of the load pulse. On the subsequent falling edge, the data are read as data of the mode of the register. 1998-04-21 5/25

@ Data input (DATA-IN, CLOCK, LOAD) The data are input serially using the SERIAL-IN pin. The data input interface consists of a total of three inputs : SERIAL-IN, LOAD, and CLOCK. Binary code stored in the 16-bit shift register offers control modes including Duty Control Register Set, Digit Set, Decode Set and Standby Set. The data are shifted, starting from the MSB, on the rising edge of the clock. Cascade-connecting TB62713N or TB62713F devices provides capability for controlling a larger number of digits extensibility. The serial data in the 16-bit shift register are used as follows : the four bits D15 (MSB) to D12 select the IC operating mode (Table 1), while bits D11 (MSB) to Dg select the register corresponding to the operating mode (Table 2). Bits D7 to Dg (LSB) are used for detail settings such as number of digits in use, character settings in each digit, and light intensity of these. The internal registers are loaded on the rising edge of the LOAD signal, which causes loading of data from an external some into the D15 (MSB) to Dg bits of the shift register, operating mode and the corresponding register selection data. On the subsequent falling edge, the detail setting data of D7 to Dg (LSB) are loaded. Normally LOAD is Low. After a serial transfer of 16bits, the input of a High-level pulse loads the data. Note the following caution. Use the D415 to Dg setting and the D7 to Dg detail data setting as a pair. If just the D7 to Dg data are input without setting D15 to Dg an error condition may result, in which the device will not operate normally. The register settings will not be normal. If the current mode is set again by a new signal, the data for D15 to Dg must also be re-input. @ Operating precautions At power-on or after operation in Clear mode (in initial state), the data are reset. If the IC enters Normal mode after data are input and characters are specified, LEDs are lit according to the input data. Operating the IC in Blank mode (all lights off) or in All ON mode (all lights lit) does not affect the internal data. Setting the IC to Normal mode again continues the LED lighting in the state governed by the settings made immediately before mode change. Normal mode (not Shut Down, Clear, Blank, or All On mode) continues the operations set in Load Register mode. In Normal mode, operations are governed by any new settings msde in the Load register, as soon as the changed setting values are loaded. 1998-04-21 6/25

@ Operating modes (Table 1) These ICs support the following five operating modes : 1. Blank : Forcibly turns OFF the constant-current output both for data and digit setting. This mode is not affected by the values in bits D4 to Dg. 2. Normal : Used for display operations after the settings of the digits are complete. This mode is not affected by D1, to Dg. Note that setting this mode without making any other settings results in a blank display (all lights off). 3. Load Register : Used for the detail settings of the Duty Control Register and for inputting display data. D411 to Dg of the shift register are used for the detail settings of the digits currently being driven. (Table 2). 4. All On : Forcibly turns ON the constant-current data output. This mode is not affected by D411 to Do. 5. Standby : Used to set Standby state (in which internal data are not cleared) and to clear data (initialization). The settings in D3 to Dg determine the choice between standby state or initialization. Table 1 Operating mode settings REGISTER DATA INITIAL [D15]014]D13[D12] D11~Dg | D7~Da | D3~Dg [HEX CODE| SETTING BLANK NORMAL (OPERATION) [ofepoys| — |—- | — ~rr yl LOAD REGISTER ALL ON (OUT-Cy ALL ON) Pleat — ~- ~>-~s7|, | STANDBY fofrfofe; — [— |x | «xn [| X=Input H or L. "—"=Are not affected by the truth table. 1998-04-21 7125

@ Load Register Selection modes (Table 2) These modes select the register to provide the data to control the IC operation. The Load Register selection mode is determined by the settings of D15 to D12 and Dyq to Dg of the shift register 1. Duty Register : Sets the digit output duty cycle. Duty Settings can be made in 16 steps from 0/ 16 to 15/16. (Table 3) 2. Data Register : Sets 7x5 display characters. D7 to Dg are used to set the display characters. Table 2 Load register selection REGISTER DATA D15~D12[D11[D19] Dg [Dg | D7~Dg | D3~Do [HEX CODE TOAD DUTY REGISTER [2m [ofofolo| x | x | 20xn LOAD CHARACTER-DATA was TL [efefets] | x | ae | X=Input H or L. 1998-04-21 8/25

DUTY CONTROL REGISTER SETTINGS @ Duty Control Register detail settings and operation (Table 3) Writing 20H to D15~Dg and writing O~FH to D3~Dg sets the duty cycle shown in the following table for the digit-side source driver output. The duty cycle can be set in 16 steps. The initial setting is 15/16. After Data Clear, the setting is also 15/16. The current settings remain in force until changed (to the initial state, Data Clear state, standby state, or by reset execution). Table 3 Duty control register settings INITIAL | purvcvcte bpigcog [pms [bs] be] br] Dp [HBC CODE| SETTING [oe 20 T= opofolol ax] ‘| [ans 20 fo fofol i] axn | _—s a A a 7 arg 200 fo fo | 20xa | [se 20k f= fo ft fo ft] xs |_| [erie fo tft fol oxen |_| a0 of 20x rig 0 fo 2x9 [076 20 fof fol 20xan |_| A e620 20x | P5620 fo 20x paris 20k [20x] Psst 20x |_| X=Input H or L. "—"=Are not affected by the truth table. 1998-04-21 9/25

@ Standby mode settings and operation (Table 4) Writing 4H to D15~Dg and writing 0001 to D3~Dg sets Standby mode. Writing 4H to D15~Dg and writing 0001 to D3-Dg sets All Data Clear mode. Standby mode maintains the settings made immediately before this mode came in force, turns the output current OFF, and controls the bias current the internal circuits. Resets all settings to their initial states. Table 7 Standby mode settings REGISTER DATA D15~Dg | D7~Dg [D3 [D2 [Ds | Do [HEX CODE STANDBY (NO DATA CLEAR) [ 4H | — [o][o]o]|o] 4xxoH fAUL DATA CLEAR | #H | — [oo fo|1| axxn | X=Input H or L. "—"=Are not affected by the truth table. 1998-04-21 10/25

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2 COOsOCO | COmsO0Om | 0000000 | 0000000 | ammmm@e | Os00000 | 0000000 | bo00000

8 OOO00Gm | M§OOO0D | OOO—O00 | 0000030 | mlm | 0000000 | O000000 | O000000

3 {| )O0000m— | OO00s00 | OgOmO—0 | OO00000 | sammmmd | wg0000m | 0000009 | Comoooe o OO0Os00 | Cao50e5 ata fotsi DOO0080 | SOCOCm | gOsD0 le SCRe) COMOe g —|<|CODS LOS SaaGnan JOM O00 | Camm | OCCOSOm | BOOBS Cm COmU00s COmDSoR . COMOmCS | OSO00N0 | COmmmo0 | Cmm@Ommo | COOO0Om | SOOUmOm | OOCOOOm | OCO0ee gs Og000mm OCm@mmOS | Cmomomd | 0000000 | CO005m0 | SOO00mm | COO0GmD | CoEsooum fa Opec ONOO00— 0000000] Ommmm@ | 0000000 | gg§00000 | 0900005 | oomsoo0 a OO0s09m | §CO000s | SOD0509 | SO0sCGm | BCO000s | COm—090 | OO0000m | SO00soo

3 OCemmes COUSLOn Lies faeces AGHHRHS Pislacitl OOO0000 | OOMgO00

3 CES

lelel-lel=| F a I-I-lelele| : BSEEa x] - = BR EE 4 . pe |e [eye pe Te T= t=] ¢ 7998-04-21 12/25

DATA INPUT (Example 1 : Displays A to G, blinks F and G, and adjusts luminance.) Dis | D1 | D7 Rn~ “Cn~ DISPLAY ster |_9°,| <b | ~0a OUT-Ro~Rg | OUT-Co~C4 INFORMATION At power-on [1 [9070 | 0000 [roox DUTY =15/16 ALL BLANK [2 [0010 [0001 | 0100 | 0001 | OFF | OFF __|CHARACTER-DATA=A| ALL BLANK | [3 [0001 Poo pooxpoox] FF [oN | Normal [aA ——*d [4 [oot | 000% [0100 [0010 ON | ON _|GHARACTER-DATA=8| 8 —_—+ [6 [0010 [ 0001 | 0100 | 0100 | ON | ON |CHARACTERDATA=D| >= [7 [oor [0001 [0100 [0101 | ON | ON _|CHARACTER-DATA=E|__—& —_—+t [8 [ 0010 [ 0000 [0700 [0110 ON | ON _|CHARACTER-DATA=F| __F___| | 9 | 0000 | XXxXX]XXXx [XXXX BLANK ALL BLANK 10 [0010 | 0000 DUTY=8/16 0001 |XXXX|XXXX|XXxx] ON [ON | NORMAL F (MIDDLE BLIGHT)

0000 BLANK ALL BLANK

[12 [0010 | 0000 0100 [0111 | ON | OFF _|CHARACTER-DATA=G| ALL BLANK | | 13 [0001 |XXXX|Xxxx[xxxx] ON [ON | NORMAL G (MIDDLE BLIGHT) STANDBY STATE TRANSITION DIAGRAM POWER ON NORMAL OPE , i f "0 suut oown "".,, ALE ON CLEAR LOAD REGISTER “ye & BLANK A, LOAD REGISTER in 4 \\ sHUT DOWN / CLEAR LOAD REGISTER > B s. & BLANK ra - SHUT DOWN, BLANK ALL BLANK + normat _/ ‘LEDs lit (lit in accordance with & LOAD REGISTER (data input complete) TY (OPE. the input data) toy 1 vr T cear | # awn snut own “ON {NORMAL OPE NORMAL OPE. & BLANK ‘ _— LOAD REGISTER i \\ ALL ON } Load Register mode is used for AN ; the detail settings for the digit SSL? ‘output duty cycle, and for inputting display data. 1998-04-21 13/25

MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING Supply Voltage for Logic Circuits Yop 70 v Supply Voage OUT-Cg to OUT-C3 Output _ Current 'co 420 mA OUT-Rg to OUT-R¢ Output mA Current Output Current for Logic + Block loH/IOL $5 mA EASELS Operating Frequency Total Supply Current VDD mower Dissipation) TE2TTN w Operating Temperature -40~85 Storage Temperature -55~150

ELECTRICAL CHARACTERISTICS

(Unless otherwise stated, Vpp =5.0V, Vcc =5.0V, ReExT = 5800, Ta= -40 to 85°C) TEST CHARACTERISTIC SYMBOL TEST CONDITION an | ve. | ax UNIT CUIT SET NORMAL OPE. MODE, | R =5900 @OUT-Ro~Rg ALL 370 Perating Power Supply cct Rext =5900 ° one eurrent for Output SET NORMAL OPE. MODE, lec2 1 |RexT=5909 @OUT-Ro~Rg ALL 390 ON, Vcc = 12V, Ta = 25°C OUT-Cg to OUT-Cq NORMAL OPE. MODE, OUT-Rg to OUT-R¢ NORMAL OPE. MODE, 23.0 mA Output Sink Current VceE=0.7V, Rext = 5900 . OUT-Cg to C4 Output _ Leakage Current Neak1 ALL OFF MODE, Vcc =17V -20 LN OUT-Ro to Rg Output _ Leakage Current Neak2 ALL OFF MODE, Vcc =17V pe OUT-Cg to C4 Output NORMAL OPE. MODE, Voltage Vout louT-Cn = - 350mA 3.0 v 1998-04-21 14/25

CHARACTERISTIC SYMBOL TEST CONDITION ran | ve | max UNIT CUIT Save Fave’ Sma | oor] « [tanoey wove To=ase | — | — | a] oa | Current for Logic crs Poor |e Jasawewooetoaase | — | — [2s | wa . NORMAL OPE. MODE, Operating Power fox = 10MHz Supply Current for IppD3 DATALN : OUT-R ~Re = ON, mA Logic Circuits Ta=25°C . o~N6 ‘ High Input Current for \\ DATA-IN, LOAD & CLOCK : A Logic Circuits |H Vin =5V # Low Input Current for \\ DATA-IN, LOAD & CLOCK : A Logic Circuits IL Vin =0V # High Output Vorage | Voi | 6 [DATA-OUT, Iou=-TomA | 46 | —|— |, for Logic Circuits VoH2 | 6 |DATA-OUT, IoH = -1.02A | — | Vpo[ — | Low Output Voltage | Voir | 6 [DATA-OUT, IoL=1.0mA [— [-— [oat for Logic Circuits | Vow2 | 6 [DATA-OUT, IoH=1.0%A [ — [o1 | — | cearoono [ex [o famee® [= | [= [oe] 1998-04-21 15/25

SWITCHING CHARACTERISTICS (Unless otherwise stated, Vpp =5.0V, Vcc =5.0V, Ta = 25°C) [ome | oom freer [on on] CUIT Data Hold Time (D-IN-CLOCK) *DHO ns Data Setup Time (D-IN-CLOCK) ‘DsT ns Serial Output Dela’ fie coceooum | so |= fam | = | | = | | [low Clock Pulse Width [ tex, | — | ——*dY | 0 P| ns fecocevoany” texto || = = | = | (CLOCK-LOAD) Clock Load Time t (LOAD-CLOCK) LD-CLK ns OUT-Cg to OUT-C6 Output Delay Time tpp CO CL = 10pF US (LOAD-OUT-Cp) OUT-Cg to OUT-CE Output Rise Time t, CO CL = 10pF us (OUT-Cn) OUT-Cg to OUT-CE Output Fall Time t¢ CO C, = 10pF 1.0 us (OUT-Cn) OUT-Rg to OUT-Rq ol IES (LOAD-OUT-Rn) OUT-Rg to OUT-Rq ae CESS (OUT-Rp) OUT-Rg to OUT-Rq4 Eee fe [be [eff (OUT-Rp) 1998-04-21 16/25

RECOMMENDED OPERATING CONDITIONS (Unless otherwise stated, Vpp =5.0V, Vcc =5.0V, Ta= -40 to 85°C) TEST CHARACTERISTIC SYMBOL TEST CONDITION van | re. | max UNIT CUIT Supply Voltage for Output Block Vcc 15.0 v OUT-Rg to Rq4 Output _ Source Current 'co Vout =3.0V 280 | ma OUT-Cg to Cg Output _ Sink Current Vce=0.7V mA Logic block TEST CHARACTERISTIC SYMBOL TEST CONDITION va | re. | max UNIT CUIT High Input Current for iH |- | DATA-IN, LOAD & CLOCK, 1 | pa Logic Circuits Vin =Vpb Low Input Current for | DATA-IN, LOAD & CLOCK, 1 A Logic Circuits IL Vin =0V # High Input Voltage for 0.7 Logic Circuits VIH Vppb v Low Input Voltage for 0.3 Logic Circuits ViL Vpp v SWITCHING CONDITIONS TEST CHARACTERISTIC SYMBOL TEST CONDITION va | re. | max UNIT CUIT Data Hold Time Data Setup Time 4 (D-IN-CLOCK) DST Serial Output Delay _ Load Clock Time t ns (CLOCK-LOAD) CLKLD Clock Load Time t (LOAD-CLOCK) LocLK 1998-04-21 17/25

() lect Iec2 from CU 0 Leno [D>

i (<a -en ea (2) fosc from CU pO Leno [D> & Co * te0uT:D vst ‘Osc x QC} tena e-eno [| 1998-04-21 18/25

(3) IseG from CU. pO Leno [D> 8 = Rext [> 8 @®-houra Z o1ceD (@)—C] our-F oic-a [) (4) lleak1) Heak2 from CU. pO Leno [D> 8 = Rext [> ®-Gours = vc0D—-® 2 t Jour nN vee) ——— 2 1998-04-21 19/25

(5) Vout from CU. ae pp Leno (ID) tO ours = o60f[——w—+4 © & pours Face p—F C} ours TEIN p+ - TE-IN2 PGND Pat RL=10.70 Ipig = 0.284 Ipp1~3 Ipp1 : STANDBY me Din Dour Pp {opz RonMaL me CLK Rext ®

08 Fcuk = 10MHz Co * teour bp

ra OurA ZF DIGE RJ Vout: Vout : loH=—1MA, loL=1mA > ouTB -— o01G-D[) VoH2: VoL2 : |OH= ~ 144, lOL= 144A x 9 ae OUT-D bd DIG-C Saves C) te-in2 p-enp [) 1998-04-21 20/25

lout-Duty Cycle (TB62713N) lout-Duty Cycle (TB62713N) “COOL SOOT oL-EE EEE LLL COO COO ag LEE > a LEE i eee 2 OO Po ee 2 CELE © EEE EECEP eee © CCE Pa 38 oo} wow © ET TTT veces¥ TTT {tT T tty veces¥ [TTT TTT TT vf Meets CEEEEEET TT A ee yerecimn [TTT ELL | jeremy FT TTL TT TTT Lees ETT PT wee PP] oie Se ae ae ae TB oe SE ae BT Ee STB Duty Control Duty Control lout-Duty Cycle (TB62713F) lout-Duty Cycle (TB62713F) “COTA “COTTE LL EEE EEE eo LLLP COO COCO - wl LEE wl LEN Po eee 8 “CCCCCCCeeeeN 2 gf LOPE 2 gL FPN © CCPC © CCE ee 3B ol vow © ITT TTT oo oo of ees COPE A yerocomn [TT PTTL yevocmo [TT TT) {tty eee ree PE 0/16 3/16 6/16 9/16 12/16 15/16 0/16 3/16 6/16 9/16 12/16 = 15/16 Duty Control Duty Control 1998-04-21 21/25

EXTERNAL RESISTANCE AND OUTPUT CURRENT VALUES Rext - louT Ree ‘a NAHE lout (mA /bit) = 20 x (per (V)/Rext (Q)) SMALE TTT TTT UTNE 5 a tit & “HHTESsw T TTT tect ge | LTT | “SSL tT {LU REXT (KO) The following diagram shows the application circuit. Because operation may be unstable due to influences such as the electromagnetic induction of the wiring, the IC should be located as close as possible to the LED. The L-GND and P-GND of this IC are connected to the substrate in the IC. Take care to avoid a potential difference exceeding 0.4V at two pins. When executing the pattern layout, Toshiba recommends not including inductance components in the GND or output pin lines, and not inserting capacitance components exceeding 50pF between the RexT pin and GND. 1998-04-21 22/25

APPLICATION CIRCUIT EXAMPLE (Connection example) ® ELTA DD <3 tecesm eee “Tht et | toe od PU TB62713N, Re FL} 4H) TB62713F i) — __\\_ PRECAUTIONS for USING Utmost care is necessary in the design of the output line, Vcc (Vpp) and GND (L-GND, P-GND) line since IC may be destroyed due to short-circuit between outputs, air contamination fault, or fault by improper grounding. 1998-04-21 23/25

SDIP24-P-300-1.78 Unit : mm fo 24 13 3 fon os ee | |g g 8 ; 2 $F, a “‘LItItItiitsttittitititl a 1 12 22.5MAX. 22.040.2 po a ATNQUCATVAQUDIBIBIBIBLBNDT a] i libs Twat —— i 3 o Weight : 1.62g (Typ.) 1998-04-21 24/25

SSOP24-P-300-1.00 Unit : mm 24 13. ODAaAAAAaAAeAaD =) HHHHHHHHHHHH A} —¥ yy} ail| E gl g eg So 1 12 1.0TYP 0.4+0.1 fel020) 13.5MAX 13.0+0.2 w 8 2 eT = NL o a 0.525+0.2 ry Weight : 0.32g (Typ.) 1998-04-21 25/25

Product Information

TB62713N specifications and overview.

Summary

7 x 5 DOT DISPLAY DECODER AND DRIVER (COMMON CATHODE ROW CAPABILITY)

Description

7 x 5 DOT DISPLAY DECODER AND DRIVER (COMMON CATHODE ROW CAPABILITY)

Source title TB62713N Datasheet(PDF) - Toshiba Semiconductor

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TB62713N TOSHIBA | Alldatasheet

Document overview

Technical content

128 CHARACTERS

28 Ht ari 1 a io sa Ae Hin 5 Hin rh Piet sal = 5

2 COOsOCO | COmsO0Om | 0000000 | 0000000 | ammmm@e | Os00000 | 0000000 | bo00000

8 OOO00Gm | M§OOO0D | OOO—O00 | 0000030 | mlm | 0000000 | O000000 | O000000

3 OCemmes COUSLOn Lies faeces AGHHRHS Pislacitl OOO0000 | OOMgO00

3 CES

0000 BLANK ALL BLANK

ELECTRICAL CHARACTERISTICS

5 OUTD © DIG-C ice1, 2

08 Fcuk = 10MHz Co * teour bp

TB62713N specifications and overview.

More parts from the same family.