TB62710FN MARKTECH | Alldatasheet
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Technical content
TOAHIBA Bi-CMOS Integrated Circuit Silicon Monolithic TB62710P, TB62710F, TB62710FN 8-Bit Constant-Current LED Driver for Cathode Common LED The TB62710P, TB62710F and TB62710FN are specifically designed for use as LED and LED display (cathode-common) Constant-current drivers. The constant-current output circuits can be set up using an external resistor (IOUT = −90 mA max). These ICs are monolithic integrated circuits have been designed using the Bi-CMOS process. The devices consist of an 8-bit shift register, a latch, an ANDgate and constant-current drivers.
FEATURES
Constant-current output: A single resistor can be used to set any output current in the range −5~−90 mA. Maximum clock frequency: fCLK = 15 MHz (operating while connected in cascade, Topr = 25°C) 5-V CMOS compatible input Packages: P-type: DIP20-P-300-2.54A F-type: SSOP24-P-300-1.00 FN-type: SSOP20-P-225-0.65A Constant-output-current accuracy: Current accuracy Output − GND Voltage between bits between ICs Output Current (max) = 2.0 V (min) −5~−90 mA = 1.5 V (min) ±6% ±15% −5~−40 mA TB62710P TB62710F TB62710FN Weight: DIP20-P-300-2.54A: 2.25 g (Typ.) SSOP24-P-300-1.00: 0.33 g (Typ.) SSOP20-P-225-0.65A: 0.10 g (Typ.) Web: www.marktechopto.com | Email: info@marktechopto.com Company Headquarters
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Pin Assignment (top view) Block Diagram Truth Table CLOCK LATCH ENABLE SERIAL-IN OUT0… OUT5 … OUT7 SERIAL-OUT H L Dn Dn … Dn − 5 … Dn − 7 Dn − 7 L L Dn + 1 No Change Dn − 6 H L Dn + 2 Dn + 2 … Dn − 3 … Dn − 5 Dn − 5 X L Dn + 3 Dn + 2 … Dn − 3 … Dn − 5 Dn − 5 X H Dn + 3 OFF Dn − 5 Note 1: OUT0~OUT7 = ON when Dn = “H”; OUT0~OUT7 = OFF when Dn = “L”. In order to ensure that the level of the power supply voltate is correct, an external resistor must be connected between R-EXT and GND. GND SERIAL-IN LATCH CLOCK NC VCC OUT0 OUT1 VDD R-EXT SERIAL-OUT1 ENABLE SERIAL-OUT2 VCC OUT7 OUT6 P- & FN-types OUT2 OUT5 OUT3 OUT4 GND SERIAL-IN LATCH CLOCK NC VCC OUT0 OUT1 VDD R-EXT SERIAL-OUT1 ENABLE SERIAL-OUT2 NC OUT7 OUT6 F-type OUT2 OUT5 OUT3 OUT4 NC NC NC VCC SERIAL-IN LATCH R-EXT ENABLE I-REG Q ST D Q ST D D Q CK Q ST D D Q CK D Q CK CLOCK OUT0 OUT1 OUT7 SERIAL-OUT1 VCC VCC VCC D Q CK SERIAL-OUT2
Note 2: The latches circuit holds data by pulling the LATCH terminal Low. And, when LATCH terminal is a “H” level, latch circuit doesn’t hold data, and it passes from the input to the output. When ENABLE terminal is a “L” level, output terminal OUT0~ OUT7 respond to the data, and on & off does. And, when ENABLE terminal is a “H” level, it offs with the output terminal regardless of the data. SERIAL-IN LATCH CLOCK OUT0 OUT1 OUT6 ENABLE n = 1 SERIAL-OUT2 SERIAL-OUT1 OUT7 OFF OFF ON OFF OFF OFF ON OFF 5 V 0 V 5 V 0 V 5 V 0 V 5 V 0 V 5 V 0 V 5 V 0 V
Pin No. P/FN-Type F-Type Pin Name Function GND GND terminal for control logic SERIAL-IN Input terminal for serial data for data shift register CLOCK Input terminal for clock for data shift on rising edge LATCH Input terminal for data strobe When the LATCH input is driven High, data is latched. When it is pulled Low, data is hold. 6, 15 7, 18 VCC
0 V~17 V supply voltage terminal for LED
7~14 9~16 OUT0~OUT7 Output terminals ENABLE Input terminal for output enable. All outputs (OUT0~OUT7) are turned off, when the ENABLE terminal is driven High. And are turned on, when the terminal is driven Low. SERIAL-OUT2 Output terminal for serial data input on SERIAL-IN terminal SERIAL-OUT1 Output terminal for serial data input on SERIAL-IN terminal R-EXT Input terminal used to connect an external resistor. This regulated the output current. VDD 5-V supply voltage terminal 4, 6, 8, 17, 19 NC Not connected Equivalent Circuits For Inputs and Outputs ENABLE terminal LATCH terminal CLOCK, SERIAL-IN terminal SERIAL-OUT1 and SERIAL-OUT2 terminals CLOCK, SERIAL-IN VDD GND 300 k VDD ENABLE GND R (UP) VDD LATCH GND R (DOWN) 200 k VDD GND SERIAL-OUT1, 2
Maximum Ratings (Topr ==== 25°C) Characteristic Symbol Rating Unit Supply voltage VDD 0~7.0 V Supply voltage for LED VLED 0~17.0 V Input voltage VIN −0.4~VDD + 0.4 V Output current IOUT −90 mA Output voltage VOUT −0.4~17 V Clock frequency fCLK MHz VCC terminal current IVCC 1440 mA P-type (when not mounted) Pd1 1.47 F-type (when not mounted) 0.59 F-type (on PCB) Pd2 0.83 FN-type (when not mounted) 0.71 Power Dissipation (Note 3) FN-type (on PCB) Pd3 0.96 W P-type (when not mounted) Rth (j-a) 1 F-type (when not mounted) 210 F-type (on PCB) Rth (j-a) 2 150 FN-type (when not mounted) 175 Thermal Resistance (Note 3) FN-type (on PCB) Rth (j-a) 3 130 °C/W Operating Temperature Topr −40~85 Storage Temperature Tstg −55~150 Note 3: P-Type: Powes dissipation is derated by 12.5 mW/°C if device is mounted on PCB and ambient temperature is above 25°C. F-Type: Powes dissipation is derated by 6.7 mW/°C if device is mounted on PCB and ambient temperature is above 25°C. With device mounted on PCB of 60% Cu and of dimensions 50 mm × 50 mm × 1.6 mm FN-Type: Powes dissipation is derated by 7.7 mW/°C if device is mounted on PCB and ambient temperature is above 25°C. With device mounted on PCB of 40% Cu and of dimensions 50 mm × 50 mm × 1.6 mm
Recommended Operating Conditions (Topr ==== −−−−40°C ~85°C unless otherwise specified) Characteristic Symbol Conditions Min Typ. Max Unit Supply voltage VDD 4.5 5.0 5.5 V VCC1 VCC − VOUT > = 2.0 V, IOUT < = −90 mA Supply voltage for LED VCC2 VCC − VOUT > = 1.5 V, IOUT < = −40 mA 3.5 V Output voltage VOUT VCC common −17 V IOUT DC1 circuit −78 IOH SERIAL-OUT1, 2 −1.0 Output current IOL SERIAL-OUT1, 2 1.0 mA VIH 0.7 VDD VDD + 0.3 Input voltage VIL VDD = 4.5~5.5 V −0.3 0.3 VDD V LATCH pulse width twLAT VDD = 4.5~5.5 V 100 ns CLOCK pulse width twCLK VDD = 4.5~5.5 V ns ENABLE pulse width twENA VDD = 4.5~5.5 V 1000 ns Set-up time for DATA tsetup VDD = 4.5~5.5 V 100 ns Hold time for DATA thold VDD = 4.5~5.5 V 100 ns Clock frequency tCLK VDD = 4.5~5.5 V, Cascade operation 10.0 ns P-type Pd1 When not mounted 0.76 F-type Pd2 0.43 Power Dissipation FN-type Pd3 Topr = 85°C On PCB 0.50 W
Electrical Characteristics (Topr ==== 25°C, VDD ==== 5 V, VCC ==== 17 V unless otherwise specified) Characteristic Symbol Test circuit Conditions Min Typ. Max Unit Output leakage current ILEAK VCC = 17.0 V −10 µA VOH IOH = −1.0 mA 0.4 Output voltage SERIAL-OUT 1, 2 VOL IOL = 1.0 mA 4.6 V IOUT1 VCC = 4 V, VOUT = VCC − 2.0 V REXT = 360 Ω −62.1 −73.0 −83.9 IOUT2 VCC = 4 V, VOUT = VCC − 2.0 V REXT = 620 Ω −34.0 −40.0 −46.0 Output current (including current skewing) IOUT3 VCC = 3.5 V, VOUT = VCC − 1.5 V REXT = 620 Ω −32.3 −38.0 −43.7 mA Current skew ∆IOUT Same as IOUT1, IOUT2 and IOUT3 ±1.5 ±6.0 Supply voltage regulation %/VDD Ta = −40~85°C REXT = 360 Ω 1.5 5.0 %/V Pull-up resistor Rin (Up) 150 300 600 kΩ Pull-down resistor Rin (Down) 100 200 400 kΩ IDD (OFF) All outputs = OFF REXT = OPEN 0.6 1.2 IDD (ON) 1 DATA = ALL “H”, All outputs = ON (no load) REXT = 360 Ω 7.5 10.0 VDD IDD (ON) 2 DATA = ALL “H”, All outputs = ON (no load) REXT = 620 Ω 4.0 7.0 ICC (OFF) DATA = ALL “L”, All outputs = OFF (no load) REXT = 620 Ω 0.5 1.0 Supply current VCC ICC (ON) DATA = ALL “H”, All outputs = ON (no load) REXT = 360 Ω 42.0 52.0 mA
Switching Characteristics (Topr ==== 25°C unless otherwise specifed) Characteristic Symbol Test circuit Conditions Min Typ. Max Unit CLK-OUTn LATCH -OUTn ENABLE -OUTn 200 450 Propagation delay time (“L” to “H”) CLK-SOUTn tpLH ns CLK-OUTn LATCH -OUTn ENABLE -OUTn 180 Propagation delay time (“H” to “L”) CLK-SOUTn tpHL ns CLK twCLK Pulse width LATCH twLAT ns Set-up time LATCH /SIN/ CLOCK tsetup ns Hold time LATCH /SIN/ CLOCK thold ns Rise time (Note 4) tr µs Slow clock Fall time (Note 4) tf µs Output rise time tor 110 ns Output fall time tof VDD = 5.0 V, VCC = 17.0 V VOUT = VCC − 2.0 V VIH = VDD, VIL = GND REXT = 620 Ω CL = 10.5 pF tor: 10~90% tof: 90~10% tpLH: 50~10% tpHL: 50~90% Set the switching characteristics according to the result of measuring the voltage waveform. 250 450 600 ns Note 4: If the device is connected in a cascade and tr/tf for the waveform is large, it may not be possible to achieve the timing required for data transfer. Please consider the timings carefully.
SERIAL-OUT1, SERIAL-OUT2 ENABLE OUT7 IIL, IIH VDD IDD VIL, VIH IOUT VCC ILED CL RL CL GND SERIAL-IN LATCH CLOCK OUT0 SERIAL-OUT1, 2 ENABLE OUT7 VDD VCC Function Generator VIH, VIL RL CL Logic input waveform VDD = VIH = 5.0 V VIL = 0 V tr = tf = 10 ns (10% to 90%)
- CLOCK, SERIAL OUTn 2. CLOCK, LATCH 3. ENABLE – OUTn tr 90% SERIAL-IN CLOCK OUTn tr 50% 10% 10% twCLK 50% 50% 50% tsetup SERIAL-OUT1 90% tof 50% 10% tor 10% 50% 90% tpLH tpHL 50% tpLH 50% tpHL SERIAL-OUT2 50% 50% tpLH tpHL LATCH twCLK SERIAL-IN CLOCK 50% tsetup 50% 50% 50% twLAT OUTn ENABLE tpLH 50% 50% 50% 50% tpHL ON OFF
Reference Data (duty curves ++++ package power dissipation) Duty (%) IOUT (mA) Duty (%) IOUT – Duty on PCB Duty (%) IOUT (mA) IOUT – Duty on PCB Topr (°C) Pd – Topr Pd (W/IC) 0.5 1.0 1.5 2.0 100 P-type FREE AIR F-type ON PCB FN-type ON PCB 100 1000 10000 25°C VDD = 5.0 V, VCE = 2.0 V, VCC = 17.0 V 5000 500 IOUT (mA) = 85°C Topr = −40°C REXT (Ω) IOUT (mA) IOUT – REXT IOUT – Duty on PCB IOUT (mA) 100 Topr = 85°C, VCC − VOUT = 2.0 V Tj = 120°C TB62710FN TB62710F TB62710P 100 Topr = 60°C, VCC − VOUT = 2.0 V Tj = 120°C TB62710FN TB62710F TB62710P 100 Topr = 25°C, VCC − VOUT = 2.0 V Tj = 120°C TB62710FN TB62710F TB62710P
The bottom figure shows an application circuit. For best results, this IC should be operated with VO = 2.0 V. VO (V) = VCC − VOUT = VCC − Vf (LED) − VCE1 When VCC is high and the Vf of the LED is low. VO is also high , the increase in power dissipation may in turn adversely affect the IC’s output current. In this case, reduce the voltage by connecting an external resistor. In this way the IC’s output current can be stabilized. (max) number BIT (max) OUT I (min) O V f V CC V R It is looked for. it is also possible that the IC will operate in an unstable manner due to the inductance of the wiring. To counter this, it is recommended that the IC be situated as close as possible on the PCB to the LED module, and as far as possible from other ICs. Otherwise, there is the risk that the IC will malfunction. Application CPU SCAN VDD n R GND SERIAL-IN LATCH CLOCK OUT0 SERIAL-OUT1, SERIAL-OUT2 ENABLE OUT7 VCC VCC R-EXT GND SERIAL-IN LATCH CLOCK OUT0 SERIAL-OUT1, SERIAL-OUT2 ENABLE OUT7 VCC VCC R-EXT VLED = 5~17 (V) VO = VCC − Vf (LED) − VCE1 For best results, operate at VO = 2.0 V VCE1
Operation may become unstable due to the electromagnetic interference caused by the wiring and other phenomena. To counter this, it is recommended that the IC be situated as close as possible to the LED module. If overvoltage is caused by inductance between the LED and the output terminals, both the LED and the terminals may suffer damage as a result. There is only one GND terminal on this device when the inductance in the GND line and the resistor are large, the device may malfunction due to the GND noise when output switchings by the circuit board pattern and wiring. To achieve stable operation, it is necessary to connect a resistor between the REXT terminal and the GND line. Fluctuation in the output waveform is likely to occur when the GND line is unstable or when a capacitor (of more than 50 pF) is used. Therefore, take care when designing the circuit board pattern layout and the wiring from the controller. This application circuit is a reference example and is not guaranteed to work in all conditions. Be sure to check the operation of your circuits. This device does not include protection circuits for overvoltage, overcurrent or overtemperature. If protection is necessary, it must be incorporated into the control circuitry. The device is likely to be destroyed if a short-circuit occurs between either of the power supply pins and any of the output terminals when designing circuits, pay special attention to the positions of the output terminals and the power supply terminals (VDD and VLED), and to the design of the GND line.
質量: 2.25 g (標準)
質量: 0.33 g (標準)
質量: .0.10 g (標準)
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