TB62706BN TOSHIBA | Alldatasheet
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TOSHIBA Bi-CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC TB62706BN, TB62706BF 16BIT SHIFT REGISTER, LATCHES & CONSTANT CURRENT DRIVERS The TB62706BN, TB62706BF is specifically designed for LED TB62706BN and LED DISPLAY constant current drivers. This constant current output circuits is able to set up external resistor (IOUT =5~90m<A). (Note) < <r This Ic is monolithic integrated circuit designed to be used LR J 1 tert | together with Bi-CMOS process. { in \\ ) \\ The devices consist of 16bit shift register, latch, AND-GATE and Constant Current Drivers. SDIP24-P-300-1.78 TB62706BF FEATURES. © Constant Current Output: Can set up all output current oo with one resister for 5 to — _— 90ma. Qee™ @ Maximum Clock Frequency : fo_K=15 (MHz) (Cascade Connected Operate, Topr=25°C) SSOP24-P-300-1.00B . Weight @ 5V C-MOS Compatible Input SDIP24-P-300-1.78 : 1.22g (Typ.) : SSOP24-P-300-1.00B : 0.32g (Typ.) @ Package : SDIP24-P-300-1.78~1.778mmPitch~ (TB62706BN) SSOP24-P-300-1.00B~1.0mmPitch~ (TB62706BF) @ Constant Output Current Matchong : OUTPUT-GND CURRENT VOLTAGE MATCHING _| OUTPUT CURRENT Por 6.0% | 5~90ma | (Note) (Note) TB62706BF can be used under limited Pp! (Pp 1.04W, with PCB) 961001E8A1 @ TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook. sm products described in this document are subject to foreign exchange and foreign trade control laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. @ The information contained herein is subject to change without notice. 1999-02-16 1/13
PIN CONNECTION (Top view) np (1 241) Voo SERIAL-IN [J 2 23 [] R-EXT cLock 73 22 [] SERIAL-OUT vaTcu Ja 21 f] enagle ouTo 5 20) ouT1s ouTi 6 19f] ouT14 our2 47 18 f] OuT13 ours [8 17] ourr2 ouTa 9 16] OuTI1 outs J 10 15} outro ouré 11 147] outs ouT7 412 13] ouTs BLOCK DIAGRAM ouro oun our7 fo) fo) fo) 0 a) a) ENABLE O—q> q H ae 1 sto stp sto Tarr oO—d> 4 a seriaLin O—] > DQ DQ -----—}D Q © SERIAL-OUT re cK } ck bck cock o> a TIMING DIAGRAM ov seraun Dt Lt Lt lt ov —e——— eet wv oi 3V — sv ware Ly ov ou + ft +t +t +t ft tf ft ft ft ott om ot to to tototoaog i On Off ours on ToT H i a oT on senal-our YAP LLL \\ ay a (Note) Latches are level sensitive, not rising edges sensitive and not syncronus CLOCK. Input of LATCH-terminal to H Level, data passes latches, and input to L level, data hold latches. Input of ENABLE-terminal to H level, all output (OUTO~15) do off. 1999-02-16 2/13
| PIN No. | PIN NAME FUNCTION | 1 [GND _[GND terminal for control logic. | 2 | SERIAL-IN _|Input terminal of a serial-data for shift-register. Input terminal of a clock for data shift to up-edge. TATCH Input terminal of a data strobe. Latches passes data with “H” level input of LATCH-terminal, and hold data with “L” level input. [3-20 [OUT=T_[Outputtermina SSS 1 ENABLE Input terminal of output enable. All outputs (OUTO~15) do off with “H” level input of ENABLE-terminal, and do on with “L” level input. SERIAL-OUT |Output terminal of a serial-data for next SERIAL-IN terminal. R-EXT Input terminal of connects with a resister for to set up all output current. SV Supply voltage terminal TRUTH TABLE CLOCK LATCH ENABLE | SERIAL-IN OUTO -* OUTS - OUT7 SERIAL-OUT pup Tn Dts pup | KT Ona | nga Png Dnt3 DOWN Dn+2 = Dn-5 = Dni3 DOWN (Note) OUTO~15=0n in case of Dy =H level and OUTO~15 = off in case of Dp =L level. A resistor is connected with R-EXT and GND accompanied with outside, and it is necessary that a correct power supply voltage is supplied. EQUIVALENT CIRCUIT OF INPUTS AND OUTPUTS 1. ENABLE terminal 2. LATCH terminal Yoo Yoo ‘ENABLE: TATA GND GND 3. CLOCK, SERIAL-IN termina 4. SERIAL-OUT terminal Yoo Voo LOCK, LATCH DATA ‘SERIAL-IN ‘SERIAL-OUT GND GND 1999-02-16 3/13
MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING Supply voltage lout | Sim Output Voltage -0.5~17.0 Clock Frequency i GND Terminal Current | Iend | 74a0———~d Sma P Dissipati 1.78 (BN-type : ON PCB, Ta =25°C) w ower Dissipation 7.00 (BF-type : ON PCB, Ta=25°C) . . BN : 70 (BN-type : ON PCB) °, Tharmal Resistance Rth (j-a) BF : 120 (BF-type : ON PCB) C/W Operating Temperature Storage Temperature —55~150 (Note) BN-type : Ambient temperature delated above 25°C in the proportion of 14.2mW/°C BF-type : Ambient temperature delated above 25°C in the proportion of 8.3mW/°C RECOMMENDED OPERATING CONDITION (Ta = - 40~85°C unless otherwise noted) Supply Voltage a Output Voltage Vour | | — | 80 [io OuTn, be Tera «ds | — | a | Output Current SERIAL-OUT [| — [| — [| 10] 0.7 vi Vin DD Vpp +03 Input Voltage Vv pm ff 2 | = Iv | Yop TATCH Pulse Width [too [ — [as | CLOCK Pulse Width [sof — | — [os | ENABLE Pulse Width [as00 [= | — [ns | Set-Up Time for DATA Vpp=45~5.5V «of — | — | ns | Hold Time for DATA thold (D 20 — P= [ns | Set-Up Time for LATCH [700 [= [ns] Clock Frequency [fcuk [Cascade operation | — | — | 70.0 | mie | cin oti Ta = 85°C (BN-type) [| — | — | 0292 | rower eee [ro frasese rues [= = oso] 1999-02-16 4/13
ELECTRICAL CHARACTERISTICS (Vpp =5.0V, Ta = 25°C unless otherwise noted) TEST CHARACTERISTIC SYMBOL | CIR- CONDITION TYP. | MAX. | UNIT CUIT “H" Level V Ta = -40~85°C 07 V Input eve 1H a= Vpp DD Vv Volt . sin [rien fw [a fenenee dow] — [ae Output Leakage Current | Ton | — |Vou=150V b= f= 0 |_| Output | <eeiar our LYOL |= [lor=toma———SC~dT — P — | yy Voltage [Vou | — lon= -1.0mA [asp — || Output Current 1 (include current) torr __| = |Vce=04v [matching | 397 | 295 | 45, | 19 =40mA, = + + 9 Pos [= [eesor [fez Toa [75 [os | Output Current 2 (include current) 19 =75mA, _ + + 9 Current Skew] Alo_2 | — [lozzene RexT = 2500 | - | +15 | +6.0 % Supply Voltage 9 _ = — AD ~ RR 9 Regulation %/VDD RexT =4700, Ta= -40~85°C 5.0 | %/V Pull-Up Resistor [ave [= [80300 [60 || lipo (of 1] — [Raq =OPEN, OUTI~8=off | — | 06] 12] sane vor” Lipp (off) — [Rexr=4700, our~e=off | 35] 58| a0] Supply ipp (ofp 3] — |Rext=2500, OUTI~B= off Tipp tonal — 1Rexr=2500, ourI=8son | 180 | 28.3 | 385 | 1999-02-16 5/13
SWITCHING CHARACTERISTICS (Ta =25°C unless otherwise noted) TEST CHARACTERISTIC SYMBOL CONDITION sn. |v. | ax UNIT cult papagation TATCH-OUTh | — | 1200] 1500 CL" to bie ENABLE-OUTn | ‘tH | — | 1200] 1500] CLK-SOUT | — | 30] 70} __ [CLK-OUThA [| — | 700] 1000 Propagation |TATcH-OUTn Vpp =5.0V | — | 700] 1000| Delay Time =| tp ; ns CH to "1" [ENABLE-OUTA Vee =0.4V | — | 700] 1000] CLK-SOUT ViH=Vpb | — | 30] 70] Pulse Width tw cK, CLK | — |Vi_= GND [= | 20] 30] ns _| use ie [LATCH tw Lat. LAT | — |Rext=4700 |= {tof 25] ns | Set-up Time ViL=3.0V [= | 2s] so] ns _| for LATCH R= 650 [= | 25] 50] ns_| Hold Time thold (L CL= 10.5pF p= {of 15] ns | for LATCH thold (C ee ee [Maximum CLOCK Rise Time| tr | — | P= |= [10] ps | Maximum CLOCK Fall Time | ty «Ys — ‘| | — | — | 10] xs | Output Rise Time [tor | = | | 150 [300] 600] ns _| Output Fall Time [top | — | | 150 [300] 600] ns _| 1999-02-16 613
‘oof Vop outot_) re) o—( ENABLE : "OL tnt / oho : o—C}seriat.in seriaout ()——O Yiu Yi R-EXT GND OO tref 1 AC characteristic Vop RL | i q ‘SW-MATRIX Pees : 2) Be TATCH ours] C)seRIAL-N SERIAL-OUT[(_) REXT GND OO i " PRECAUTIONS for USING Utmost care is necessary in the design of the output line, Vcc (Vpp) and GND line since IC may be destroyed due to short-circuit between outputs, air contamination fault, or fault by improper grounding. 1999-02-16 7/13
- CLOCK-SERIAL OUT, OUTn te tt tw ck. LF 50% k| | 90% clock 50% 50% 50% 10% 10% tsetup (© thold (C) SERIAL IN 50% 50% tof ‘90% 90% SERIAL OUT, 50% 50% UTA (current) | 10% 1096 ‘tpLH ‘toHL 2. CLOCK-LATCH ~ — om XT) TATCH | \\ 50% tsetup (L) 3. ENABLE-OUTn ENABLE 50% 50% outn 50% IY 50% 1999-02-16 8/13
lout - Duty Cycle (TB62706BN) lout - Duty Cycle (TB62706BF) a ee s-_ + 1} Pro ft a_i yrs 0 fT Vo =0.7 yy | wf} ttt tT Nvo=10 ap—__| 1 At ft Ing 4 = wl a ee eT Se a a a a A a ee ee a a SS | a a a Sg DS a a | a 5 ‘rr 5 Oa 2. a BF 020 Vop=5v a ee | Vopesv ee 20 ee aol 22? a | Tj =120°C (Max.) a | Tj= 120°C (Max.) r | | | | | | to] Bbit Active es | tg} Bbit Active a Tan25°C es Te=25% ee a ec | ol | A | 0 20 20 60 20100 ° 70 20 60 30 Too Duty Cycle (%) Duty Cycle (%) louT - Duty Cycle (TB62706BN) lout - Duty Cycle (TB62706BF) * a i sop a eS) FS oor sof a OV FR pot oS a a | Se ae ee 2 ool) NP RIN Sag A OS Sg a a a a Sag a a a oh rr coh Ft N= 10 3 “EPP oa 5 Noe i 3 yf 1 0" Ss ar a SS Vop=5v | Vop=5v ss | ao) 12° ee | 20 ee | T= 120°C (Max) FF T= 120°C (Max) [J to] Sbit Active es a a | jo] Sbit Active [+f vo-20 mf Taxcorc a a | Ta=60" oe ol es | A | 0 20 20 60 0 100 0 20 20 60 80 700 Duty Cycle (%) Duty Cycle (%) lout - Duty Cycle (TB62706BN) lout - Duty Cycle (TB62706BF) i ied eof sop > VARS ed a a ae a = of NN BONN g MTT NR 2 gf IY RS 2 sof RN a 6 SNE a a a op A NE 0-07 | 3 pe NS ro 3 yf PNET NS Vop=5v es en | 20) ,=20%¢ oxy | + 20] Yoo=5v PSU j= mT o-20 | 20 (vex) | to] Bbit Active ee to] abit active a Ta=25% a = 25% PT TT 9220 7 o a oe [97281] 0 20 40 60 80 100 0 20 40 60 80 100 Duty Cycle (%) Duty Cycle (%) 1999-02-16 9/13
Pp - Ta (TB62706BN) Pp - Ta (TB62706BF) COTTE COOLEY won “CON EE “ERLE | tr ne ssora EEN CEE st oy 2 \\ PTT PIN EE yt BCUOPE NCEE of i eT P PEN EE BPP NEE e JL PEN e “COPCLENLLELL LLL a TELL ot] TT EST SEEEEEATAEE Pe eee Ere 7riiti iit Sc Ta (°C) Ta (°C) LED DRIVER TB6270X SERIES APPLICATION NOTE
100 RExT - louT
A A 2 UC 2 “CON TO T es es a a a CS le (Lr 100 200 300 500 1000 2,0003,000 5,000 REXT (0) Fig. 1 TTT *42'799-02-16 10/13
[1] Output current (IQuT) lOUT is set by the enternal resistor (R-EXT) as shown in Fig.1. [2] Total supply voltage (VLEp) This device can operate 0.4~0.7V (Vo). When a higher voltage is input to the device, the excess voltage is consumed inside the device, that leads to power dissipation. In order to minimize power dissipation and loss, we would like to recommend to set the total supply voltage as shown below, VLED (total supply voltage) —VcE (Tr Vsat) + Vf (LED Forward voltage) + Vo (Ic supply voltage) When the total supply is too high considering the power dissipation of this device, an additional R can decrease the supply voltage (Vo). Vie =3~4 (V) Yop “a ENABLE ouro y cies | Cyarc 1 Wh A " Cseriavin ours) R-EXT GND __SERIAL-OUT “ LT] ng ENABLE ouTol) reo i ra LATCH ' Cy seriaun ouris) EXT GND__SERIALOUT 7 ° [3] Pattern layout This device owns only one ground pin that means signal ground pin and power ground pin are common. If ground pattern layout contains large inductance and impedance, and the voltage between ground and LATCH, CLOCK terminals exceeds 2.5V by switching noise in operation, this device may miss-operate. So we would lile you to pay attention to pattern layout to minimize inductance. 1999-02-16 11/13
SDIP24-P-300-1.78 Unit : mm fo 24 13 3 foe oe eee oe | alg R 2 ) 3 N i Pod € LItItItittttitiiitli so 1 12 22.5MAX 22.010.2 po ) a WIC TAI es |_| 2 | lia leat oS Weight : 1.22g (Typ.) 1999-02-16 12/13
SSOP24-P-300-1.00B Unit : mm HAAARAAR RRA aa NI ) = o| Qe «| ol 2 1 ij 12 1.0TYP 0.40.1 10.20) 13.5MAX 13.0+0.2 a x a) GS BF rye oat o “8 o 70.15] ea z 0.4540.2 Weight : 0.32g (Typ.) 1999-02-16 13/13