TB62705CPG_09 TOSHIBA | Alldatasheet
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TOSHIBA Bi−CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC TB62705CPG, TB62705CFG, TB62705CFNG 8-BIT SHIFT REGISTER, LATCHES & CONSTANT-CURRENT DRIVERS The TB62705CPG / CFG / CFNG are specifically designed for LED and LED DISPLAY constant-current drivers. These constant-current output circuits can support the set-up of an external resistor (I OUT = 5~90mA). This IC is a monolithic integrated circuit designed to be used together with Bi-CMOS process. The devices consist of an 8-bit shift register, latch, AND-GATE and constant-current drivers. This devices are a product for the Pb free(Sn-Ag).
FEATURES
z Constant-current Output : current with one resistor for 5 to 90mA. z Maximum Clock Frequency : f CLK = 15 (MHz) (Cascade Connecte Operate, Topr = 25°C) z 5V C−MOS Compatible Input z Package : DIP16 −P−300−2.54A (TB62705CPG) SSOP16−P−225−1.00A (TB62705CFG) SSOP16−P−225−0.65B (TB62705CFNG) z Constant Output Current Matching: OUTPUT-GND VOLTAGE CURRENT MATCHING OUTPUT CURRENT PIN CONNECTION (Top view) TB62705CPG TB62705CFG TB62705CFNG Weight DIP16−P−300−2.54A : 1.11 g (typ.) SSOP16−P−225−1.00A : 0.14 g (typ.) SSOP16−P−225−0.65B : 0.07 g (typ.) GND 1 SERIAL-IN CLOCK OUTn 9 8 ENABLELATCH OUTn OUTn OUTn OUTn OUTn OUTn OUTn SERIAL-OUT R-EXT VDD Company Headquarters
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Note: Latches are level-sensitive, not rising edge-sensitive, and are not synchronized with the CLOCK signal. The data will pass through the latch circuit if the latch input is set at “H” level, and will be retained if the input is set at “L”. OUTn OUTn OUTn SERIAL-IN LATCH CLOCK OUT0 OUT1 OUT3 SERIAL-OUT ENABLE OUT7 5 V 0 V 5 V 0 V Off On 0 V 5 V 0 V 5 V Off On Off On Off 5 V 0 V
PIN No. PIN NAME FUNCTION
1 GND GND terminal for control logic
2 SERIAL −IN Input pin for shift register serial data
3 CLOCK Clock input terminal for data shift to up-edge. 4 LATCH Data strobe input terminal. Latches pass LATCH data with “H” level input and retain data with “L” level input. 5~12 OUTn Output terminals 13 ENABLE Input terminal for output enable. All outputs ( OUTn ) go off with ENABLE data input at "H" level and go on with data input at "L" level. 14 SERIAL −OUT Output terminal for serial data for the next SERIAL-IN terminal. 15 R −EXT Input terminal for connecting a resistor to regulate all output currents.
16 V DD 5-V supply pin of the IC
CLOCK LATCH ENABLE SERIAL −IN OUTn SERIAL −OUT UP L L D n+1 No change D n−6 DOWN X H D n+3 Off D n−5 Note: OUTn = on if D n = H level, and OUTn = off if D n = L level. An external resistor is connected with R −EXT and GND. Be sure to administer the correct power supply voltage. INPUT/OUTPUT EQUIVALENT CIRCUITS 1. ENABLE terminal 2. LATCH terminal 3. CLOCK, SERIAL−IN terminal 4. SERIAL−OUT terminal
MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC SYMBOL RATING UNIT Supply Voltage VDD 0~7.0 V Input Voltage VIN −0.4~VDD + 0.4 V Output Current IOUT 90 mA Output Voltage VCE −0.5~17.0 V Clock Frequency fCK 15 MHz GND Terminal Current IGND 720 mA 1.47 (CPG−type : FREE AIR, Ta = 25°C) Power Dissipation PD 0.78 (CFG / CFNG−type : ON PCB, Ta = 25°C) W 85 (CPG−type : FREE AIR, Ta = 25°C) Thermal Resistance Rth (j−a) 160 (CFG / CFNG−type : ON PCB, Ta = 25°C) °C / W Operating Temperature Topr −40~85 °C Storage Temperature Tstg −55~150 °C Note: CPG type: For an ambient temperature above 25°C, the derating is 11.8 mW/°C. CFG and CFNG type: For an ambient temperature above 25°C, the derating is 6.3 mW/°C. RECOMMENDED OPERATING CONDITION (Ta = −40~85°C unless otherwise stated) CHARACTERISTIC SYMBOL CONDITION MIN TYP. MAX UNIT Supply Voltage VDD ― 4.5 5.0 5.5 V Output Voltage VOUT ― ― ― 15.0 V IO OUTn , DC 1 circuit 5 ― 88 IOH SERIAL −OUT ― ― 1.0 Output Current IOL SERIAL −OUT ― ― −1.0 mA VIH ― 0.7 VDD ― VDD +0.3 Input Voltage VIL ― −0.3 ― 0.3 VDD V LATCH Pulse Width tw LAT 100 ― ― ns CLOCK Pulse Width tw CLK 50 ― ― ns ENABLE Pulse Width tw EN 4500 ― ― ns Set-up Time for DATA tsetup (D) 60 ― ― ns Hold Time for DATA thold (D) 20 ― ― ns Set-up Time for LATCH tsetup (L) 100 ― ― ns Hold Time for LATCH thold (L) VDD = 4.5~5.5 V 60 ― ― ns Clock Frequency fCK Cascade operation 10.0 ― ― MHz Ta = 85°C (CPG−type FREE AIR) ― ― 0.82 Power Dissipation PD Ta = 85°C (CFG / CFNG−type ON PCB) ― ― 0.40 W
ELECTRICAL CHARACTERISTICS (VDD = 5.0 V, Ta = 25°C unless otherwise stated) CHARACTERISTIC SYMBOL TEST CIR− CUIT CONDITION MIN TYP. MAX UNIT "H" Level V IH ― ― 0.7 VDD ― V DD Input Voltage "L" Level V IL ― ― GND ― 0.3 VDD V Output Leakage Current IOH ― V OH = 15.0 V ― ― 10 µA VOL ― I OL = 1.0 mA ― ― 0.4 Output Voltage S −OUT VOH ― I OH = −1.0 mA 4.6 ― ― V IOL1 ― V CE = 0.7 V 34.1 40.0 45.9 Output Current 1 IOL2 ― V CE = 0.4 V REXT = 470 Ω (Include skew) 33.7 39.5 45.3 mA Current Skew ∆IOL1 ― IO = 40 mA, VCE = 0.4 V REXT = 470 Ω ― ±1.5 ±6.0 % IOL3 ― V CE = 1.0 V 64.2 75.5 86.8 Output Current 2 IOL4 ― V CE = 0.7 V REXT = 250 Ω (Include skew) 63.8 75.0 86.2 mA Current Skew ∆IOL2 ― IO = 75 mA, VCE = 0.7 V REXT = 250 Ω ― ±1.5 ±6.0 % Supply Voltage Regulation % / VDD ― R EXT = 470 Ω, Ta = −40~85°C ― 1.5 5.0 % / V Pull−Up Resistor R IN (up) ― ― 150 300 600 k Ω Pull−Down Resistor R IN (down) ― ― 100 200 400 k Ω IDD (off) 1 ― R EXT = OPEN, 7 ~OUT0 = off ― 0.6 1.2 IDD (off) 2 ― R EXT = 470 Ω, 7 ~OUT0 = off 3.5 5.8 8.0 "OFF" IDD (off) 3 ― R EXT = 250 Ω, 7 ~OUT0 = off 6.5 10.7 15.0 IDD (on) 1 ― R EXT = 470 Ω, 7 ~OUT0 = on 7.0 12.0 18.0 Supply Current "ON" IDD (on) 2 ― R EXT = 250 Ω, 7 ~OUT0 = on 10.0 22.0 32.0 mA
SWITCHING CHARACTERISTICS (Ta = 25°C unless otherwise stated) CHARACTERISTIC SYMBOL TEST CIR− CUIT CONDITION MIN TYP. MAX UNIT SIN−OUTn ― 1200 1500 LATCH −OUTn ― 1200 1500 ENABLE −OUTn ― 1200 1500 Propagation Delay Time (“L” to “H”) CLK−SOUT tpLH ― ― 30 70 ns SIN −OUTn ― 700 1000 LATCH −OUTn ― 700 1000 ENABLE −OUTn ― 700 1000 Propagation Delay Time (“H” to “L”) CLK−SOUT t pHL ― ― 30 70 ns CK t w CLK ― ― 20 30 Pulse Width LATCH t w LAT ― ― 10 25 ns L−H ― 25 50 Set−up Time for LATCH H−L tsetup ― ― 25 50 ns L−H ― 0 30 Hold Time for LATCH H−L t hold ― ― 0 30 ns Maximum CLOCK Rise Time tr ― ― ― 10 µs Maximum CLOCK Fall Time tf ― ― ― 10 µs Output Rise Time tor ― 300 600 1000 ns Output Fall Time tof ― VDD = 5.0 V VCE = 0.4 V VIH = VDD VIL = GND REXT = 470 Ω IOUT = 40 mA VL = 3.0 V RL = 65 Ω CL = 10.5 pF 150 300 600 ns
Utmost care is necessary in the design of the output line, V CC (VDD) and GND line since the IC may be damaged due to short-circuits between outputs, air contamination faults, or faults caused by improper grounding. OUTn OUTn OUTn OUTn
- CLOCK−SERIAL OUT, OUTn 2. CLOCK−LATCH 3. ENABLE−OUTn OUTn (current) OUTn
Iout-Duty Cycle(TB62705CFG/CFNG) Iout-Duty Cycle(TB62705CFG/CFNG) Iout-Duty Cycle(TB62705CFG/CFNG) Iout-Duty Cycle(TB62705CPG) Iout-Duty Cycle(TB62705CPG) Iout-Duty Cycle(TB62705CPG)
LED DRIVER TB6270X SERIES APPLICATION NOTE 1:CFG/CFNG ON PCB 2:CFG/CFNG FREE AIR 3:CPG FREE AIR
[1] Output current (I OUT) IOUT is set by the external resistor (R−EXT), as shown in Fig. 1. [2] Total supply voltage (VLED) This device can operate on 0.4~0.7 V (VO). When a higher voltage is input to the device, the excess voltage is consumed inside the device, which leads to power dissipation. To minimize power dissipation and loss, we recommend that the total supply voltage be set as follows: V LED (total supply voltage) = VCE (Tr Vsat) + Vf (LED forward voltage) + VO (IC supply voltage). When the total supply is too high in the light of the power dissipation of this device, an additional resistor (R) can be used to decrease the supply voltage (VO). PATTERN LAYOUT [3] Pattern layout This device has only one ground pin, i.e., the combined signal ground pin and power ground pin. If the ground pattern layout contains a large amount of inductance and impedance, and the voltage between the ground and LATCH or CLOCK terminals exceeds 2.5 V due to switching noise, the device may not operate correctly. Be sure to pay attention to pattern layout to minimize inductance. OUTn OUTn OUTn OUTn
Weight: 1.11 g (Typ.)
Weight: 0.14 g (Typ.)
Weight: 0.07 g (Typ.)